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Messages from 101475

Article: 101475
Subject: Re: Book Software for XC3190A?
From: tuxfriend <tuxfriend@arcor.de>
Date: Mon, 01 May 2006 22:47:26 +0200
Links: << >>  << T >>  << A >>
> I have a moderately old copy of Foundation 2.1 around on CD. It is from
> circa 2000, and claims to support the XC3100A family of devices. I think
> Xilinx has the old versions of their software available on their website
> somewhere. But I would agree with others who are trying to talk you out
> of bothering with these old devices.

There are many old links to the Xilinx website to the old software.
But the oldest version that is available is the webpack 3.3 and there is no
more support for XC3000. For a new bigger design there is no question to
use the new devices. But sometimes when I have a little project, the
XC3190A is the right size - and I have over 100 of this...
I would be very interested of a copy of your old copy ;)


Article: 101476
Subject: quartus 5.1 assignment_defaults.qdf
From: brehob@gmail.com
Date: 1 May 2006 14:08:50 -0700
Links: << >>  << T >>  << A >>
Hello,
While I'd swear I had this working at one point, two of us are finding
that Quartus 5.1 (under Linux) is ignoring the assignment_defaults.qdf
file in the project directory for pin assignments.  If we put the
assignments in the appropriate .qsf file things work just fine.

Has anyone gotten this to work in 5.1 under Linux?  Anyone had the same
problem?

Thanks,
Mark


Article: 101477
Subject: Re: ISE 8.1 Comment Bug, Very hideous
From: "Andy Peters" <Bassman59a@yahoo.com>
Date: 1 May 2006 14:50:11 -0700
Links: << >>  << T >>  << A >>
Eli Hughes wrote:
> Eli Hughes wrote:
> > The following code was shown to me by a collegue.  All of the logic has
> > been removed for clarity (and to protect IP).  The Synthsizer reports 3
> > errors that some of the signals are not declared as input, inout or
> > output.    If you remove the line comments in front of the input and
> > output declarations, the program synthsizes as expected.
> >
> > 8.1  YUCK!!
> >
> > -Eli
>
>
> Oops, here is the verilog code:
>
> module Main(SysReset,Zero,ClkInput, UZBEERX, ROW_Q1, COL_Q1, ROW_Q2 ,
> COL_Q2 , ROW_Q3 , COL_Q3 , ROW_Q4,COL_Q4,PSUP,PSUPo);
>
> /*inputs outputs registers wires*/
> 	input					SysReset;
> 	output				Zero;
> 	input					ClkInput;
> 	input					UZBEERX;
> 	output	[12:0]	ROW_Q1;	// row select quadrant1
> 	output	[12:0]	COL_Q1;	// column select quadrant1
> 	output	[12:0]	ROW_Q2;	// row select quadrant2
> 	output	[12:0]	COL_Q2;	// column select quadrant2
> 	output	[12:0]	ROW_Q3;	// row select quadrant3
> 	output	[12:0]	COL_Q3;	// column select quadrant3
> 	output	[12:0]	ROW_Q4;	// row select quadrant4
> 	output	[12:0]	COL_Q4;	// column select quadrant4
> 	output	[3:0]		PSUP;
> 	output	[3:0]		PSUPo;
>
> endmodule

Quick question: why aren't you using the modern ANSI-C-style
declarations?

-a


Article: 101478
Subject: Re: Async FPGA ~2GHz
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 02 May 2006 10:02:13 +1200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

>>>As you linearly decrease the voltage you get a cubic improvement in
>>>power consumption. So at 0.6-V we got 400-MHz performance on our
>>>prototype but with an 87 percent reduction in power consumption.
>>
> In my book it is f x C x Vsquared. Where does the third power come
> from?
> Physics is physics, even when it runs asynchronously.

Let's see:

1.93-GHz @ 1.2V
400-MHz  @ 0.6V

(0.4/1.93)*(0.6/1.2)*(0.6/1.2)= 0.052, or 5.2%.

He mentions 13%, but that value will include static Icc,
so it looks like, to a rough first iteration :

(5.2% Dynamic(calc) + 7.8% Static(inferred) = 13%(measured).

Assumed: Thermal equilibrium in their measurements.

However, because MHz has changed a better performance metric is energy.
( "cubic improvement in power consumption" is not the whole story,
as it does come at a cost.. )

ie at 400MHz, it will take 4.825x as long to complete
a multi cycle calculation (assumes a Burst/sleep scheme),
and their Static Icc content has reduced the energy ratio to 0.62725.

[An ideal device with no Static Icc, and following the Physics, would
have an energy ratio of 0.2509]

  If you transfer that energy back to a battery, then the regulator 
choice becomes important.

  Duty cycles and Idle.max ratios also matter, because that sets average
die temperatures and Static Icc will suffer with 'C, and also MHz drops
as well.

-jg




Article: 101479
Subject: Re: ML403 ZBT SRAM
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Mon, 1 May 2006 15:33:02 -0700
Links: << >>  << T >>  << A >>
I have a ML402 ZBT RAM running, however, how can I help you? You do not 
describe your problem.

Brad Smallridge
AiVision dot com



Article: 101480
Subject: Re: design optimization
From: Eric Smith <eric@brouhaha.com>
Date: 01 May 2006 16:48:32 -0700
Links: << >>  << T >>  << A >>
Rob wrote:
> Aren't you and Xilinx developing a new line of FPGA's called "The Crystal 
> Ball Series"?  Parallel psychic processing that transcends the sphere of 
> phsyical science or knowledge.

So *that* is what that recent Xilinx patent on LUTs with negative 100 ps propogation delay
is all about.  Daisy-chain enough of those, and you could really do some amazing things!

Given how exotic the materials needed to fabricate these parts are, I expect that they
will be priced too high for my budget.

Eric

Article: 101481
Subject: BFM and ISE simulator
From: "Fizzy" <fpgalearner@gmail.com>
Date: 1 May 2006 17:04:16 -0700
Links: << >>  << T >>  << A >>
Can anybuddy tell me how can i make BFM work with ISE simulator or
Active-HDL simulator. Actually these are the ONLY options we have.

I would really apperitiate as i am stuck and i want to simulate my
custom IP is having right bus transaction with PLB

Thanks 

Faraz


Article: 101482
Subject: Re: ISE 8.1i for Linux ?
From: Daniel O'Connor <darius@dons.net.au>
Date: Tue, 02 May 2006 11:17:02 +0930
Links: << >>  << T >>  << A >>
Markus Kuhn wrote:

> Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de> writes:
> (A certain competitor has figured out already a while ago how really easy
> using an FPGA USB programming cable can be made under Linux:
> 
>   http://www.altera.com/support/software/drivers/dri-usb_b-lnx.html

Pity their Linux design tools are not free though :)

> All that is really necessary is that root installs a tiny hotplug-invoked
> shell script that makes the /proc/bus/usb/ device file writeable for
> any user once the USB programming cable has been plugged in, and even
> that script could be included into the next hotplug release.)
> 
> Apart from the big hassle with the USB platform cable kernel driver,
> ise8.1i does seem to work reasonably well under SUSE Linux 9.3.

I would prefer a binary (eg CableServer) with an open spec (and open source
in my wildest dreams) which iMpact/ChipScope/etc talk to.

That way I could port it to FreeBSD and be able to do everything there
instead of having to use a third part programming tool :)

Would also mean I could debug CableServer so it doesn't eat all the CPU when
iMpact crashes.

I *did* file a web case on it :)

-- 
Daniel O'Connor software and network engineer
for Genesis Software - http://www.gsoft.com.au
"The nice thing about standards is that there
are so many of them to choose from."
  -- Andrew Tanenbaum
GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8C

Article: 101483
Subject: Re: Quartus and source control
From: "Derek Simmons" <dereks314@gmail.com>
Date: 1 May 2006 19:31:18 -0700
Links: << >>  << T >>  << A >>
Is there a recommended source control system?

Thanks,
Derek


Article: 101484
Subject: Re: Quartus and source control
From: "Subroto Datta" <sdatta@altera.com>
Date: Tue, 02 May 2006 02:48:13 GMT
Links: << >>  << T >>  << A >>
Quartus files can be stored in any source code control system. All source 
files needed to create and compile a project are text files. We have 
customers and internal users  who have versioned Quartus projects with CVS, 
Clearcase, Perforce, RCS.... The only binary file is the .qws (workspace 
file) files that contains the locations of the window settings when the 
Quartus UI executable (quartus.exe) is closed..The .qws file is not needed 
for compilation.

Hope this helps,
- Subroto Datta
Altera Corp.

"Derek Simmons" <dereks314@gmail.com> wrote in message 
news:1146537078.892378.252860@e56g2000cwe.googlegroups.com...
> Is there a recommended source control system?
>
> Thanks,
> Derek
> 



Article: 101485
Subject: Re: Quartus and source control
From: "KJ" <kkjennings@sbcglobal.net>
Date: Tue, 02 May 2006 04:22:18 GMT
Links: << >>  << T >>  << A >>
> Apart from that, there is yet another problem. Some of the VHDL files
> in the project are generated automatically by SOPC builder. Strictly
> speaking, these are not source files, and I don't want to add them to
> the source control system (they're already there at their source
> locations).

The 'source files' for things that flow through SOPC Builder are the .PTF 
file(s).  If you develop your own unique Avalon components then those 
components will each have their own .PTF file.

Whether you develop your own components or are only integrating existing 
components via SOPC Builder, the system .PTF file is where all this 
information gets stored so at a minimum that .PTF file would need to be 
included in the sources with a build script needed to then transform the 
.PTF file into VHDL.

KJ



Article: 101486
Subject: Re: design optimization
From: "David M. Palmer" <dmpalmer@email.com>
Date: Mon, 01 May 2006 23:11:28 -0600
Links: << >>  << T >>  << A >>
In article <qhk6951f3j.fsf@ruckus.brouhaha.com>, Eric Smith
<eric@brouhaha.com> wrote:

> Rob wrote:
> > Aren't you and Xilinx developing a new line of FPGA's called "The Crystal 
> > Ball Series"?  Parallel psychic processing that transcends the sphere of 
> > phsyical science or knowledge.
> 
> So *that* is what that recent Xilinx patent on LUTs with negative 100 ps
> propogation delay
> is all about.  Daisy-chain enough of those, and you could really do some
> amazing things!

The problem is that they only work until you program them.

However, since software and firmware are usually very late, that means
that you can deliver when marketing has promised your product, and it
will be out of warantee by the time you deliver the code and it stops
working.

-- 
David M. Palmer  dmpalmer@email.com (formerly @clark.net, @ematic.com)

Article: 101487
Subject: 50-th Anniversary of the CORDIC Algorithm
From: vladimir@baykov.de
Date: 1 May 2006 22:29:27 -0700
Links: << >>  << T >>  << A >>
 50-th Anniversary of the CORDIC  Algorithm

Exactly 50 years ago - in the 1956 - the first Jack Volder's
publication, describing
CORDIC algorithm:

 "Binary computation algorithm for coordinate rotation and function
generation ",
Report IAR-I 14S , Aeroelectronic group, June, 1956 Convair
was published.

Until now CORDIC technique is one of the most effective method of
solving
many computational problems.

Since 1956, when this method was firstly suggested, about 1500
publications were issued
in more than 30 countries: Australia, Canada, China, France, Germany,
Great Britain,
Greece, Hong-  Kong, India, Israel, Italy, Japan, The Netherlands,
Romania, Spain,
 Switzerland, Taiwan, United Kingdom, USA, the former USSR (mainly
 Russia, Ukraine, and Belorussia) and many others.  Only in the USA
similar researches
 have been made in about 25 universities.

 VLSI, based on CORDIC or its modifications, have been made in
 commercial production since from the beginning of 70-th.
 They were used for trigonometric and logarithmic functions
 evaluation in Hewlett-Packard's calculators: HP-35, 45, 65.
 Many other companies in different countries use this method
 in calculators for the same purpose.


 Still further field of application of CORDIC method are
 coprocessors INTEL: 8087, 80287, 80387 etc. included in
 the personal computers IBM PC.

 Firm TRW manufactures in commercial scale microcircuit
 TRW 2330 designed for plane rotations of coordinates,
 based on CORDIC technique, for digital signal processing.
 NEC corporation produces coprocessor VLSI  PD 72691, dedi-
 cated for elementary functions evaluation and coordinate
 transformation with floating point based on Volder's
 algorithms.


 Currently the major part of publications is related to using
 of CORDIC  algorithm for digital signal processing,
 many-dimensional coordinate transforms.
 The other part concerns with generalization of the CORDIC
 algorithm for solving linear systems equations, eigenvalue
 problems, statistical characteristics estimation.

 Many publications are related to application of the CORDIC
 and CORDIC-like algorithms and structures to robotics control,
 display processors, numerical control systems.

So I suggest firstly to create  the list of the bibliography in the
CORDIC field, like it was done in 1995 (now unfortunately it is a dead
link):

http://devil.ece.utexas.edu/cordic/index.html

One of the purpose of this coordination is not to duplicate the
research, that were made by the other authors many years ago, as say
in Russia
" not to invent the bicycle again".  Now due to the Internet it is very
easy to do.

The short lists of some publications in  the  CORDIC field are in:

http://en.wikipedia.org/wiki/CORDIC
http://de.wikipedia.org/wiki/CORDIC

All the investigations related to CORDIC method could be divided into
the following
groups:

- theory of properly CORDIC:  convergence:conditions and domain, error
analysis,  fixed and floating point representation, using of
nonbinary number
representation, unification of the  algorithms, methods of
acceleration,comparing with the  other methods

- expandings of CORDIC possibilities:  new kinds of functions of one
and two variables, functions of functions, three and four-dimension
coordinate transforms, solving linear and  nonlinear systems equations,
eigenvalue  and singular value problems

- implementation and application of CORDIC : standard and nonstandard
CORDIC architectures: on-line, pipeline, matrix, ROM-based,  VLSI
and ULSI, based on CORDIC, coprocessors, cal culators,
DSP processors, display processors,  robotic processors.

May be just now it`s the time  to have a look at
"Oldies-but-goodies" things at CORDIC and digit-by-digit area:

http://baykov.de/cordic1972.htm

http://baykov.de/cordic1975.htm

http://baykov.de/cordic1985.htm

http://baykov.de/cordic1992.htm


Article: 101488
Subject: RESET pin on NIOS II processor
From: alessandro.strazzero@gmail.com
Date: 1 May 2006 23:10:24 -0700
Links: << >>  << T >>  << A >>
Hi all,

I have a problem driving the RESET pin on a NIOS II processor. I expect
that when I pull LOW
this pin, the NIOS II processor makes a reset. But this is not true,
instead it reaches an
unstable condition.

Obviously, I make something of wrong, but where ? Do you have
experienced my same
situation ?

Best Regards

/Alessandro


Article: 101489
Subject: Re: XDL router info needed
From: Markus <none@nowhere.org>
Date: Tue, 02 May 2006 08:28:49 +0200
Links: << >>  << T >>  << A >>
potter wrote:
> hi ALL!!
> 
> i have a small query, FPGA geeks help me plz...
> 
> I have a question on the XDL report, i am acually trying to move a
> circuit by modifying the XDL file, btw i am using a Virtex II FPGA.
> 
> i have been successful in moving the slices and the pins to differnt
> locartion but not the routers, i was able to decode the slice info.,
> but not the routrers information. Please help me in decoding the
> routers info.
> 
> i have attached a small report on the routers info from the XDL file,
> the info that i have attached it the output net of the 2 input AND
> gate.
> =======================================================
> net "Z_OBUF" ,
>   inpin "Z" O1 ,
>   outpin "Z_OBUF" Y ,
>   pip R17C1 Y3 -> OMUX10 ,
>   pip LIOIR16 OMUX_NW10 -> IOIS_FAN_BX2 ,
>   pip LIOIR16 IOIS_FAN_BX2 -> O1_B1 ,
>   ;
> =========================================================
> 
> i want information on OMUX, FAN_BX2, and where i can get info on them,
> please help me with the routers info, i am stranded with this for the
> past 3 days.
> i will thanful if you could throw some light on it.

You can create a complete device description with xdl:

e.g.: xdl -report -pips v50pq240-5 v50pq240-5.xdlrc

It contains also information about the routing fabric. Beware, the file 
becomes awfully large

-Markus

Article: 101490
Subject: Re: Picoblaze C Compiler
From: "Francesco" <francesco.poderico@trendcomms.com>
Date: 2 May 2006 00:25:06 -0700
Links: << >>  << T >>  << A >>

electro wrote:
> Hi Francesco,
>
> Thanks for your effort,
>
> Take a look at the following article for accessing jtag port in a user
> design.
>
> http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm
>
> Best regards,
> Alper YILDIRIM
>
> > Does anybody know how to read/write the BRAM using the JTAG?
> > I need this to design the debugger....

Thank you electro.


Article: 101491
Subject: Re: Async FPGA ~2GHz
From: Kolja Sulimma <news@sulimma.de>
Date: Tue, 02 May 2006 09:27:21 +0200
Links: << >>  << T >>  << A >>
Peter Alfke schrieb:
>>>As you linearly decrease the voltage you get a cubic improvement in
>>>power consumption. So at 0.6-V we got 400-MHz performance on our
>>>prototype but with an 87 percent reduction in power consumption.
>>
> In my book it is f x C x Vsquared. Where does the third power come
> from?
> Physics is physics, even when it runs asynchronously.
> Peter Alfke

LOL.
f_max is a linear function of V. So you really get a cubic improvement
in thermal design power. But of course, you also get less performance.

Actually, who cares about the time the energy is spent in for dynamic
power? What really matters is Joule per operation which is C x V x V.
The number of operations depends on your algorithm. Once you know how
quickly you need a result you can select f to choose the amount of time
you want to spent that energy in.

Kolja Sulimma


Article: 101492
Subject: Deadlock PLB
From: "Fizzy" <fpgalearner@gmail.com>
Date: 2 May 2006 00:28:46 -0700
Links: << >>  << T >>  << A >>
Hi,

I need some direction and advice on integrating PLB slave. I have a
design which i want to integrate with processor using PLB. Any good
examples, tutorial or papers please. I am looking somthing like
designed in system generator

Thanks


Article: 101493
Subject: Re: FPGA Single LED Demos: FPGA board for a good ideas/suggestions
From: "Thomas Stanka" <usenet_10@stanka-web.de>
Date: 2 May 2006 00:52:03 -0700
Links: << >>  << T >>  << A >>

Antti Lukats schrieb:
[..]
> * 1 user LED for display
[..]
> Current list of Applications
[..]

I miss the obvious timeshare of your led. eg. 1s divided clock followed
by 1s "clock stable" status followed by whatever useful state comes out
of your design.
I used similar technics to get 24 bits on 4 LEDs visible.
Serialise some information and display it a measureable amount of time
with remarkable start/end of data (blinking seems for better than
stable signal for this task) would be the best for 1 LED.

bye Thomas


Article: 101494
Subject: Re: ML403 ZBT SRAM
From: "=?iso-8859-1?B?R2FMYUt0SWtVc5k=?=" <taileb.mehdi@gmail.com>
Date: 2 May 2006 00:57:31 -0700
Links: << >>  << T >>  << A >>
The problem is the following: I write some thing and when I read back I
get 32'd0.
When I make a post Place and route simulation all is ok.


Article: 101495
Subject: Re: Reset
From: "Jochen" <JFrensch@HarmanBecker.com>
Date: 2 May 2006 01:14:13 -0700
Links: << >>  << T >>  << A >>

> I am desging a state machine [..]

NEVER (again: NEVER) use async resets on statemachines!
Problem here is the "reset-release": you might end up with one FlipFlop
in "normal operation" and another one still in "reset state"
=> your statemachine might change from "one hot" into "two (too?) hot"
!!!


Article: 101496
Subject: Re: design optimization
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 2 May 2006 10:23:33 +0100
Links: << >>  << T >>  << A >>
"Eric Smith" <eric@brouhaha.com> wrote in message 
news:qhk6951f3j.fsf@ruckus.brouhaha.com...
>
> Given how exotic the materials needed to fabricate these parts are, I 
> expect that they
> will be priced too high for my budget.
>
> Eric
>

As someone has gone and blabbed this into a public newsgroup, I can reveal 
that Googling for "The Endochronic Properties of Resublimated Thiotimoline" 
will reveal more about the materials used.
HTH, Syms. 



Article: 101497
Subject: Re: Question about the ip I developed
From: "Symon" <symon_brewer@hotmail.com>
Date: Tue, 2 May 2006 10:33:37 +0100
Links: << >>  << T >>  << A >>
"Fred" <fred@nowhere.com> wrote in message 
news:4456098b$0$203$db0fefd9@news.zen.co.uk...
>
> It does however depend on general working practices within the company 
> such as is the occasional use of phones allowed for private use etc. 
> Whether lawful would include contractual and normal practice within the 
> company.  If a clause in your contract is openly abused, known and 
> accepted by management they cannot, on an ad-hoc basis, enforce it.
>
>
Hi Fred,
On a related note, did you see this in the Times yesterday?
http://business.timesonline.co.uk/article/0,,16849-2159286.html
HMRC might start taxing people to use work computers for personal email and 
browsing. According to the article, the tax would appear to be based on the 
cost of the computer. I guess you could just give everyone an old 20 PC to 
use for email!
Cheers, Syms. 



Article: 101498
Subject: Re: help me friend
From: "mohan" <kulkarku@math.net>
Date: 2 May 2006 03:03:13 -0700
Links: << >>  << T >>  << A >>
HI Kapil,
i woulkd like to suggest you some points.
1.what is the cost alloted to project?
2.what will be scope of project?means whether u want to download the
design into FPGA or only simulation on PC will serve ur purpose.
3.If ur going for implentation of design into FPGA,then u need to find
availabilty of FPGA along with the tool which supports this FPGA.

I hope if u get the answer of these things,ur project execution will
get easy.

Thanks


Article: 101499
Subject: Re: design optimization
From: Kolja Sulimma <news@sulimma.de>
Date: Tue, 02 May 2006 12:05:12 +0200
Links: << >>  << T >>  << A >>
Eric Smith schrieb:
> Rob wrote:
> Given how exotic the materials needed to fabricate these parts are, I expect that they
> will be priced too high for my budget.

The rumors must be true.
I asked my local distributor and they have not listed these parts.
Drawing from Spartan-2 and Spartan-3 experience this is a sure sign that
millions of pieces have been sold allready.

Kolja Sulimma



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2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

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