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Mike Treseler wrote: > Roger Bourne wrote: > >> How are constants implemented in an FPGA ? > > > All FPGA gates are synthesized in look-up tables. > A constant is synthesized with tables set for fixed output. > Think of it as wires to power or ground. > >> How many can be stored >> without causing bottlenecks (routing issues)? > > > Try it and see. > One constant bit per LUT is maximum. > > -- Mike Treseler and some routing resources have tie offs (to gnd or vcc) mostly on the gaskets of hard ip blocks. AurashArticle: 101201
As far as I've tried it, just enabling virtex-4 support in the MPD file doesn't help. The hwicap core uses the ICAP_VIRTEX2 component, which obviously is not supported on the Virtex-4. I didn't try changing the hwicap source to use the new ICAP_VIRTEX4 - that might work, since it still supports the 8 bit SelectIO interface. Regards -EnnoArticle: 101202
"Kolja Sulimma" <news@sulimma.de> schrieb im Newsbeitrag news:4448ed30$0$18265$9b4e6d93@newsread2.arcor-online.net... > Falk Salewski schrieb: >> I am doing some research on the reliability of microcontrollers software >> in >> comparison to hardware description languages for PLDs (CPLD/FPGA). >> >> Another interesting point is whether there are general benefits of one >> hardware regarding reliability, e.g. in an automotive environment. > > This all depends on the type of errors you are talking about. To get an > overall estimate will be really difficult. > > E.g. in automotives a big issue are real time constraint violations when > many things happen at once. You can easily specify the timing of most > hardware implemented algorithms with a granularity of nanoseconds > because there is real concurrency in the implementation. For uC it is > hard to get below tens of microseconds. > > Also, error detection and correction on ALUs, busses and memory is just > not available for commercial uC, while you can easily implement it for > your FPGA circuit. In theory a uC using all these techniques would be > more reliable, but if you can not buy it.... > (BTW: I talked to Bosch about that topic, and apparently the volume of > their orders is not big enough to have Motorola design such a uC for > them.) > > Formal model checking and property checking are becoming mainstream for > hardware development but are hardly ever used for software development. > > These are all factors in favor of FPGAs that are often not considered, > but I am sure that you come up with many reasons why uCs are more > reliable. (Less transistors for example) > > Kolja Sulimma > Thanks for your reply! I am also of the opinion that applications realizing hard real-time parallel functionality are easier to verify on a device allowing real parallelism. Possible integration of error detection and correction functionalities in FPGAs are also a big plus, in my opinion. Finally it seems that the aspect MCU vs. FPGA regarding reliability is, again, application dependent. Falk SalewskiArticle: 101203
Roger,
It's not exactly as simple as 'storing' them... Often a constant
input to some logic results in a simplifaction of the logic (e.g. 1 and x
just becomes x) and this is propogated through the design by the tools,
pruning off redundant logic etc. Any constant input to the base LUTs in
the design can be absorbed into the LUT contents and so is never
explicitly stored.
Or if you mean a lookup table of addressable constants they may be stored
in LUT ram or embedded RAM etc. depending on how they are coded.
A constant input to an embedded resource such as a RAM or multiplier will
be stored in slice registers (flip flops) within the device.
hth
cds
Roger Bourne (rover8898@hotmail.com) wrote:
: Hello all,
: I always wondered the following:
: How are constants implemented in an FPGA ? How many can be stored
: without causing bottlenecks (routing issues)?
: A quick scan of a Spartan3 indicated there is no ROM.
: Thx
: -Roger
Article: 101204c d saunter wrote: > Roger, > It's not exactly as simple as 'storing' them... Often a constant > input to some logic results in a simplifaction of the logic (e.g. 1 and x > just becomes x) and this is propogated through the design by the tools, > pruning off redundant logic etc. Any constant input to the base LUTs in > the design can be absorbed into the LUT contents and so is never > explicitly stored. > > Or if you mean a lookup table of addressable constants they may be stored > in LUT ram or embedded RAM etc. depending on how they are coded. > > A constant input to an embedded resource such as a RAM or multiplier will > be stored in slice registers (flip flops) within the device. > > hth > cds > Roger Bourne (rover8898@hotmail.com) wrote: > : Hello all, > > : I always wondered the following: > > : How are constants implemented in an FPGA ? How many can be stored > : without causing bottlenecks (routing issues)? > : A quick scan of a Spartan3 indicated there is no ROM. > > : Thx > : -Roger Actually, what I was pondering was how a set of constants that are suppose to be routed to the same operand of a multiplier (not at the same time, of course ), will be stored. > A constant input to an embedded resource such as a RAM or multiplier will > be stored in slice registers (flip flops) within the device. I guess, from the above, it means that the constants will stored in the same number of FFs as the number of bits of the constants. -RogerArticle: 101205
Roger Bourne (rover8898@hotmail.com) wrote: : c d saunter wrote: : Actually, : what I was pondering was how a set of constants that are suppose to be : routed to the same operand of a multiplier (not at the same time, of : course ), will be stored. : > A constant input to an embedded resource such as a RAM or multiplier will : > be stored in slice registers (flip flops) within the device. : I guess, from the above, it means that the constants will stored in : the same number of FFs as the number of bits of the constants. Roger I snarfed there - looks like they are stored in the LUTs not the FFs. There are several options for efficient storage of multiple constants for a multiplier etc. - in a Xilinx device the LUTs may act as 16x1 ROMs or RAMs or a 16 bit shift register. So if you wanted to store say 16 8 bit constants you would only need 8 LUTs and no extra routing overhead compared to having only 1 constant (except for the addressing) It's called Distrbuted RAM in the X. devices. If you only need cyclic and not random access to the data using the shift mode simplifies things - SRL16E. Involve the slice FF as well as the LUT and get an extra element... cdsArticle: 101206
Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:
> I encourage active feedback. If something is confusing, please let us
> know, as it will likely be confusing to others. Most of our best
> product and documentation ideas come from Xilinx users! Feel free to
> E-mail me directly for Spartan documentation or use the Feedback link
> from the Xilinx web site.
> http://www.xilinx.com/askx/feedback.htm
You might also try educating your FAEs. I specifically asked my local
FAE about using resistors to set the mode pins ("Why do the app notes
show direct connections to Vcc and Gnd, will resistors work ok?") and
he said that we could use 4.7 kohm resistors. Clearly this is not a
correct answer. Based on his reply I almost commited to a design that
would not have worked.
Like I said in my email, the info is mostly in the data sheet. But
there are many places where it seems to contradict itself and is so
scattered around that it would take a hour or more of intensive
searching to find all the relevant info. I actually sat down earlier
and did a search on "pull-up" trying to find all the info on the
pullups and the configuration pins. Even then I missed a few items
like the *only* place in the document where pull-ups on the mode pins
are mentioned, in the header for the pin description section that
covers the configuration pins.
I am asking that you not wait until a frustrated user reports your
mistakes. I am asking that you have someone look at what it takes to
find all the info that an engineer needs to configure these parts and
make the info consistent and more usable.
Article: 101207
Hi Roger,
"Roger Bourne" <rover8898@hotmail.com> wrote in message
news:1146145740.204076.326360@e56g2000cwe.googlegroups.com...
>
> what I was pondering was how a set of constants that are suppose to be
> routed to the same operand of a multiplier (not at the same time, of
> course ), will be stored.
>
> > A constant input to an embedded resource such as a RAM or multiplier
will
> > be stored in slice registers (flip flops) within the device.
>
> I guess, from the above, it means that the constants will stored in
> the same number of FFs as the number of bits of the constants.
Actually, a constant will rarely if ever be stored in a flip-flop, because
the tools will optimize away a flip-flop that never toggles and replace it
with a LUT driving the same value. Since there are only two possible values
for each bit, you need a minimum of two LUTs to give you "global" 1/0
signals, which can then be routed to the appropriate input(s). Your original
question seemed to be: does this cause routing congestion, and if so, how
can I avoid it? The answer is that the implementation tools will (read:
/should/) take care of this for you, by duplicating these constant drivers
appropriately
However, in your case, it sounds like you actually want a ROM to store your
multiplier coefficients. What you describe seems to be a number of constant
values, fed to a multiplexor that selects the appropriate constant given the
state of some other signals in your design. Now say that you have four
signals that determine which constant to use on the current clock cycle. For
each bit of the constant operand you need a function that determines what
that bit should be. This function is four-bit input, one bit output: i.e. it
is a LUT. So in fact all of your constants (up to 16 of them) will fit in N
LUTs, where N is the number of bits of the constant.
When the said four bits are a binary-encoded address, the LUT is effectively
being used as a conventional ROM.
In general, constants are rarely "stored" in any recognizable way in an
FPGA, except in ROM tables; rather, constant propagation at synthesis time
causes them to be absorbed into the surrounding logical expressions (often
simplifying them and reducing the area consumed by your circuit).
Cheers,
-Ben-
Article: 101208The xilinx template for V4 block ram with one read/write and one read port is not synthesizing correctly in the synplify. The original code maps into LUT rams. If we latch the input address and include a synthesize directive for block RAM then it creates two block RAM instead of 1 one for each read port. Why it is like that. Is there any way we can corrct this behaviour. Else how can we integrate a synthesized output from xilinx to synplify. That is i want to synthesize the module contaiig this RAM in xst correctly and then combine that synthesized output to synplify and then resynthesize it. Is this type of design flow possible. regards Sumesh V SArticle: 101209
On 26 Apr 2006 17:01:21 -0700, karrelsj@gmail.com wrote: >Has anyone implemented OR1K on a XUP? Download from opencores cvs the or1k/rc203soc module. It is a full implementation of OpenRISC 1200 over a Celoxica RC203 platform. It should be not very dificult to make it work over XUP, just adding a SDRAM controller. JavierArticle: 101210
Since I couldn't find a good mode file for editing Xilinx User Constraint File (UCF) in Emacs, I put one together. This is my first .el exercise, so nothing fancy here. It just includes color-highlighting of most of the keywords and several menu commands for inserting constraints that I commonly use. It is availabe at http://home.comcast.net/~jimwu88/tools/#ucf-mode HTH, JimArticle: 101211
Hello, Im my design I have an asynchr mux with two inputs and one output: - In1 - In2 - Out I have FFS on In1 clock, on In2 clock and on the Out clock. If the mux selects In1 clock then there is a datapath from the FFS(In1 domain) to the FFS(Out) domain. If the mux selects In2 clock then there is a datapath from the FFS(In2 domain) to the FFS(Out) domain. How should I constrain this? Now I (try to) group the elements: NET "In1" TNM_NET = FFS(*) "TNM_In1"; #60 MHz NET "In2" TNM_NET = FFS(*) "TNM_In2"; #50 MHz NET "Out" TNM_NET = FFS(*) "TNM_Out"; And I give a period constraint on these three clocks. I also give a from to constraint for In1 => Out and for In2 => Out. To be complete I constrain the length of the path from In1 to out and from In2 to out. The problem is that the worst case timing constraint is propagated through the mux, as a consequence my TNM groups are not correct: TNM_In1 = all FFS in the In1 and the out domain. TNM_In2 = all FFS in the In2 domain TNM_Out = empty My from-to constraints don't work because my tnm groups are not correct. Has anyone had a similar problem? best regards, Karel DArticle: 101212
WAU!!!! you do actually read and parse NCD files with your ADEPT tool !!! Great job! I did think I am one of a very few ones (outside Xilinx) who can do that :) AnttiArticle: 101213
Using a mux to select between two different clocks can cause you a lot of trouble, because you must avoid output glitches. I published an absolutely safe solution as the final item in "Six eeasy pieces" as TechXclusives (search for it on the Xilinx website.) That design is guaranteed to switch glitchfree between two free-running clocks, no matter when or how you activate the Select input. Peter Alfke, Xilinx ApplicationsArticle: 101214
Hi, We would like to drive LEDs using Ramp Waveforms using Xilinx CPLDs. Is it possible to write a driver and control the LED directly from CPLD or should an external D/A Converter be used?Article: 101215
That's what I thought, but then somebody told me that he might keep the electronics down there, at 175 degrees C, for a few weeks...Slowly cooking... Peter Alfke Have we gotten this thread away from -193 degrees, 0.2 V and 2 GHz, and related Marketing exuberances ?Article: 101216
you can use PWM modulation to control the LED current AnttiArticle: 101217
Hi, If i have 100 MHz clock how can i generate a 200 Hz with 50% duty cycle clock. Let me explain why i need this.... I have a custome IP which will be attached to PLB through IPIF block (using xilinx virtex4-FX). The IPIF uses bus clock for data to be put in FIFO. But my logic runs at 200 Hz. What i was thinking was to divide 100MHz clock to generate 200 Hz clock and then clock the data in from IPIF block to my logic. I think i have to use async FIFO to change the data between the different clock domains... I am not sure. Cna any buddy help in this.. ThanksArticle: 101218
Hey Fizzy man,
"Fizzy" <fpgalearner@gmail.com> wrote in message
news:1146153626.105056.203130@v46g2000cwv.googlegroups.com...
> If i have 100 MHz clock how can i generate a 200 Hz with 50% duty cycle
> clock.
Erm, a 19-bit counter?
Did you really mean 200Hz, or did you mean 200MHz? Why would your logic run
at 200Hz? You might want to think about using a clock-enable rather than a
separate 200Hz clock signal; that will be much easier for the design tools
to analyse.
> I think i have to use async FIFO to change the data between the
> different clock domains... I am not sure. Cna any buddy help in this..
If you really *did* mean 200Hz, then you would be best of using a simple
handshaking circuit, with enough buffering in it that the PLB doesn't get
tied up for milliseconds at a time by your incredibly slow circuit. This
could be an async FIFO, but it most likely doesn't need to be as complicated
as that (particularly given the huge differential between the two domains).
If you meant 200MHz, then you can generate that using a DLL (x2 output) and
the clocks will be related, so you can again manage without a FIFO (although
you will still have to design your circuit carefully).
-Ben-
Article: 101219"Fizzy" <fpgalearner@gmail.com> wrote in message news:1146153626.105056.203130@v46g2000cwv.googlegroups.com... > Hi, > > If i have 100 MHz clock how can i generate a 200 Hz with 50% duty cycle > clock. > > > Let me explain why i need this.... I have a custome IP which will be > attached to PLB through IPIF block (using xilinx virtex4-FX). The IPIF > uses bus clock for data to be put in FIFO. But my logic runs at 200 Hz. > What i was thinking was to divide 100MHz clock to generate 200 Hz clock > and then clock the data in from IPIF block to my logic. I think i have > to use async FIFO to change the data between the different clock > domains... I am not sure. Cna any buddy help in this.. > > Thanks I can see a gated clock being acceptable in this case without elaborate FIFO management. First, generate the 200 MHz clock with a toggle flip-flop toggled by the "wrap" from a divede-by-250,000 counter. The only trouble then is the (delayed) alignment of the 200 Hz generated clock. If you register your data in the 200 Hz domain, you can pick up that data one or two clocks later (once and only once) in the 100 MHz domain. For feeding from the 100 MHz domain to the 200 Hz, you need the data loaded to transfer into the 200 Hz domain 1 clock before the 200 Hz transition and maintained steady for two 100 MHz clocks. The transfer from 100 MHz output registers to 200 Hz input registers and 200 Hz output registers to 100 MHz input registers just need coordination to account for the gated clock skew. Just be sure to try to route the 200 Hz clock through a global buffer so the 200 Hz logic doesn't get confused at the gated clock edge. The logic may be only 200 Hz but the edges are fast and can beat the skew in a poorly distributed, non-global clock source which would be a bad thing.Article: 101220
Read the Logicore PCI v3.0 User Guide, Initiator 64-bit Extension, Additional Considerations, Monitor the Target Response. It appears the PCI spec requires that the user handle the switch from a desired 64-bit initiator transaction as a 32-bit sequence after the original attempt at a 64-bit transaction is terminated by the target. "sjulhes" <t@aol.fr> wrote in message news:44509f8a$0$12862$626a54ce@news.free.fr... > Hello, > > We have a design with master PCI DMA in 64 bits. This design implements > the > xilinx PCI 64/32 bits IP. > The problem is that our board should be plugged in various versions of the > PCI bus ( 64 bits/ 66 Mhz and 32 bits/ 33 mhz, 32 bits / 66 Mhz ). > > My question is : Is the IP abble to transparently handle the fact that the > board is plugged in a 32 or 64 bit PCI slot ? > > The goal is to have only one design that feeds the PCI master DMA section > with 64 bits data whether the bus is 32 or 64 bits wide. > > What are the limitations with this IP ? > Are there specifics configuration or design stuffs to add ? > > Thanks for your feedbacks. > > Stéphane. > > > >Article: 101221
jimwu88NOOOSPAM@yahoo.com wrote: > Since I couldn't find a good mode file for editing Xilinx User > Constraint File (UCF) in Emacs, I put one together. This is my first > .el exercise, so nothing fancy here. It just includes > color-highlighting of most of the keywords and several menu commands > for inserting constraints that I commonly use. It is availabe at > > http://home.comcast.net/~jimwu88/tools/#ucf-mode Works well. Thanks! -aArticle: 101222
I've been able to infer dual port block rams in synplify with no problems before. Can you post a test case that fails? Help us help you. AndyArticle: 101223
Its really 200 Hz. My application is very slow and the bus speed(PLB) is very fast. So my problem is to tranfer the data from very fast domain to very slow doamin. I am still looking for a easy solution.Article: 101224
Does any buddy knows what are the steps to bring a system generator model in to VHDL top level module. I have a simple logic implemented in system generator and i use NGC netlist to create netlist and Vhdl code fo that model. Now i i would have a top level model how can i bring sysgen model in it. I know a little that i have to instantiate it in top level but any one can give me any example... Thanks
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Compare FPGA features and resources
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