Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search

Messages from 101100

Article: 101100
Subject: Re: Max and Argmax across 1,000 unsigned 10-bit numbers
From: andrewfelch@gmail.com
Date: 25 Apr 2006 10:46:01 -0700
Links: << >>  << T >>  << A >>
Ahh, I see.  Thanks very much.  So it takes 10 LUT's to take the
maximum over two 10-bit numbers.  If pipelined, it can do this at a
throughput of 1 per clock cycle?  So ideally, performing 1,000 max
operations/10 cycles = 100 max operations per cycle, = 1,000 LUT's.

Thanks,
AndrewF


Article: 101101
Subject: Re: clock multiplication
From: dancedynamix@hotmail.com
Date: 25 Apr 2006 11:02:30 -0700
Links: << >>  << T >>  << A >>
Thank you for your response.

Could you detail how a PLL can be used in this instance?

How can I set the multiplication rate at 32?

Would it be able to deal with rapid changes in the input clock?

Thanks, Bob


Article: 101102
Subject: Re: clock multiplication
From: "unfrostedpoptart" <david@therogoffs.com>
Date: 25 Apr 2006 11:17:01 -0700
Links: << >>  << T >>  << A >>

dancedynamix@hotmail.com wrote:
> Thank you for your response.
>
> Could you detail how a PLL can be used in this instance?

Which FPGA?  What company?  You need to read about PLLs (or DCMs in
Xilinx).

>
> How can I set the multiplication rate at 32?

Depends on the PLL.
>
> Would it be able to deal with rapid changes in the input clock?

How rapid?  How quickly does it need to settle?

Anyway, your input clock is probably way to low frequency to work with
the PLLs/DCMs in FPGAs.  They are set up for multi-megaHertz clock
rates.  You will likely have to design an outboard PLL (4046?).

 David


Article: 101103
Subject: Re: clock multiplication
From: Rene Tschaggelar <none@none.net>
Date: Tue, 25 Apr 2006 20:39:48 +0200
Links: << >>  << T >>  << A >>
dancedynamix@hotmail.com wrote:

> Thank you for your response.
> 
> Could you detail how a PLL can be used in this instance?
> 
> How can I set the multiplication rate at 32?
> 
> Would it be able to deal with rapid changes in the input clock?

As said, forget the FPGA. Take a 4046. Then take
a VCO, such as a LTC6900 resistor set oscillator
and add a div32 divider in the form of 5 Flipflops
or a presetable counter.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

Article: 101104
Subject: 116 warnings... successive approximation register using both phases of clock by spliting them
From: "bad synchrounous assignment" <him.wanderer@gmail.com>
Date: 25 Apr 2006 11:44:58 -0700
Links: << >>  << T >>  << A >>
after compiling my project...116 warnings came ... i m new to VHDL..
gotta submit within 24 hrs
HELP>>SOS>>SOS

hello thr

hi! i am stuck up pretty bad with my project and need your immediate
assistance within 24hrs...... i have successive approximation register
using VHDL and simulated it in Altera: Quartus 2 5.0 web edition.. now
i have no errors but 116 warnings of all sorts plus output waveform is
not what i was expecting either... now  I tell you somethin regarding
how it shud work and if you can please see what all you can do to make
it run fine.... this is S.O.S.... save me man..........
I use a component called clock generator that provides me with two
clocks both in phase opposition to each other (VHDL description is
included in project).... so basically what i tried to do is to decrease
the number of clock cycles tht normally takes for successive
approximation by almost half.... from single clock I derived two clocks
and divided the entire logic into two halves each running alternatively
one after another so that by using both the halves of incoming clock I
am able to get result in half the time... but anyways
its all useless till the shit starts giving me correct outputs....
Well best of luck to you:

feel free for any other information......

VHDL code for clockgenerator is:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity clkgen is
    Port ( clk : in std_ulogic;
           nclk: out std_ulogic;
           pclk : out std_ulogic
          );
end clkgen;

architecture Behavioral of clkgen is
begin
nclk <= clk nand clk;
pclk <= clk and '1';
end Behavioral;

VHDL CODE FOR SAR(main project) IS

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sar_b is
 Port ( clk, Cin, Em, Rm : in std_ulogic;
           sample: out std_ulogic := '0';
           eoc: out std_ulogic := '0';
           I: out std_ulogic_vector(7 downto 0) := "00000000";
           O: out std_ulogic_vector(7 downto 0) := "00000000");
end sar_b;
architecture behavioral of sar_b is
signal check: BOOLEAN;
signal nc,pc: std_ulogic;
signal d:std_ulogic_vector(0 to 7) := "00000000";
component clkgen is
port (clk : in std_ulogic;
      nclk : out std_ulogic;
      pclk : out std_ulogic
     );
end component clkgen;
begin
c1: clkgen port map(clk,nc,pc);--positive clock(pn)&negative clk(nc)
process (Em, Rm, nc, pc,Cin, d)
variable temp: integer := 0;
begin
if Em = '1' then
   if Rm = '1' then
      I<="00000000";
      O<="00000000";
      d<="00000000";
     if pc = '1' then
       temp:=temp+1;
       if temp = 1 then
         d(7)<='1';
         I<="10000000";
         sample<=i(7);
       elsif temp = 2 then
         d(6)<=Cin;
         d(5)<='1';
         I<=(d(7),d(6),'1',others=>'0');
       elsif temp = 3 then
         d(4)<=Cin;
         d(3)<='1';
         I<=(d(7),d(6),d(5),d(4),'1','0','0','0');
       elsif temp = 4 then
         d(2)<= Cin;
         d(1)<= '1';
         I<=(d(7),d(6),d(5),d(4),d(3),d(2),'1','0');
       elsif temp = 5 then
         d(0)<=Cin;
         I<=D;
       end if;
     end if;
   elsif nc = '1' then
       if temp = 1 then
          d(7)<=Cin;
          d(6)<='1';
          I<=(d(7),'1',others=>'0');
       elsif temp = 2 then
          d(5)<=Cin;
          d(4)<='1';
          I<=(d(7),d(6),d(5),'1', others=>'0');
       elsif temp = 3 then
          d(3)<=Cin;
          d(2)<='1';
          I<=(d(7),d(6),d(5),d(4),d(3),'1','0','0');
       elsif temp = 4 then
          d(1)<= Cin;
          d(0)<= '1';
          I<=(d(7),d(6),d(5),d(4),d(3),d(2),d(1),'0');
       elsif temp = 5 then
          O<=d;
          eoc<='1';
       end if;
     end if;
   end if;

end process;
end behavioral;


Article: 101105
Subject: Re: Xilinx Virtex-4 OCM Usage Issues
From: "charles.eddleston@gmail.com" <charles.eddleston@gmail.com>
Date: 25 Apr 2006 11:55:07 -0700
Links: << >>  << T >>  << A >>
Ben-
Thanks for the suggestion - my explaination wasn't very clear:  Our
first iteration used a small BRAM on the PLB bus to boot, loaded SDRAM
(which was defined as cached memory space), and then ran out of SDRAM.
With the all the PLB arbitration and overhead logic, this resulted in a
4% of our virtex 4 (fx20).  Currently, we're around 85% and would like
to save this 4% to help build time and allow for future flexibility.

Thanks,
-Charles


Article: 101106
Subject: Re: Initializing array of BlockRAM instances in verilog
From: "Gabor" <gabor@alacron.com>
Date: 25 Apr 2006 12:30:38 -0700
Links: << >>  << T >>  << A >>

Allan wrote:
> Nope, that didn't do it either. I've tried some iterations of this
> theme with no success. Where would I find the libraries you mentioned
> to take a look at?

%Xilinx%\verilog\src\unisims\RAMB16_S36_S36.v


Article: 101107
Subject: Re: clock multiplication
From: dancedynamix@hotmail.com
Date: 25 Apr 2006 12:36:17 -0700
Links: << >>  << T >>  << A >>
Thank you all very much!
Please forgive my inexperience!

All the best.


Article: 101108
Subject: Xilinx Map vs IOB tri-state with clock enable...
From: "johnp" <johnp3+nospam@probo.com>
Date: 25 Apr 2006 12:46:08 -0700
Links: << >>  << T >>  << A >>
I'm using XST 8.1 SP3 with a Spartan3 design.  I'm trying to
use both the output and tri-state flip-flops in the IOB, but the
Xilinx tools are fighting me.

If I code my logic as:

always @(posedge ifclk)
      amb_data_enable <= ~wr_pending;

always @(posedge ifclk)
    if (dclkp)
        o_data          <= bits128 ? next_odata : {next_odata[63:0],
64'b0};

I end up using both the output and tri-state enable flip-flops in all
128
of the IOBs.  Great!

BUT...  If I change the code to be:

always @(posedge ifclk)
    if (dclkp) // <--------------------------- NOTE THE CLOCK ENABLE
        amb_data_enable <= ~wr_pending;

always @(posedge ifclk)
    if (dclkp)
        o_data          <= bits128 ? next_odata : {next_odata[63:0],
64'b0};

The Xilinx tools no longer pack the tri-state enable flip-flop
into the IOB.

Looking at the IOB structure in the data sheet, this looks like it
should be
a legal construct that should take advantage of the IOB resources.

Has anyone seen this before?  Any suggestions?  I hate to waste time
opening a Web Case with Xilinx - I seldom get any reasonable answer
from them.

John Providenza


Article: 101109
Subject: Re: 116 warnings... successive approximation register using both
From: Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com>
Date: Tue, 25 Apr 2006 21:51:19 +0200
Links: << >>  << T >>  << A >>
bad synchrounous assignment wrote:
> after compiling my project...116 warnings came ... i m new to VHDL..
> gotta submit within 24 hrs
> HELP>>SOS>>SOS
> 
> hello thr
> 
> hi! i am stuck up pretty bad with my project and need your immediate
> assistance within 24hrs...... 

May I suggest to hire in emergency a consultant that you're gonna pay
$$$$ to work out your problem thru the night.


Sylvain

Article: 101110
Subject: Re: Xilinx Map vs IOB tri-state with clock enable...
From: "johnp" <johnp3+nospam@probo.com>
Date: 25 Apr 2006 13:42:37 -0700
Links: << >>  << T >>  << A >>
Here's more info....

I re-coded to get rid of the clock enable thinking that would
trivially fix my problem:

reg             data_on;
wire            data_enable;
always @(posedge ifclk)
    if (dclkp)
        data_on <= wr_pending;

assign data_enable = dclkp ? wr_pending : data_on ;

always @(posedge ifclk)
        amb_data_disable <= ~data_enable;


always @(posedge ifclk)
    if (dclkp)
        o_data          <= bits128 ? next_odata : {next_odata[63:0],
64'b0};

assign amb_dat = amb_data_disable ? 128'bz : o_data;

The above version works fine.  I end up using the data_out and
tri-state regs
in the IOB.     BUT...      if I remove the "~" from the assignment
to amb_data_disable, the Xilinx tools again fail to use the flip-flop
in the IOB
that controls the tri-state.  SO....

always @(posedge ifclk)
        amb_data_disable <= ~data_enable;  // ALLOWS IOB 3state
register

always @(posedge ifclk)
        amb_data_disable <= data_enable;  // BREAKS IOB 3state reigster

Also - in ISE 8.1, bothg Synthesis and Map have options to control IOB
register packing.  Changing the Synthesis option to YES seemed to make
things worse.

XILINX: isn't it time that you finally fix the IOB register inference?
How much
time do we designers have to waste on this stupid problem?

John Providenza


Article: 101111
Subject: Re: Opinions on Viva
From: Ray Andraka <ray@andraka.com>
Date: Tue, 25 Apr 2006 17:12:21 -0400
Links: << >>  << T >>  << A >>
Kolja Sulimma wrote:

>>http://www.starbridgesystems.com/
> 
> 
> Isn't that the company that "put the hype back into hypercomputing?"
> 
> Kolja Sulimma

ROFLMAO!  Thanks, I needed that!

Article: 101112
Subject: USB slot on Xilinx ML310 board - linux platform
From: "chakra" <narashimanc@gmail.com>
Date: 25 Apr 2006 14:36:36 -0700
Links: << >>  << T >>  << A >>
Dear Group,

I wonder if anyone in this group has successfully used USB slot for
anything (say camera, mouse or any device) on the Xilinx ML310 board?
I saw a few people (Pradeep, wong-australia) work on the board mid last
year, but would like to know if they had any success with the usb slot.

with warm regards,
chakra.


Article: 101113
Subject: Re: Smallest uClinux configuration
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Wed, 26 Apr 2006 09:14:18 +1000
Links: << >>  << T >>  << A >>
Hi Justin,

Justin Erickson wrote:

> I am trying to get uClinux to run in under 2MB of RAM without flash and if 
> possible to still have networking support. All I need is basic command line 
> support and the ability to load and execute one additional program.

You can do it, but it will be tight.  You will also need to consider how
to boot your system each time, if you have no persistent storage.

> I'd guess that a bunch of people have tried this before and would appreicate 
> any help/suggestions on how best to setup the uClinux build configuration.

Best place to talk about this is probably on the microblaze-uclinux
mailing list - send an email to "majordomo@itee.uq.edu.au" with the body
text "subscribe microblaze-uclinux" and you'll be ready to go.

List archives are indexed nicely by google, just add the term
"microblaze-uclinux" to your search terms.

Regards,

John


Article: 101114
Subject: Re: clock multiplication
From: "Peter Alfke" <peter@xilinx.com>
Date: 25 Apr 2006 16:36:40 -0700
Links: << >>  << T >>  << A >>
Your design would be much simpler if you had an input clock that varies
between 1.3 and 1.6 MHz. You could then easily generate the 32-times
lower clock frequency with a 5-bit counter.
In your case, you have to build a feedback (or servo) system, that
multiplies the frequency in an indirect way: it adjusts a variable high
frequency (1.2...1.6 MHz Voltage-Controlled Oscillator). This high
frequency is divided by 32 in a 5-bit binary counter, and the output of
this counter is compared (in a phase/frequency detector) against your
incoming 39 to 50 kHz clock. Any frequency or phase difference
generates a control signal that, appopriately filtered, changes the VCO
frequency in the right direction.
A long time constant in the Low-pass filter gives you a very stable
frequency, but slows down the response to any frequency changes of your
incoming clock. A higher cut-off frequency in the Low-pass fiter gives
you less stability, but better agility.
There are many textbooks that describe PLL (Phase-Locked Loop) design.
Any FPGA can implement the counter and also the phase/frequency
detector, but not the VCO.
Peter Alfke, Xilinx Applications


Article: 101115
Subject: Re: clock multiplication
From: "John_H" <johnhandwork@mail.com>
Date: Tue, 25 Apr 2006 23:51:02 GMT
Links: << >>  << T >>  << A >>
<dancedynamix@hotmail.com> wrote in message 
news:1145982839.568784.88950@y43g2000cwc.googlegroups.com...
> Hi there,
>
> I have a low frequency variable clock frequency (for vari-speed audio
> tasks) in the range of 39 KHz to 50 KHz.
>
> Is it easy within an FPGA to implement a 32 times clock multiplier?
>
> Would the circuit be a combination of PLL's?
>
> Any advice/help appreciated!
>
> Thanks, Bob.

Say, could you *generate* the 39kHz or 50 Khz clock with the FPGA?  If you 
use a fixed 50 MHz system clock (easy in today's FPGAs) you could get a 
jitter-free output clock with better than 0.1% frequency accuracy over your 
range of interest.

If you can tolerate a little jitter (which I would expect is undesirable for 
audio) then a digital phase locked loop could slave a clock generated by the 
FPGA back to your reference clock. 



Article: 101116
Subject: Re: SPARTAN3E SK LCD
From: "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com>
Date: 25 Apr 2006 17:30:27 -0700
Links: << >>  << T >>  << A >>

Eka From Indonesia wrote:
> I have SPARTAN3E STARTER KIT and I'm uncomfortable with its LCD
> off-backlight. I would like to turn on it permanently. Is it safe to
> turn on LCD backlight with 5V SPARTAN3E SK-PSU by connecting pin15 (LCD
> BL Anode) to pin2 (LCD VDD) and pin16 (LCD BL Cathode) to pin1 (LCD VSS
> / Ground)? Please advise me, thank you.

The Spartan-3E Starter Kit board uses a PowerTip PC1602-D character LCD
screen that does not include a backlight.

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.


Article: 101117
Subject: Re: Spartan 3 documentation confusing...
From: "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com>
Date: 25 Apr 2006 17:49:21 -0700
Links: << >>  << T >>  << A >>
rickman wrote:

[... snip ...]

> "A Low logic level on HSWAP_EN activates the pull-up resistors on all
> I/Os during configuration."  Does this include the dedicated
> configuration signals?  How about the dual purpose configuration pins?
> Or is it just the User IO?

First, some background.  On Spartan-3, the dedicated configuration
pins, like CCLK, DONE, PROG_B, M2, M1, M0, and HSWAP_EN itself, all
have an internal pull-up resistor to VCCAUX that is active during
configuration, regardless of HSWAP_EN.  After configuration, these pins
have a bitstream generator option that defines their respective
behavior.

All other pins have optional pull-up resistors, controlled by the
HSWAP_EN pin.  When HSWAP_EN=0, these pull-ups are enabled to their
respective I/O Bank voltage supply (such as VCCO_0, VCCO_1, etc.).

> I found this sentance to be especially unenlightening...
>
> "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0,
> HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a
> pull-up resistor to HSWAP_EN during configuration, regardless of the
> value on the HSWAP_EN pin."
>
> What does a "pull-up resistor to HSWAP_EN" mean???  Why would TDO have
> (or need) a pull up to any value since it is a full time output?

What the who!?!  I think the intention was that the "pull-up resistor
connects to VCCAUX", _not_ HSWAP_EN.  I'll see that we get that one
fixed ASAP!

> Why does Xilinx make it so hard to get the all important details on a
> part that has been in full production for so long?  They just updated
> the Spartan 3 data sheet this month!  Why wasn't the information that
> they know is lacking included?  I say they know info is lacking because
> you can find it in an answer record if you know to look for it.

The updates happen periodically.  As various issues are reported by the
Xilinx Technical Support team, we update the documentation to make sure
that you don't bump into any known landmines (okay, not a Marketing
term).  The latest updated changed maybe 0.1% of the verbage.  We
incorporate the latest learning, new ideas, and latest information.
Believe me, we want to make your design experience as pleasant and
trouble-free as possible.

I encourage active feedback.  If something is confusing, please let us
know, as it will likely be confusing to others.  Most of our best
product and documentation ideas come from Xilinx users!  Feel free to
E-mail me directly for Spartan documentation or use the Feedback link
from the Xilinx web site.
http://www.xilinx.com/askx/feedback.htm

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
E-mail: steve.knapp@xilinx.com
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.


Article: 101118
Subject: Re: Heating problem of the CPLD
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 26 Apr 2006 13:03:29 +1200
Links: << >>  << T >>  << A >>
john wrote:
> Hello,
> 
> I am using atmel's ATF1508AS-7QC160. My clock frequency is 20MHz. Now,
> my cpld some times work and sometimes does not work at that frequency.
> If I lower the clcok frequency to 12MHz then it always work. bu tin
> both cases the chip does get hot. I put a heat sink on the chip but if
> the chip works for long hours then it effects its functionality. Can
> anybody advice me how to slove this problem?

First, measure the Icc, and determine if it is close to the data sheet
typicals ( see the graphs ). If it is widely higher, then look for 
shorted pins, floating IPs etc ( enable the PinKeepers )

In the ATF15xx series, you have a Reduced Power Mode (per macrocell) 
option, that can save power, at the trade off of additional delay.
Use that on the MCells that do not have to be fast.

How many levels of logic do you have ? ~20MHz should be ok in a 1508,
but if you have a lot of logic levels, you will get the marginal
operation you describe - 20Mhz is 50ns full cycle, 25ns half cycle.

Look at the fitter .FIT report file, to see the levels of Logic,
and MC options.

-jg


Article: 101119
Subject: Re: ISE 8.1i for Linux ?
From: "Steve Knapp (Xilinx Spartan-3 Generation FPGAs)" <steve.knapp@xilinx.com>
Date: 25 Apr 2006 18:05:54 -0700
Links: << >>  << T >>  << A >>

Bob Smith wrote:
> The Silicon Valley Homebrew Robotics Club has several
> members using the Digilent 3e starter kit to learn
> Verilog and FPGA design.  We are all newbies and a
> few of us are trying to do this using Linux.  Attached
> is a posting I did to describe some problems and some
> work-arounds to those problems.

Very cool.  BTW, you should add a link to the club site.  Looks like a
number of interesting topics!
http://www.hbrobotics.org/

[ ... snip ... ]

> To learn FPGA design I followed in the steps of Chris Palmer
> of the HBRobotics Club and ordered a Digilent "Spartan-3 Board"
> for $99.  You can order one at http://www.digilentinc.com/

There is also a new board, called the Spartan-3E Starter Kit board that
has a larger-density FPGA, lots of Flash, a display, DDR SDRAM, etc.

It is available for US$149 from the Xilinx store.
http://www.xilinx.com/s3estarter

It too is fully supported by WebPack 8.1i.  The kit also includes an
evaluation version of the EDK software, which includes the 32-bit
FPGA-based MicroBlaze RISC core and peripherals.

The user guide is available here ...
http://www.xilinx.com/bvdocs/userguides/ug230.pdf

... and there are various reference designs available as well.
http://www.xilinx.com/products/boards/s3estarter/reference_designs.htm

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.


Article: 101120
Subject: Re: How to avoid lossing channel bonding when using Rocket IO?
From: "king" <frogkinger908@sina.com>
Date: 25 Apr 2006 18:56:29 -0700
Links: << >>  << T >>  << A >>
to colin:

but it really happend :-(
the frequency is 155MHz, and I made channel banding once a time
when the data flow is slow, there is nothing wrong
but as soon as the data flow becomes fast (also working at 155MHz),
the 4 channels can not receive a special mark at the same time
so I think they are lossing channel banding

I wonder what happend when the speed of data flow changes, and why this
can 
result in the loss of channel banding.

Thanks a lot!!

king


Article: 101121
Subject: Re: Simulated Quartus II delays are much greater than measured
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 26 Apr 2006 14:46:57 +1200
Links: << >>  << T >>  << A >>
oopere wrote:
> Kolja Sulimma wrote:
> 
> 
>>oopere schrieb:
>>
>>
>>>The question is, why is the simulation wrong? (Yes, I have selected the
>>>correct device in the assignments). I can understand that reality is
>>>always worse than simulation but have almost never the opposite!
>>
>>Wrong. Always the opposite.
>>The delay values given by the manufacturer (and used in simulation) are
>>guaranteed values under worst case conditions. For CMOS these usually are:
>>- worst case input rise time (yes, gate delays depend on input slope)
>>- The lowest allowed VCC
>>- A rather high output loading (e.g. 50pF for PCI compliant outputs)
>>- The highest allowed temperature
>>- slowest chip on a wafer
>>- slowest wafer produced over time
>>
>>If you have flip flops in your design:
>>- worst case clock arrival time for on chip clock skew and jitter
>>
>>additionally for SOI chips:
>>- worst case signal history (delay depends on the last couple of
>>transitions)
>>
>>You are probably far away from worst case for most of these parameters,
>>so you will always be faster in reality than in a worst case simulation.
>>
>>
>>>In any case, the simulator is almost useless in this case.
>>
>>On the contrary. For virtually all applications the slowest edge
>>behaviour is what you want to simulate.
>>For all other applications you need to do monte carlo simulation.
>>
>>Kolja Sulimma
> 
> 
> Thank you. I understand your points. I did not take into account that I
> am simulating the worst case scenario. However,
> 
> a) I still wonder if 15ns is a reasonable worst-case delay for a direct
> input to output connection (or for an input->not gate->output
> connection) for this kind of device. I have been trying to figure out
> which combination of t_xyzk?#? from the datasheet I should be adding in
> this case (have to say, without success)
> 
> b) It is surprising that the simulator tells that the direct connection
> exhibits greater delay than the inverted one. Perhaps this depends on
> which particular output pin is driven?

That sounds like a bug - if you have checked that's what the design 
tools actually created.

ie What may have actually been created is a nett-non-inv path, and an 
nett-inv-path, and if the latter can be made by _removing_  an inverter, 
then the delays you report make sense. ( 400ps faster )

You can reality check your silicon, with a ring oscillator design.
That can indicate how Vcc and Temperature affect delays, for example.
  Process variations are harder to get a handle on, but 3:1 ratios
you seem to have, would be at the conservative (pessimistic)  end of the 
range.

  What can also result in that, is if vendors have faster speed grades
and the slow one is a 'yield safety net', plus they round-up to the
nearest 5ns, and they can also meet some competition point ( 15ns
was a common spec point, years ago ) - combine all that, and
you can get what looks like a very fat margin, especially on the
trail-end devices.

  Sometimes vendors have to keep labeling (eg) -15 parts, because that's
what purchasing depts have 'locked in', and not because it has
much to do with what the FABs produce :)

-jg


Article: 101122
Subject: Async FPGA ~2GHz
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 26 Apr 2006 16:24:21 +1200
Links: << >>  << T >>  << A >>
For those interested in Async devices, and uses :

http://www.achronix.com/news.html?newsID=72&PHPSESSID=f6e19bf363bdcb02af69ce9b919f7562

It is a way's off being usable, but the numbers are impressive :)

  No mention of device size, but the info suggests they target the 
high-price/low volume user space.
  [ Not too many customers need -196'C :) ]

.. and no mention of design tools, which may prove to be a bigger
challenge than the silicon.

-jg



Article: 101123
Subject: Re: Synthesizer is creating unwanted global resources
From: "vssumesh" <vssumesh_asic@yahoo.com>
Date: 25 Apr 2006 22:49:53 -0700
Links: << >>  << T >>  << A >>
One main doubt,
why
assign out = in[ind];
is possible but
assign out[ind] = in; is not possible
Because of this i think demuxing can only be done with FFs or latches
created in a behavioural code. Or is there any other method ????
but
always @(*)
out[ind] = in;
is creating all the logic needed for the demuxing only the storage is
to be avoided How can we extract the combinatorial logic part?


Article: 101124
Subject: Re: Async FPGA ~2GHz
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Wed, 26 Apr 2006 08:10:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
Jim Granville <no.spam@designtools.co.nz> wrote:
> For those interested in Async devices, and uses :

> http://www.achronix.com/news.html?newsID=72&PHPSESSID=f6e19bf363bdcb02af69ce9b919f7562

> It is a way's off being usable, but the numbers are impressive :)

>   No mention of device size, but the info suggests they target the 
> high-price/low volume user space.
>   [ Not too many customers need -196'C :) ]

Jim, the press release tells about testing from -196C to +130C not only at
-196 C... 

> .. and no mention of design tools, which may prove to be a bigger
> challenge than the silicon.

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------



Site Home   Archive Home   FAQ Home   How to search the Archive   How to Navigate the Archive   
Compare FPGA features and resources   

Threads starting:
1994JulAugSepOctNovDec1994
1995JanFebMarAprMayJunJulAugSepOctNovDec1995
1996JanFebMarAprMayJunJulAugSepOctNovDec1996
1997JanFebMarAprMayJunJulAugSepOctNovDec1997
1998JanFebMarAprMayJunJulAugSepOctNovDec1998
1999JanFebMarAprMayJunJulAugSepOctNovDec1999
2000JanFebMarAprMayJunJulAugSepOctNovDec2000
2001JanFebMarAprMayJunJulAugSepOctNovDec2001
2002JanFebMarAprMayJunJulAugSepOctNovDec2002
2003JanFebMarAprMayJunJulAugSepOctNovDec2003
2004JanFebMarAprMayJunJulAugSepOctNovDec2004
2005JanFebMarAprMayJunJulAugSepOctNovDec2005
2006JanFebMarAprMayJunJulAugSepOctNovDec2006
2007JanFebMarAprMayJunJulAugSepOctNovDec2007
2008JanFebMarAprMayJunJulAugSepOctNovDec2008
2009JanFebMarAprMayJunJulAugSepOctNovDec2009
2010JanFebMarAprMayJunJulAugSepOctNovDec2010
2011JanFebMarAprMayJunJulAugSepOctNovDec2011
2012JanFebMarAprMayJunJulAugSepOctNovDec2012
2013JanFebMarAprMayJunJulAugSepOctNovDec2013
2014JanFebMarAprMayJunJulAugSepOctNovDec2014
2015JanFebMarAprMayJunJulAugSepOctNovDec2015
2016JanFebMarAprMayJunJulAugSepOctNovDec2016
2017JanFebMarAprMayJunJulAugSepOctNovDec2017
2018JanFebMarAprMayJunJulAugSepOctNovDec2018
2019JanFebMarAprMayJunJulAugSepOctNovDec2019
2020JanFebMarAprMay2020

Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Custom Search