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"Austin Lesea" <austin@xilinx.com> wrote in message news:e6fqor$7ar14@xco-news.xilinx.com... > John, > > I have taken a new direction: when insulted, ignored, and railed > against unjustly when all I offered was help, I press "ignore" so that > I never have to experience your unhappy existence, again. I can not > solve all the world's problems, and I must accept there are those who > are so intent on being miserable, and causing others pain, that I can > have no positive influence whatsoever. > > Good luck. > > (Mr) Austin Lesea All I want is a customer service that works. Why are you attacking me ? When I discover en error in one of your products, and there is no way what so ever tha I can get in touch with you, I gett pissed off ! You must have some sort of customer service, anything else is just stupid..Article: 103776
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:448b629d$1@clear.net.nz... > John Smith wrote: > > <snip> > > > > I totally agree with you ! I have gone throug all of that, but there is an > > error in the schematics. > > Here is a tip : provide information and you will get information back. > Spit the dummy, and you will get ignored... > > > And there is now way I can get support on this > > issue, no email support, noe phone support.. > > Well, others seem able to get answers to questions ? > perhaps, you should work on your skills, and not throw the toys out > of your cot ? > > In engineering, you _are_ going to need the skill of getting > information you require, and a rant is counter-productive - or do you > not plan employment in engineering ? > > > > I am totally pissed off by > > Xilinx, if they dont straighten up i'll cut them lose and left them drift > > away..forever. > > and the point of that rant is what, exactly ? > > If you have a specific issue, like an error in a schematic, point that > out, and it will likely be corrected. > > <paste> > > If you dont wish to support individual customers,you should not engage in > > the retail end of the market. Its as simple as that-you make great chips but > > you dont understand the retail business. > > Xilinx are not engaged in the retail end of the market. Their customers > are designers and engineers. Walmart is a retailer. > > > > > I expect to see some improvement in your coustumers service soon. > > here is an example of what your homepage should looke like : > > > > http://www.msi.com.tw/ > > Hmm, well, _that_ is a shocker of a web site - all froth, and no > substance. > I hope Xilinx do NOT copy that. I hope they do. Xilinx now is all substance, but no front......Article: 103777
"Austin Lesea" <austin@xilinx.com> wrote in message news:e6fqor$7ar14@xco-news.xilinx.com... > John, > > I have taken a new direction: when insulted, ignored, and railed If you are insulted by THIS discussion, I think you need a new job ! Somewhere else ! ROFL ::--))) I'm switching to Altera, thats for sure.... Ha-ha-ha-Article: 103778
"John Smith" <someone@microsoft.com> wrote in message news:e6gg43$bqi$3@readme.uio.no... > > "Austin Lesea" <austin@xilinx.com> wrote in message > news:e6fqor$7ar14@xco-news.xilinx.com... > > John, > > > > I have taken a new direction: when insulted, ignored, and railed > > If you are insulted by THIS discussion, I think you need a new job ! > Somewhere else ! > > ROFL ::--))) > > I'm switching to Altera, thats for sure.... Ha-ha-ha- I fyou wnat to be insulted, i can do that in Norwegian, yopu know. the land og the Vikings ! OK here It comes (you dont wnat to get this translated, believe me ) Hallo Austin ! Hvorfor ha dere ikke en kundestøtte på epost ! That's about the most rude thing anyone could say to a Xilinx employee.....If you feel insulted, i can understand that.Article: 103779
"Jim Granville" <no.spam@designtools.co.nz> wrote in message news:448b629d$1@clear.net.nz... > John Smith wrote: > > <snip> > > > > I totally agree with you ! I have gone throug all of that, but there is an > > error in the schematics. > > Here is a tip : provide information and you will get information back. > Spit the dummy, and you will get ignored... > > > And there is now way I can get support on this > > issue, no email support, noe phone support.. > > Well, others seem able to get answers to questions ? > perhaps, you should work on your skills, and not throw the toys out > of your cot ? Lucky you ! Thats the E-mail Im looking for , can you discover this secret "suopprt-mail-adress", or is it classified ? Like the aliens at AERA-51 ? Powered på chips from Xilinx ? Ha-ha-ha-ha. One should not mess with stuff like that..Article: 103780
blisca wrote: > John Smith <someone@microsoft.com> wrote in message > e6dtau$6jo$2@readme.uio.no... > > > > "blisca" <blisca@tiscali.it> wrote in message > > news:448a698e$0$18282$4fafbaef@reader1.news.tin.it... > > > > > > blisca <blisca@tiscali.it> wrote in message > > > 448a0bad$0$14780$4fafbaef@reader4.news.tin.it... > > > > > > > > John Smith <someone@microsoft.com> wrote in message > > > > e6cskr$ofc$2@readme.uio.no... > > > > > > > > > > "blisca" <blisca@tiscali.it> wrote in message > > > > > news:4489bd31$0$18288$4fafbaef@reader1.news.tin.it... > > > > > > hello > > > > > > i built on myself a cable 3 interface,following the xilinx > drawing,i > > > > > checked > > > > > > in all the possible ways,ohmically,injecting square waves,and then > > > once > > > > > > connected tho the parallel port i used the option in the Jtag > > > programmer > > > > > > utility that allows to force level on tdi,sending n clock pulses > and > > > so > > > > > > on,these signals are present on the pins of the fpga and the cable > > is > > > > > > connected to the supply(5V),but the pc doesn't see the cable at > all > > > > > > please,anyone can help me?thanks! > > > > > > > > > > > > > > > > Try the different BIOS setup options on your computer for the port > in > > > > > question. It worked wonders for me, but that was a Parallel IV > cable. > > > When > > > > > it was set to ECP-mode, everything worked so much better. > > > > > > > > > > > > > > despite here in italy are 1:45 a.m. i want to follow your hint,stay > > tuned > > > > and thank you > > > > > > > no way :-( but thank you > > Well, try to change the port. My Cable IV would not work at all on my > > "expansion bord" LPT, but it worked on my mainboard LPT. Maybe the > opposite > > is the case for you ? > > > > Regards, > > > > John > > > >mmmmmm.....thank you but i tried it yet on 2 different pc's ,reverse proof > now should be to find another cable III > and use it on the same pc.......... > if i could find it here in italy i should buy an official xilinx > programmer....... Digilent sells a clone of the Cable III quite cheaply. I got one with their Spartan 3 kit. LeonArticle: 103781
Rich, I am not really sure, why you are trying to install Xilinx on Slackware. As you describe, you have a plain vanilla system, so probably the reason for using Slackware is, that you just did not have access to RedHat? Try this: http://www.centos.org http://www.lineox.net This is both basically RedHat with a few changed artworks and logos. It is compiled from the same sources as RedHat and seems to work fine. You will see a few error messages during install, but the software seems to run fine. Xilinx: Would have been nice to have a hint to the available RedHat clones on your web site, as not everybody wants to buy RedHat. Thanks for adding this to your knowledge base. Best regards, Felix -- Dipl.-Ing. Felix Bertram http://www.bertram-family.com/felix Rich Grise schrieb: > [crossposted because it's about Xilinx S/W, I'm running Slackware, and > s.e.d is where all the really smart people hang out...] > > OK, I decided to take a chance and download that 839MB shell script that's > written for RedHat Enterprise, and was doing OK, (I had to shell out as > root a couple of times to give the install script permission to write to a > new directory, but that felt kind of kewl. :-) ), and now I'm at kind of a > stopper. The graphic install has the progress bar at 99%, and there's a > white-X-in-the-red-circle error message: Error: Cannot run process - > /usr/local/richgrise/Xilinx/.xinstall/install_driverscript > while simultaneously, the Konsole where I invoked it says: > ------<quote>------ > richgrise@thunderbird:~/L/Downloads/Xilinx_Webpack_8.1i_Webpack $ > WebPACK_81i_SFD.sh > Verifying archive integrity... All good. Uncompressing Xilinx ISE WebPACK > Installer..................................................................................................................................................................................................... > /lib/modules/misc/windrvr6.o: kernel-module version mismatch > /lib/modules/misc/windrvr6.o was compiled for kernel version > 2.4.18-14 while this kernel is version 2.4.31. > ------</quote>------ > and the console is patiently waiting (no prompt), and the error dialog box > is patiently waiting for me to click "OK". > > So, I wonder, is there some way to spoof Xilinx ISE for Red Hat Enterprise > into thinking that I have the older kernel? Or, maybe (yah, right) that > Xilinx guy who shows up from time to time on comp.arch.fpga might have > some suggestion. :-) > > Frankly, I'm kinda surprised that it's gotten as far as it has, running a > Red Hat Enterprise script on a plain vanilla Slackware box. :-) That's > Slackware 10.2, basically right out of the box; and the "Single File > Install" at Xilinx: > http://www.xilinx.com/ise/logic_design_prod/webpack.htm > > So, back to the question, can I spoof it? Or get enough source code to > recompile and relink it? I certainly don't want to try to install a > different kernel - that's WAY beyond my scope of "expertise". ;-) > > Thanks! > Rich >Article: 103782
Subhasri krishnan wrote: > Hi all, > I have some basic doubts. The initialization sequence for sdram's from > different chip manufacturers vary slightly although the ones that I > have referred to(micron, samsung, hynix) use "precharge followed by 2 > auto-refresh cycles". how does this wake up the device? Also does the 2 > cycles here mean two complete refreshes of 4096 rows? It means 2 auto-refresh commands, as though you were doing a distributed refresh. > > My understanding is this. Once I power-up and initialize using burst > type auto-refresh, my device is in idle state and because I write/read > every row and column more than twice within 64ms, i dont need any > refresh. Although from post-place and route simulation results I can > verify that the logic and timing for memory controller is ok, the > pattern still looks very strange(on the monitor after configuration > with the bit fle). It looked to me like once every few rows, a wrong > row is opened. The only thing that changed this strange pattern was the > auto-refresh counter in the initialization sequence Are you simulating using the Verilog or VHDL models provided by Micron, and if so, do you have the debugging statements turned on? Micron has excellent HDL simulation models that check many, if not all of the signal timing relationships. > > Auto-refresh specified can be implemented either as a burst of 4096 > cycles every 64ms or can be distributed every 15.625 us right? so while > initializing the device if I use burst type command then after 2 > complete cycles the device should be in idle state. No, the device is in the idle state because of the Precharge command; the auto-refresh doesn't activate any banks. If the device is not idle before auto-refresh, I don't think the manufacturer guarantees anything. The Micron HDL models will spot these problems. --- Joe Samson Pixel VelocityArticle: 103783
Chris Sorenson wrote: >> installable package in a shell script? Binary here documents? >> > > Nvidia does the same thing with their binary-only drivers, the binary > is included as part of one giant shell script. Perhaps you could > even modify it if you used an 8-bit clean editor... It's a tried and true technique. See gzexe for another example. I don't believe there's anything special about RH that caused Xilinx to pick it other than being "the enterprise Linux". Heck the "script written for RH" runs just fine under ABI emulation on FreeBSD. -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 103784
Alan Nishioka wrote: > I have never implemented the SDRAM init sequence. The manual says it > is essential, but not why. To prepare the memory for the first access (by making sure that the device is in idle, all open rows precharged, and recently refreshed) and to set the mode register. --- Joe SamsonArticle: 103785
Alex Gibson wrote: > Altium gives a link to Tony's products via third party plugin io modules > http://www.altium.com/Community/LiveDesignEvaluationBoards/ You might want to be careful assuming they work.. The example project for the Memc/Avent Spartan 3 board doesn't work for me and I have had quite a number of support emails back and forth but no progress yet (and they don't actually have the board anymore). Can't say it inspires me to buy it when the demo version doesn't work on a board they have allegedly tested with.. > Note that the graphics engine requires a graphics card that supports > DirectX® 9.0c and Shader Model 3.0. Seems pretty dumb they don't have a GDI fallback (since they already have it written and debugged) > Work isn't renewing our altium licenses , switching to Eagle instead for > pcbs. Yeah given Altium's apparent inability to fix bugs in their software or come up with half decent licensing models I am not surprised :) -- Daniel O'Connor software and network engineer for Genesis Software - http://www.gsoft.com.au "The nice thing about standards is that there are so many of them to choose from." -- Andrew Tanenbaum GPG Fingerprint - 5596 B766 97C0 0E94 4347 295E E593 DC20 7B3F CE8CArticle: 103786
John Smith wrote: > > I fyou wnat to be insulted, i can do that in Norwegian, yopu know. the = land > og the Vikings ! OK here It comes (you dont wnat to get this translated, > believe me ) > > Hvorfor ha dere ikke en kundest=F8tte p=E5 epost ! > > That's about the most rude thing anyone could say to a Xilinx > employee.....If you feel insulted, i can understand that. Well, we understand Norwegian. It translates to: "Why do you not have customer service via e-mail?" Hilsen fra Peter AlfkeArticle: 103787
>The main problem is that none of these cores include documentation or >verification suites. I would plan on being able to switch different >cores in and out if you run into problems. Kind of a pain since they >are all a little different, but might save pain during development. It might be a fun project to run two cores in lock step running the same program and see how far they get before they get a different result. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 103788
> > > > > > Regards, > > > > > > John > > > > > >mmmmmm.....thank you but i tried it yet on 2 different pc's ,reverse proof > > now should be to find another cable III > > and use it on the same pc.......... > > if i could find it here in italy i should buy an official xilinx > > programmer....... > > Digilent sells a clone of the Cable III quite cheaply. I got one with > their Spartan 3 kit. > > Leon > Thanks for help to the 2 Johns and LeonArticle: 103789
Hi everyone, I'm a student electronics and computer engineering, and I've already got quite a bit of experience with hardware design in general and with VHDL. I was wondering if someone knows a good reference or book that explains what the VHDL compiler actually does with the code, to convert it into logic and put it into the FPGA. In other words, how is a VHDL compiler created, how does it take your code, like a behavioural approach, and litteraly draws a logic circuit out of it? Does anyone know a good website/book/reference where to start to get this knowledge? Thanks. Sincerely, E. LesserArticle: 103790
> It might be a fun project to run two cores in lock step running > the same program and see how far they get before they get a different > result. > I maintain the cores on fpgaarcade. That trick is how I found most of the problems in the T80 core, and is the reason it is more accurate than the T65 core which I have never got around to doing the same thing. I think there are some pictures on the pacman page on the website showing the real Z80 being run alongside. When running the pacman code, the real Z80 and the T80 core stay in lock-step indefinately, which I am quite happy with. http://www.opencores.org/forums.cgi/cores/2002/10/00062 /MikeJArticle: 103791
Joseph Samson wrote: > Alan Nishioka wrote: > > I have never implemented the SDRAM init sequence. The manual says it > > is essential, but not why. > To prepare the memory for the first access (by making sure that the > device is in idle, all open rows precharged, and recently refreshed) and > to set the mode register. I suppose that's all the SDRAM init sequence is for. I guess I was expecting something deeper. And it confirms my belief that it is unnecessary in my frame buffer application. Alan NishiokaArticle: 103792
Joseph Samson wrote: > Subhasri krishnan wrote: > > Hi all, > > I have some basic doubts. The initialization sequence for sdram's from > > different chip manufacturers vary slightly although the ones that I > > have referred to(micron, samsung, hynix) use "precharge followed by 2 > > auto-refresh cycles". how does this wake up the device? Also does the 2 > > cycles here mean two complete refreshes of 4096 rows? > > It means 2 auto-refresh commands, as though you were doing a distributed > refresh. So the address is being generated internally and refresh is performed at regular intervals. What if I donot issue any more refreshes after these initial two auto-refresh command? Also, I am wondering if there is any difference between these two ways of writing to an sdram with 256 columns in each row. 1) Open a row. Write 256 values continuously (single burst). Close row. 2) Open a row. Write about 30-32 pixels(once a fifo is almost full). Close row. Open row again after fifo reaches almost full and write 30-32 pixels. Close row and so on... Is there a timing constraint in the second case that I should be aware of. For the first case I am able to get the sdram to work. > > > > > My understanding is this. Once I power-up and initialize using burst > > type auto-refresh, my device is in idle state and because I write/read > > every row and column more than twice within 64ms, i dont need any > > refresh. Although from post-place and route simulation results I can > > verify that the logic and timing for memory controller is ok, the > > pattern still looks very strange(on the monitor after configuration > > with the bit fle). It looked to me like once every few rows, a wrong > > row is opened. The only thing that changed this strange pattern was the > > auto-refresh counter in the initialization sequence > > Are you simulating using the Verilog or VHDL models provided by Micron, > and if so, do you have the debugging statements turned on? Micron has > excellent HDL simulation models that check many, if not all of the > signal timing relationships. > > > > > Auto-refresh specified can be implemented either as a burst of 4096 > > cycles every 64ms or can be distributed every 15.625 us right? so while > > initializing the device if I use burst type command then after 2 > > complete cycles the device should be in idle state. > > No, the device is in the idle state because of the Precharge command; > the auto-refresh doesn't activate any banks. If the device is not idle > before auto-refresh, I don't think the manufacturer guarantees anything. > The Micron HDL models will spot these problems. > Thanks for the pointer. I was able to download it and I am going take a look. Subhasri.KArticle: 103793
Alan Nishioka wrote: > Joseph Samson wrote: > >>Alan Nishioka wrote: >> >>>I have never implemented the SDRAM init sequence. The manual says it >>>is essential, but not why. >> >>To prepare the memory for the first access (by making sure that the >>device is in idle, all open rows precharged, and recently refreshed) and >>to set the mode register. > > > I suppose that's all the SDRAM init sequence is for. I guess I was > expecting something deeper. And it confirms my belief that it is > unnecessary in my frame buffer application. I don't see how that follows at all from my explanation. 1. "To prepare the memory for the first access" - Unless you don't plan on having a first access, you will need to make sure that the memory is in idle before you open a row. 2. "to set the mode register" -You need to tell the memory the burst size, CAS latency, burst sequence... --- JoeArticle: 103794
Subhasri krishnan wrote: > So the address is being generated internally and refresh is performed > at regular intervals. What if I donot issue any more refreshes after > these initial two auto-refresh command? As long as you are reading every row within the distributed refresh time spec you should be OK. > Also, I am wondering if there is any difference between these two ways > of writing to an sdram with 256 columns in each row. > 1) Open a row. Write 256 values continuously (single burst). Close row. > 2) Open a row. Write about 30-32 pixels(once a fifo is almost full). > Close row. Open row again after fifo reaches almost full and write > 30-32 pixels. Close row and so on... There's no need to close the row just because you have stopped reading or writing. It may simplify your state machine, but the memory is happy to NOP until you get back to it. In my last SDRAM controller, I could have as many as 4 rows open at a time (one per bank). I'd keep them open unless I had to change rows or do a (distributed) refresh. There is a spec (Tras) on how long a row can stay open. > Is there a timing constraint in the second case that I should be aware > of. For the first case I am able to get the sdram to work. The second case looks identical to the first except for the length of the burst. If you're designing a memory controller, you need to be aware of every timing constraint. > > > > Thanks for the pointer. I was able to download it and I am going take a > look. There are a lot of good postings in comp.arch.fpga on SDRAM controller design and board layout. You should go through them. I seem to recall a good discussion on what's actually happening inside a DRAM (although I can't find it now). --- Joe Samson Pixel VelocityArticle: 103795
elesser wrote: > Hi everyone, > > I'm a student electronics and computer engineering, and I've already > got quite a bit of experience with hardware design in general and with > VHDL. > > I was wondering if someone knows a good reference or book that explains > what the VHDL compiler actually does with the code, to convert it into > logic and put it into the FPGA. In other words, how is a VHDL compiler > created, how does it take your code, like a behavioural approach, and > litteraly draws a logic circuit out of it? > > Does anyone know a good website/book/reference where to start to get > this knowledge? > > Thanks. > > Sincerely, > E. Lesser google <structural synthesis> google <behavioural synthesis> It doesn't matter what the front end language is, VHDL, Verilog & others all map to the same internal representation prior to the real work of synthesis. Synthesis started with ASICs and moved later to FPGAs so some of the material will only cover ASIC. JohnArticle: 103796
Hi all, I am facing timing violations in my FPGA with Max frequency 125 Mhz(Set up viloations). What are the steps to be taken to meet the frequency other than doing a pipeline in RTL. I am using Xilinx FPGA's. regardsArticle: 103797
I am new to using Xilinx cores. My intention is to use the DDS core, for which I was able to generate a number of files using coregen. It appears that only the "padded" EDIF can be run through the backend stages. My question - as naive as it is - is what do you instantiate in a higher level verilog module in order to implement the design?Article: 103798
Hi, Thanks! Any particular book that focuses on this subject that you liked? Sincerely, E. LesserArticle: 103799
elesser wrote: > Hi, > > Thanks! > Any particular book that focuses on this subject that you liked? > > Sincerely, > E. Lesser Not really, most of my textbooks on synthesis are dated back to the earlier work and are really for ASIC design. Some I picked up from Microcenter when they quite selling technical books, got many for $10 instead of $70+++. more ideas Use amazon search engine on same strings to get idea of whats there, you don't have to buy anything or your Uni will have. Look for peer reviewed academic papers, you should have full access to IEEE, ACM & other portals, use citeseer, google scholar. Outside Uni, access is much more limited. Millions of papers on lots of interesting research things. Look at some of the free synthesis software that does structural or behavioural synthsis, then you could read their sources, some get mentioned here quite often. Look for geda, & edacafe as portals, 1st 2 hits on google <free eda software> And google groups for same or similar to find threads on open software. Checkout the DAC conference for company listings, papers presented, not sure if they are online. Also dig around X,A,L websites for any technical or application notes on synthesis, doubt you will find research level EDA type material but it might help since their tools will be proprietary. Some of their employees publish quite a few papers, perhaps that why they got hired. As has been said here before, there are no or very few books on FPGAs since they move so fast. My last technical "FPGA" book covered the 4000 I think, and nothing about synthesis. There are a few FPGA versions of ASIC books that cover language use but nothing much added for FPGAs so no real extra value. happing digging John Jakson
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