Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
I currently have a license for ISE Foundation 8.1. Is it possible to obtain old versions? I am trying to open up an old project from a board vendor and it seems their project must have been built in 4.0 because ISE is complaining that it can't migrate the project file if it's not from ver 5, 6, or 7. Any ideas? Thanks -BrandonArticle: 104851
Brandon,
try the Xilinx classics
http://www.xilinx.com/ise/logic_design_prod/classics.htm
Aurash
Brandon Jasionowski wrote:
>I currently have a license for ISE Foundation 8.1. Is it possible to
>obtain old versions? I am trying to open up an old project from a board
>vendor and it seems their project must have been built in 4.0 because
>ISE is complaining that it can't migrate the project file if it's not
>from ver 5, 6, or 7. Any ideas?
>
>Thanks
>-Brandon
>
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 104852Hi All, We have a prototype board with 4 fpga's. One is an XC3S1500 and the others are XC3S200. There are a lot of jumpers so each one can be the only device on the chain. The bigger device is detected. But when the jumpers are set to individually select the small ones, they arent recognized and is listed as 'unknown device'. If anyone has seen something like this please do tell me what is wrong. Any help is highly appreciated. Thanks Subhasri.KArticle: 104853
"Thomas Stanka" <usenet_10@stanka-web.de> wrote in message
news:1152277556.727243.271290@p79g2000cwp.googlegroups.com...
>
> Logan Shaw schrieb:
>> No, the formula is not correct. The formula does not have any units;
>> therefore, the constant factor is meaningless and the formula cannot
>> be correct.
>
> Maybe you should google a bit after landau symbols and complexity
> theorie.
> In general complexity therorie constants are ignored, but for more
> detailed (or practical oriented) inspections they are still used.
I think the point Logan is making is that the original question was "How
long will this algorithm take to run?" and someone else said (essentially)
"200 million." To which Logan responds "200 million what? Milliseconds?
Clock cycles? Something else?"
Therefore, "200 million" is an "incorrect" answer in that it does not
actually answer the question asked.
- Oliver
Article: 104854Weng Tianxiang schrieb: > Hi Kolja, > I am talking about a real world measurements, not a theoretical one: > 1. Input data are in random; > 2. Input data are 32-bit or 64-bit; > 3. Sorting must be stable; > > Radix sort cannot be applied to my case: how can you sort by 11-bit for > a data set of 32-bits? You may imagine a set of data with same all > lowest 11 bits, but different upper 21 bits? Maybe this would be the time to read up how radix sort works? Hint: Try google. Radix sort is stable. It can applied to all sorting problems, it just might not be the fastest one. E.g. unlinke other methods it will be half the speed for 64-bit than for 32-bit. Hint: In my post I spoke about three passes with 11-bits or two passes with 16-bit. How does this relate to the 32-bit of the values? > PC running frequency and cache size are not my concern, because when a > coefficient is given, a PC frequency and cache size may be appended to > the result and everyone knows their relations. Definitely not. Cache access time is access pattern dependant. Kolja SulimmaArticle: 104855
Weng Tianxiang wrote: > > <snip> > > If a table of coefficient can be available based on frequency and cache > size, it is convenient for everyone to get a taste on how fast a > sorting algorithm is. > Would you add another axis to the table for Issue width? Retirement width? The number of ALUs? What about ALUs of a certain type? Perhaps an entry for the number of architected vs physical registers? What about the latency of a cache hit? The latency of a miss? What about the size of L1 vs L2 vs L3? Inclusive or exclusive caches? Interconnect network? Memory interface? Microcode issues? (This list could go on for pages)) I believe I understand what you're attempting to do but the number of performance altering variables you would be omitting is astounding. That's part of the reason such constants are ignored in complexity theory. If you would like to make up some magic number for your particular hardware, algorithm, coding style, compiler, etc feel free. Will that constant mean anything on another system? Generally not.Article: 104856
The following is taken from a Xilinx Webcase (18292, http://tinyurl.com/hclbc) "My design is a simple circuit with an IOB that utilizes an output FF, IOBUF PCI, and an input FF. The timing tools analyze a path from the output FF through IOBUF PCI to the input FF. However, if I change the IOSTANDARD attribute to another value (like LVTTL) , TRACE does not show a path from the output FF through IOBUF LVTTL to the input FF." The web case says it is normal that XST analyses it but does not say why it should be. Anybody has an explanation? This path makes meeting PCI timings pretty tough! Many thanks, Jean-Baptiste.Article: 104857
What I was told by my FAE is that the PCI timing specs cannot rely on the actual pad for a good signal in the allocated time. The reflections from several loads across a PCI-appropriate distance would take enough time to propagate out through the PCB traces and reflect back without a valid logic level on the driving pad that the bypass was needed in order to *meet* PCI timing. If the signals in question are signals that you don't need your own output to drive your input, you can constrain those paths so the feedback is ignored. If you need the feedback, the internal route is the "appropriate" route. If your system is embedded such that you don't have to worry about long traces with multiple loads, you can relax your Tcko, Tsu, and probably Thold values as well and be perfectly PCI compatible, just not PCI compliant. Also, a DCM might work well in systems where you know you will always have a clock. So. . . what do you need? If you need more detail, you could provide the device - family, size, speed grade - for a little better footing for anyone intersted in bringing up PCI numbers from current or past projects. I'm in a Spartan3E, -5 speed grade with decent timing. My Spartan3 -4 design was nudged a little on some of the numbers if I recall correctly but perfectly fine for my embedded system. <jean-baptiste.nouvel@jdsu.com> wrote in message news:1152283793.777918.296440@b28g2000cwb.googlegroups.com... > The following is taken from a Xilinx Webcase (18292, > http://tinyurl.com/hclbc) > > "My design is a simple circuit with an IOB that utilizes an output FF, > IOBUF PCI, and an input FF. The timing tools analyze a path from the > output FF through IOBUF PCI to the input FF. However, if I change the > IOSTANDARD attribute to another value (like LVTTL) , TRACE does not > show a path from the output FF through IOBUF LVTTL to the input FF." > > The web case says it is normal that XST analyses it but does not say > why it should be. Anybody has an explanation? > > This path makes meeting PCI timings pretty tough! > > Many thanks, > > Jean-Baptiste.Article: 104858
Hi, Does anyone has a description of Virtex4 Mini-Module GigaBit LAN Phy (BCM5461) PCS registers? I desperately need them to properly setup PHY interupt line to work with Gigabit System Reference Design 2. Cheers, GuruArticle: 104859
Hi, all: I know there are some differences between SLICEM and SLICEL, like "only the SLICEM has the RAM feature, SLICEL is just an LUT". In my opinion, the LUT/RAM in SLICEM can be understood as a writeable LUT, and the LUT in SLICEL is not writeable. Is it right? Thank you.Article: 104860
"Stanley Lee" <lizhongqi@hotmail.com> wrote in message news:1152287602.749092.204580@s13g2000cwa.googlegroups.com... > Hi, all: > I know there are some differences between SLICEM and SLICEL, like "only > the SLICEM has the RAM feature, SLICEL is just an LUT". > In my opinion, the LUT/RAM in SLICEM can be understood as a writeable > LUT, and the LUT in SLICEL is not writeable. Is it right? > > Thank you. You're pretty much right but one aspect that isn't as clear in your delineation is that the "writeable LUT" can also be used as a shift register with a 16:1 mux for which bit in the shift register to use. The "writeable LUT" can also be used as a dual-port memory allowing writes independent of read. Both of these features are extremely useful in many designs as long as you know you can leverage them.Article: 104861
Hi, I am still confused about the usage of SRL16 in reset circuit, if I am using a single clock which is got out of a DCM, is the SRL16 unnecessary? Or, I should use it to syncronize the reset signal, just like a FF? I think if I connect a FF to the LOCKED pin of DCM, I can get the same as SRL16, because the LOCKED pin will be avalid only when the clock output is stable, so the SRL16 is unnecessary, a single FF is OK, too. Can anybody give me some example of using SRL16 in reset circuit, please? Both code examples and application notes are OK. Thank you very much!Article: 104862
Hi, thank you very much for the very quick answer! > What I was told by my FAE is that the PCI timing specs cannot rely on the > actual pad for a good signal in the allocated time. The reflections from > several loads across a PCI-appropriate distance would take enough time to > propagate out through the PCB traces and reflect back without a valid logic > level on the driving pad that the bypass was needed in order to *meet* PCI > timing. I am not quite sure to understand. If we take the example of the AD signals then, by the time it is next driven/read, it is 33 ns later, and the lines have had time to settle? Or I am misunderstanding something? > If the signals in question are signals that you don't need your own output > to drive your input, you can constrain those paths so the feedback is > ignored. If you need the feedback, the internal route is the "appropriate" > route. I take it it is the case of the AD signals. Then how do you constrain the paths so that the feedback is ignored? I was told this is a simple UCF constraint on Virtex 4 but I use a Spartan 3. > If your system is embedded such that you don't have to worry about long > traces with multiple loads, you can relax your Tcko, Tsu, and probably Thold > values as well and be perfectly PCI compatible, just not PCI compliant. I was indeed thinking of relaxing the timings for some other timing violation. > Also, a DCM might work well in systems where you know you will always have a > clock. What would you use the DCM for? > So. . . what do you need? If you need more detail, you could provide the > device - family, size, speed grade - for a little better footing for anyone > intersted in bringing up PCI numbers from current or past projects. I'm in > a Spartan3E, -5 speed grade with decent timing. My Spartan3 -4 design was > nudged a little on some of the numbers if I recall correctly but perfectly > fine for my embedded system. I use a Spartan 3 XC3S1500-4. Again, thank you very much for your time. Thanks, jbArticle: 104863
rickman wrote: > > I don't know what is so different about the TTL FF because no one has > explained why it is soooo "bad". A TTL-fli-flop uses far more transistors than a CMOS flip-flop does. There are no pass gates in TTL. Also, bipolar TTL cicuits combined relatively slow transistors with relatively fast metal-interconnect. In CMOS it's the other way round: extremely fast transistors, but relatively slow capacitively loaded interconnects. If I simplify my explanation and claim that the phase delay through the two cascaded inverters is insignificant compared to the phase delay through the pass transistor, (loaded by the input capacitance,) then my explanation becomes very clear: the response must be monotonic. It's like the old thumb rule: You can always prevent a feedback system from oscillating, if you make one of the low-pass time constants dominant, i.e. much slower than all the others. Somebody with a more recent education and stronger background in linear circuit analysis and feedback theory (someone who can analyze the response of a PLL) can surely give a more quantitative answer. Don't leave me alone. The solution is staring you in the face ! Peter AlfkeArticle: 104864
Guru schrieb: > Hi, > > Does anyone has a description of Virtex4 Mini-Module GigaBit LAN Phy > (BCM5461) PCS registers? I desperately need them to properly setup PHY > interupt line to work with Gigabit System Reference Design 2. > > Cheers, > > Guru you may need to sign and NDA to get the datasheet for the broadcom PHY :( its really annoying that some silicon and IP vendors only have product briefs available for downloads AnttiArticle: 104865
hi all, while generating the bitstream for a design with two processors and ddr sdram i'm getting the following error in edk 7.1i .....could anybody please state the cause of this error .... FATAL_ERROR:Bitgen:Portability/export/Port_Main.h:127:1.17.12.6 - This application has discovered an exceptional condition from which it cannot recover. Process will terminate. To resolve this error, please consult the Answers Database and other online resources at http://support.xilinx.com. If you need further assistance, please open a Webcase by clicking on the "WebCase" link at http://support.xilinx.com note: i'm a student ...so i cannot access Webcase feature .... hence this is my only way out ... SAVSArticle: 104866
savs schrieb: > hi all, > while generating the bitstream for a design with two processors and ddr > sdram i'm getting the following error in edk 7.1i .....could anybody > please state the cause of this error .... > > FATAL_ERROR:Bitgen:Portability/export/Port_Main.h:127:1.17.12.6 - This > application has discovered an exceptional condition from which it > cannot > recover. Process will terminate. To resolve this error, please > consult the > Answers Database and other online resources at > http://support.xilinx.com. If > you need further assistance, please open a Webcase by clicking on the > "WebCase" link at http://support.xilinx.com > > note: i'm a student ...so i cannot access Webcase feature .... hence > this is my only way out ... > > SAVS FATAL_ERROR:Bitgen:Portability/export/Port_Main.h:127 the h:127 is VERY famous Xilinx Error - it tells you nothing what actually went wrong and isnt helpful at all finding the problem. the only solution is usually to start your project from scratch or wait for ISE/EDK upgrade or service pack release. Antti http://antti-brain.comArticle: 104867
Stanley The problem is in the interaction of a free-running clock and an asynchronous reset signal that has different distribution delays to different destination flip-flops. If you stop the clock until after the end of reset, there can never be a problem. But few designs do. When the clock is running while the asynchronous reset ends in a poorly controlled way (at different times at different flip-flops), then you have a problem, and the solution is to stretch the reset in a synchronous way, probably for several clock cycles. And the SRL16 is the cheapest solution. Peter Alfke, Xilinx ============== Stanley Lee wrote: > Hi, > I am still confused about the usage of SRL16 in reset circuit, if I am > using a single clock which is got out of a DCM, is the SRL16 > unnecessary? Or, I should use it to syncronize the reset signal, just > like a FF? I think if I connect a FF to the LOCKED pin of DCM, I can > get the same as SRL16, because the LOCKED pin will be avalid only when > the clock output is stable, so the SRL16 is unnecessary, a single FF is > OK, too. > > Can anybody give me some example of using SRL16 in reset circuit, > please? Both code examples and application notes are OK. > > Thank you very much!Article: 104868
Hello! Everybody I got a double port RAM from Xilinx IP core generater. I test it. There is always one warning : No primary, secondary unit in the file "D:/FPGA/testram/testram/ram1.vhd. Ignore this file from project file "testram_vhdl.prj". I don't know what is it? Does any nice people tell me the reason. I got the vhdl function model of this block ram from IP core generater. ---------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL; Library XilinxCoreLib; ENTITY ram1 IS port ( addra: IN std_logic_VECTOR(2 downto 0); addrb: IN std_logic_VECTOR(2 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(7 downto 0); wea: IN std_logic); END ram1; ARCHITECTURE ram1_a OF ram1 IS component wrapped_ram1 port ( addra: IN std_logic_VECTOR(2 downto 0); addrb: IN std_logic_VECTOR(2 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(7 downto 0); wea: IN std_logic); end component; -- Configuration specification for all : wrapped_ram1 use entity XilinxCoreLib.blkmemdp_v6_1(behavioral) generic map( c_reg_inputsb => 0, c_reg_inputsa => 0, c_has_ndb => 0, c_has_nda => 0, c_ytop_addr => "1024", c_has_rfdb => 0, c_has_rfda => 0, c_ywea_is_high => 1, c_yena_is_high => 1, c_yclka_is_rising => 1, c_yhierarchy => "hierarchy1", c_ysinita_is_high => 1, c_ybottom_addr => "0", c_width_b => 8, c_width_a => 8, c_sinita_value => "0", c_sinitb_value => "0", c_limit_data_pitch => 18, c_write_modeb => 0, c_write_modea => 0, c_has_rdyb => 0, c_yuse_single_primitive => 0, c_has_rdya => 0, c_addra_width => 3, c_addrb_width => 3, c_has_limit_data_pitch => 0, c_default_data => "0", c_pipe_stages_b => 0, c_yweb_is_high => 1, c_yenb_is_high => 1, c_pipe_stages_a => 0, c_yclkb_is_rising => 1, c_yydisable_warnings => 1, c_enable_rlocs => 0, c_ysinitb_is_high => 1, c_has_default_data => 1, c_has_web => 0, c_has_sinitb => 0, c_has_wea => 1, c_has_sinita => 0, c_has_dinb => 0, c_has_dina => 1, c_ymake_bmm => 0, c_has_enb => 0, c_has_ena => 0, c_depth_b => 8, c_mem_init_file => "mif_file_16_1", c_depth_a => 8, c_has_doutb => 1, c_has_douta => 0, c_yprimitive_type => "16kx1"); BEGIN U0 : wrapped_ram1 port map ( addra => addra, addrb => addrb, clka => clka, clkb => clkb, dina => dina, doutb => doutb, wea => wea); END ram1_a; -- synopsys translate_onArticle: 104869
Hello, If I recall correctly, this source sampling bypass requirement was not present in the PCI Local Bus Specification v2.1, but was added in v2.2. It applies to both PCI and PCI-X, at all frequencies. The rule is that a device cannot "receive" a signal from the pad at the same time it is also driving the pad. Instead, the outbound signal (prior to the output driver) must be used to bypass the inbound signal (after the input buffer). It is natural that you'd want to do this with the tristate control signal. The reason for this requirement is the specification claims that the timing budget does not cover the time for the "reflected wave" to return to the driving device in time to be properly received by the next clock edge. As you pointed out, it is hard to imagine this being a big issue at 33 MHz, but at 133 MHz, I would not dare ignore it. Xilinx has implemented this feature directly in the IOB starting with the Virtex-2 family. This way, any customer using the PCI or PCI-X select I/O modes can be confident they have something that complies with this specification requirement without having to give it too much thought... It should be handled "automatically". It is curious that you are having trouble with timing through this path, but I guess it will depend on how you have constructed your interface. I suggest you file a webcase with Xilinx customer applications for assistance. EricArticle: 104870
<jean-baptiste.nouvel@jdsu.com> wrote in message news:1152288923.625775.261720@m79g2000cwm.googlegroups.com... > I am not quite sure to understand. If we take the example of the AD > signals > then, by the time it is next driven/read, it is 33 ns later, and the > lines have > had time to settle? Or I am misunderstanding something? With the Tcko specified for 33 MHz PCI feeding the required Tsu with as many PCI slots and loads as are permitted for 33 MHz PCI along with the prescribed clock skew limit, the reflected wave may not guarantee a valid logic level under all conditions. It doesn't seem to make sense from the 20k foot perspective, but the timing budgets are what they are for specific reasons. > I take it it is the case of the AD signals. Then how do you constrain the > paths so that the feedback is ignored? I was told this is a simple UCF > constraint > on Virtex 4 but I use a Spartan 3. The constraint is the same for Virtex-4 as it is for Spartan-3. I think I'd use a TIG, speciying the output FFS to the input FFS. The core's pcim_lc wrapper file would have the literal names for those registers and the Constraints Guide available in the xilinx.com online documentation would provide the syntax for the TIG. > What would you use the DCM for? If you can gurantee a clock is always present and stable, the DCM can improve the I/O timing for the FPGA. I believe the Tcko to Tsu requirement is actually less when the DCM is used but I haven't compared the non-DCM numbers lately. I've found it helpful to tune the Tcko (or Tckon) times relative to the PCI clock pad to be at the PCI timing limits and manipulate the placement for best Tsu. _____ I don't believe the -4 speed grade can give you PCI compliance so PCI compatible operation is probably your goal. You can look at your system timing budget using the PCI numbers as a guide but make the engineering decisions on your own implementation. Just improving on clock skew from the 2 ns datum for 33 MHz PCI is a lot of time to recoup as long as you can guarantee the skew for all elements in the system (such as a plug-in board from another manufacturer).Article: 104871
"Kolja Sulimma" <news@sulimma.de> wrote in message news:44ae25a9$0$26267$9b4e6d93@newsread2.arcor-online.net... > Weng Tianxiang schrieb: >> Hi Wong, >> n*log2(n) is the number of comparison operations that must be done with >> a comparison sorting algorithm. > > Forget about comaprisons on PC hardware. You are interested in the > number of load/stores because these are a lot slower than comparisons. > A typical comparison sort will have two loads and two store per > comparison. > > Radix Sort with 11-bit digits requires three O(N) passes for a total of > about 12M loads and 6M stores. > If your cache is big enough you could also do only two passes using > 16-bit digits. In the case of LSD radix sort, you can do both 16-bit counting passes in a single pass (count high 16 bits bucket and low 16 bits bucket when you access each element), hence only two passes over the data are needed (one pass to count and one pass to sort). Of course, you need 65536*2 buckets to hold your counts. If there are one million elements, you would need 32 bit buckets (actually, 20 bit buckets would do, but a 20 bit integer type would be pretty unusual).Article: 104872
Thomas and all, Actually, XST did introduce inference capabilities for parity bits in version 7.1i, but it was only for Virtex-4. In version 8.1i, that support was extended to all applicable families. This is documented in Answer Record 20829 (albeit in the future tense; I'll have that updated). thanks, david. Thomas Entner wrote: > The last time I tried, XST (ISE 7.1) did only infer *8/*16/*32-bit RAMs and > did not use the "parity" bits. Xilinx answered that this is a known > bug/limitation, don't know if it is fixed now. So I ended up in writting a > wrapper for BRAM-instantion... > > Thomas > > www.entner-electronics.com > > "Andy" <jonesandy@comcast.net> schrieb im Newsbeitrag > news:1152202901.742237.164620@a14g2000cwb.googlegroups.com... > >>Or just infer the block ram from an 9/18/36 bit wide array... >> >>Then you can store anything you like in the ram (std_logic, >>std_logic_vector, unsigned, integer, boolean, enumerated types >>(states!), records, etc. >> >>Check your synthesis manual for templates for inferring block ram from >>arrays. >> >>Andy >> >> >>Ray Andraka wrote: >> >>>PeterSmith1954@googlemail.com wrote: >>> >>> >>> >>>>The last time I used *9 / *18 / *36 mode block rams, I instantiated >>>>them as such and they exposed themselves as those *8 + the parity bit. >>>>Look for the instantiation template and you'll see what I mean. >>>> >>>>Just assign your ninth bit (for each block ram) to the parity bit. >>>> >>>>Cheers >>>> >>>>PeteS >>>> >>> >>>The primitives have the bits separated off as parity bits, but other >>>than the addressing considerations if you have different depths on the >>>dual ports, they are no different than the data bits. It may be easier >>>to deal with if you make a wrapper for the Xilinx primitives that bring >>>in/out an 18 bit bus. >> > >Article: 104873
Yes, I am aware of that. I was trying to make a shortcut. GuruArticle: 104874
On Fri, 07 Jul 2006 04:05:14 GMT, Logan Shaw <lshaw-usenet@austin.rr.com> wrote: > Weng Tianxiang wrote: >> 14.5* N * (lg N). > > Also, it's not clear whether lg() is a natural logarithm (the usual > symbol for that is ln()) or a base-2 logarithm or some other base. > So that adds in a second unknown constant factor. My Knuth books are at work, but I'm pretty certain that he makes it clear that lg() is log base 2, ln() is log base e and log10 is log base 10. I've never seen any of those notations used to mean anything else. If you had read any of the books, you would not have much doubt about Don being imprecise. A bientot Paul -- Paul Floyd http://paulf.free.fr (for what it's worth) Surgery: ennobled Gerald.
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z