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Messages from 104400

Article: 104400
Subject: Re: Achieving timing in Xilinx EDK designs
From: "Salil Raje" <salil.raje@xilinx.com>
Date: Mon, 26 Jun 2006 16:02:24 -0700
Links: << >>  << T >>  << A >>
Hi All -

You can download a full featured 30-day eval copy of PlanAhead at
www.xilinx.com/planahead
No obligation to buy and you can even finish your design in that time frame.

Salil



"Joseph Samson" <user@example.net> wrote in message
news:hlwng.72766$4L1.54616@newssvr11.news.prodigy.com...
> MM wrote:
> > "Joseph Samson" <user@example.net> wrote in message
> > news:RL%mg.122559$dW3.104421@newssvr21.news.prodigy.com...
> >
> > Thanks a lot Joe! AFAIK PlanAhead is quite expensive (not sure
though)... Is
> > it an essential tool to get the job done in your opinion?
> >
>   I'm sure that there are experts here who could floorplan a design with
> pencil and paper and get great results, I couldn't. The 30-day free
> trial was enough to convince me that it was a tool I wanted to keep. I
> wouldn't say it is essential for everyone or even every PPC system
> designer, but it is a great tool for understanding the timing errors
> you're getting and making changes to eliminate those errors.
>
>
> ---
> Joe Samson
> Pixel Velocity



Article: 104401
Subject: Re: ISE WebPack 8.2
From: "Tommy Thorn" <tommy.thorn@gmail.com>
Date: 26 Jun 2006 16:07:50 -0700
Links: << >>  << T >>  << A >>
Did you actually look at the Xilinx web site?  This page will answer
your question: http://www.xilinx.com/ise/devsys_feature_guide.pdf

AFAICT, WebPack 8.2 doesn't add any devices, not even a single Virtex
5.

Virtex II Pro is pretty old.  I wouldn't expect anything new happening
with that at any point (short of End Of Life).

Tommy



Roger wrote:
> Does anyone know if the 8.2 version of the ISE WebPack will support a wider
> range of devices or not? I'm particularly interested in the V II Pro range.
> 
> TIA,
> 
> Rog.


Article: 104402
Subject: Re: ISE WebPack 8.2
From: "Roger" <enquiries@rwconcepts.co.uk>
Date: Mon, 26 Jun 2006 23:19:57 GMT
Links: << >>  << T >>  << A >>
Tommy,

Thanks for your comments. As the version 8.2 is shown as "coming soon" on 
the web site, the documentation is therefore not necessarily up to date 
(that might also be "coming soon"), hence my question. In fact the page I 
found was still 8.1 http://www.xilinx.com/ise/products/webpack_config.htm. 
Quite reasonable I thought.

Rog.


"Tommy Thorn" <tommy.thorn@gmail.com> wrote in message 
news:1151363270.640830.232700@75g2000cwc.googlegroups.com...
> Did you actually look at the Xilinx web site?  This page will answer
> your question: http://www.xilinx.com/ise/devsys_feature_guide.pdf
>
> AFAICT, WebPack 8.2 doesn't add any devices, not even a single Virtex
> 5.
>
> Virtex II Pro is pretty old.  I wouldn't expect anything new happening
> with that at any point (short of End Of Life).
>
> Tommy
>
>
>
> Roger wrote:
>> Does anyone know if the 8.2 version of the ISE WebPack will support a 
>> wider
>> range of devices or not? I'm particularly interested in the V II Pro 
>> range.
>>
>> TIA,
>>
>> Rog.
> 



Article: 104403
Subject: Re: ISE WebPack 8.2
From: Jim Granville <no.spam@designtools.co.nz>
Date: Tue, 27 Jun 2006 12:04:11 +1200
Links: << >>  << T >>  << A >>
Roger wrote:

> Tommy,
> 
> Thanks for your comments. As the version 8.2 is shown as "coming soon" on 
> the web site, the documentation is therefore not necessarily up to date 
> (that might also be "coming soon"), hence my question. In fact the page I 
> found was still 8.1 http://www.xilinx.com/ise/products/webpack_config.htm. 
> Quite reasonable I thought.

There is some 8.2i marketing splurge here :

http://www.xilinx.com/ise/marketing/index.htm

Usual fluffy claims :
"Up to 30% faster than our previous software offering"
and
"delivering on average 30% faster performance than our previous release 
of software."

seems they confuse "Up to" and "average", and afetr reading this, I have
no idea if the COMPILE times average/up to 30% faster, or the device
operation itself is suddenly now 30% faster ( average/up to ?)

[Austin/Peter, doesn't anyone numerate actually proof-read this press 
release fluff ? ]

Back to Roger's question:
  Older devices are unlikely to 'move' much on the support list, but
I would be surprised if the Webpack (when released) did not support at 
least the smallest V5 - it is in Xilinx's interest to get design starts 
on their new devices asap.

-jg




Article: 104404
Subject: R: still having same error
From: "blisca" <blisca@tiscali.it>
Date: Tue, 27 Jun 2006 01:13:43 +0100
Links: << >>  << T >>  << A >>
I would like that some people that i know,that is still thinking that
internet it is just a waste of time could read the answers and the effort
done for helping me in this newsgroup.
Thank you again good people!

Diego

Ben Jones <ben.jones@xilinx.com> wrote in message
e7p2ca$8no1@cliff.xsj.xilinx.com...
>
> "blisca" <blisca@tiscali.it> wrote in message
> news:449fffdb$0$16939$4fafbaef@reader4.news.tin.it...
> > I.e . failed to access  library 'xilinxcorelib' at "xilinxcorelib"
> >
> > i ask,where is the path used for searching?in modelsim.ini?
>
> Read the Modelsim manual.
>
> > what does it means this sintax?
> > verilog = $MODELTECH/../verilog
>
> MODELTECH is an environment variable. It usually points to the directory
> containing the Modelsim binaries.
>
> > what are the dots about?
>
> .. = up one directory, because the libraries will usually be in a
directory
> parallel to the binary files, not in a subdirectory.
>
> > and  why slash is used?normally a path is indicated
> > using backslashes
>
> No, that's just Windows. The rest of the world uses forward-slashes for
path
> separators. Modelsim was originally a UNIX app and as such uses UNIX
> conventions all over the place.
>
>     -Ben-
>
>



Article: 104405
Subject: Re: keys to the Kingdom
From: "Dave Greenfield" <davidg@altera.com>
Date: 26 Jun 2006 18:11:33 -0700
Links: << >>  << T >>  << A >>
1. Stratix II FPGAs have been validated as conforming to FIPS-197
standard. You can refer to the NIST web site:
http://csrc.nist.gov/cryptval/aes/aesval.html.

2. NDA is no longer required for using the design security feature. NDA
is still required for getting more information about the key protection
as this adds one more level of protection.

3.  Readback is not available in Stratix II FPGAs, so there is no risk
of configuration file being read out after decryption.

4. Additional measures are taken to protect the encryption bits; some
will be discussed in the net seminar while other details are only
available under NDA.

Dave Greenfield
Altera Product Marketing


Article: 104406
Subject: Re: Space invaders on Spartan3e starter board
From: Mark McDougall <markm@vl.com.au>
Date: Tue, 27 Jun 2006 11:40:52 +1000
Links: << >>  << T >>  << A >>
Michael wrote:

> Nice application, was wondering where or how does one get the ROM
> needed to complete the design. Thanks.

Google for "mame roms invaders" or thereabouts...

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 104407
Subject: Re: keys to the Kingdom
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 26 Jun 2006 20:18:42 -0700
Links: << >>  << T >>  << A >>
Isn't Marketing wonderful...
Here we are discussing which physical implementation is more secure,
and dear Dave tells us that Altera was indeed smart enough to implement
the algorithm correctly. I would never have stooped so low to doubt
that. Yes, Altera can do logic design. Bravo! Advance to second grade!

The question, however, was totally different:  whether the key is
secure. And that is nowhere mentioned in that long URL.
Marketing 101:
If you have nothing good to say, throw in a big bunch of irrelevant
data.
That might defuse the argument. and calm down the waves...

Peter Alfke, who had expected a more relevant post from Altera.
Don't treat us like dummies.
============================
Dave Greenfield wrote:
> 1. Stratix II FPGAs have been validated as conforming to FIPS-197
> standard. You can refer to the NIST web site:
> http://csrc.nist.gov/cryptval/aes/aesval.html.
>
> 2. NDA is no longer required for using the design security feature. NDA
> is still required for getting more information about the key protection
> as this adds one more level of protection.
>
> 3.  Readback is not available in Stratix II FPGAs, so there is no risk
> of configuration file being read out after decryption.
>
> 4. Additional measures are taken to protect the encryption bits; some
> will be discussed in the net seminar while other details are only
> available under NDA.
> 
> Dave Greenfield
> Altera Product Marketing


Article: 104408
Subject: Accelerated Bioinformatics Data Processing Solutions
From: tali.cliff@gmail.com
Date: 26 Jun 2006 20:26:46 -0700
Links: << >>  << T >>  << A >>
Hi,
Just a note to let the community know of a new product - the BioBoost
from Progeniq - which accelerates computationally intensive
bioinformatics applications, at up to 50x-100x faster than on a typical
workstation processor. The BioBoost uses Field Programmable Gate Array
(FPGA) technology on a USB 2.0 or PCI based device, to accelerate
applications at significantly lower cost.
Do let me know if this may be of assistance to anyone, I'll be happy to
get in touch.
Cheers, Tali
www.progeniq.com
e-mail: tali@progeniq.com


Article: 104409
Subject: Re: Space invaders on Spartan3e starter board
From: Michael <michael.dangler@gmail.com>
Date: Mon, 26 Jun 2006 22:36:55 -0700
Links: << >>  << T >>  << A >>
Mark

Thank you, got the ROMs and all works great. Perfect way to test a new board.

Cheers, Michael

Article: 104410
Subject: Xilinx 7.1 ISE : Problem while doing post place and route simulation
From: "Srikanth BJ" <bj.srikanth@gmail.com>
Date: 26 Jun 2006 22:45:37 -0700
Links: << >>  << T >>  << A >>
Hi all,
 I am using Xilinx 7.1 ISE . I am facing a problem while doing post
place and route simulation.
I am using model sim 6.0 version. I get the following error while doing
post place simulation
"An error occurred while executing
D:/programfiles/xilinx/data/projnav/scripts/TclFileWrapper4Halite.tcl."
Has anybody faced a similar problem or has an idea about why  is it
coming?
Thanks in advance,
Srikanth


Article: 104411
Subject: Re: Space invaders on Spartan3e starter board
From: Mark McDougall <markm@vl.com.au>
Date: Tue, 27 Jun 2006 16:24:32 +1000
Links: << >>  << T >>  << A >>
Michael wrote:

> Thank you, got the ROMs and all works great. Perfect way to test a new board.

Just make sure you test it *thoroughly*!!! ;)

Regards,

-- 
Mark McDougall, Engineer
Virtual Logic Pty Ltd, <http://www.vl.com.au>
21-25 King St, Rockdale, 2216
Ph: +612-9599-3255 Fax: +612-9599-3266

Article: 104412
Subject: Re: ISE WebPack 8.2
From: Mike Harrison <mike@whitewing.co.uk>
Date: Tue, 27 Jun 2006 08:43:38 GMT
Links: << >>  << T >>  << A >>
On Mon, 26 Jun 2006 23:19:57 GMT, "Roger" <enquiries@rwconcepts.co.uk> wrote:

>Tommy,
>
>Thanks for your comments. As the version 8.2 is shown as "coming soon" on 
>the web site, the documentation is therefore not necessarily up to date 
>(that might also be "coming soon"), hence my question. In fact the page I 
>found was still 8.1 http://www.xilinx.com/ise/products/webpack_config.htm. 
>Quite reasonable I thought.

I had an email yesterday from Xilinx saying it was "Shipping Now"

Article: 104413
Subject: Webpack ISE 8 and Vertex4 XC4VLX60
From: "Vassili Savinov" <vassili.savinov@sharp.co.uk>
Date: Tue, 27 Jun 2006 02:11:04 -0700
Links: << >>  << T >>  << A >>
The free Xilinix ISE doesn't seem to support Vertex-4 LX60. How shoold Igo about writing a design for it?

Thank you

Article: 104414
Subject: Re: ISE WebPack 8.2
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 27 Jun 2006 09:14:54 +0000 (UTC)
Links: << >>  << T >>  << A >>
Mike Harrison <mike@whitewing.co.uk> wrote:
> On Mon, 26 Jun 2006 23:19:57 GMT, "Roger" 
> <enquiries@rwconcepts.co.uk> wrote:

> >Tommy,
> >
> >Thanks for your comments. As the version 8.2 is shown as "coming soon" on 
> >the web site, the documentation is therefore not necessarily up to date 
> >(that might also be "coming soon"), hence my question. In fact the page I 
> >found was still 8.1 http://www.xilinx.com/ise/products/webpack_config.htm. 
> >Quite reasonable I thought.

> I had an email yesterday from Xilinx saying it was "Shipping Now"

It said: ISE shipping, no word of Webpack...
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 104415
Subject: XC3SE available
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 27 Jun 2006 09:17:30 +0000 (UTC)
Links: << >>  << T >>  << A >>
Hello,

its seems that XC3SE is finally available, Digikey carries them and
announces them as available. Prices are attractive, starting at 6.37 Euro
for the XC3S100E-4VQG100C...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 104416
Subject: Re: multisource on signal in XPS
From: "savs" <vidyutg@gmail.com>
Date: 27 Jun 2006 02:26:56 -0700
Links: << >>  << T >>  << A >>
thanx a lot ppl ....... 

SAVS.


Article: 104417
Subject: Number of bonded IOB's
From: "savs" <vidyutg@gmail.com>
Date: 27 Jun 2006 02:29:39 -0700
Links: << >>  << T >>  << A >>
Hi all,
when trying to generate the System ACE file in ISE 7.1 for one of my
designs i get the error that no. of bonded IOB's have been exceeded
.....
what does this exactly mean and how can we rectify it ?

thanx in advance ....
SAVS.


Article: 104418
Subject: Re: Webpack ISE 8 and Vertex4 XC4VLX60
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Tue, 27 Jun 2006 10:44:49 +0100
Links: << >>  << T >>  << A >>
Vassili,
I'm afraid you need to buy full ISE for such a part.
Aurash
Vassili Savinov wrote:

>The free Xilinix ISE doesn't seem to support Vertex-4 LX60. How shoold Igo about writing a design for it?
>
>Thank you
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Article: 104419
Subject: Re: Webpack ISE 8 and Vertex4 XC4VLX60
From: "Jon Beniston" <jon@beniston.com>
Date: 27 Jun 2006 02:46:40 -0700
Links: << >>  << T >>  << A >>

Vassili Savinov wrote:
> The free Xilinix ISE doesn't seem to support Vertex-4 LX60. How shoold Igo about writing a design for it?

Buy the full version?

Jon


Article: 104420
Subject: Re: Number of bonded IOB's
From: Aurelian Lazarut <aurash@xilinx.com>
Date: Tue, 27 Jun 2006 10:55:16 +0100
Links: << >>  << T >>  << A >>
assuming this error comes from MAP, means that you ran out of available IOs.
Aurash
savs wrote:

>Hi all,
>when trying to generate the System ACE file in ISE 7.1 for one of my
>designs i get the error that no. of bonded IOB's have been exceeded
>.....
>what does this exactly mean and how can we rectify it ?
>
>thanx in advance ....
>SAVS.
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

Article: 104421
Subject: Re: Number of bonded IOB's
From: Uwe Bonnes <bon@hertz.ikp.physik.tu-darmstadt.de>
Date: Tue, 27 Jun 2006 09:56:13 +0000 (UTC)
Links: << >>  << T >>  << A >>
savs <vidyutg@gmail.com> wrote:
> Hi all,
> when trying to generate the System ACE file in ISE 7.1 for one of my
> designs i get the error that no. of bonded IOB's have been exceeded
> .....
> what does this exactly mean and how can we rectify it ?

Buy a bigger chip.

The message mean that you need more Pins then your choosen Chip/package
combination provides.

Bye
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Article: 104422
Subject: Synplify & Fedora core 5
From: Gilles GEORGES <georges@irisa.fr>
Date: Tue, 27 Jun 2006 12:18:33 +0200
Links: << >>  << T >>  << A >>
Dear all,

I'm trying to install a FPGA development platform under a Linux Fedora 
Core 5.
The only tool not working is Synplify. I have tried two different 
versions (7.3.3 and 8.5.1) but got same problem.

when trying to launch synplify_pro i got this :
---------------------------------------------
[georges@remix0 share]$ /local/share/fpga_85/bin/synplify_pro

***************************************************************

Warning: You are running on an unsupported platform
   'synplify_pro' only supports Redhat Enterprise Linux 3,4, SuSE 
Enterprise Linux Server 9

   current platform: Fedora Core release 5 (Bordeaux)
Kernel \r on an \m

***************************************************************

/local/share/fpga_85/linux/mbin/synplify: relocation error: 
/local/share/fpga_85/linux/mfw/lib-linux_optimized/libkernel32.so: 
symbol errno, version GLIBC_2.0 not defined in file libc.so.6 with link 
time reference
[georges@remix0 share]$
-------------------------------------------

The FC5 seems not to be supported, does anyone experience to make it run 
under FC5 ?
I plan to try why a FC4, any expérience ?

Thanks in advance

Gilles

Article: 104423
Subject: need help plz.
From: "lenile84" <EzzEldine@gmail.com>
Date: 27 Jun 2006 03:27:41 -0700
Links: << >>  << T >>  << A >>
 i need  a VHDL code for interface between a pc and FPGA kit (flex10ke)
to exchange data.
this programme i will use to make a demo for our project which is
implementing CDMA is95 on the that kit by sending users from serial
port on pc to kit and receive it again to another pc .
the two pc act as BAse station and mobile set. thanks in advance.
e-mail ezzeldine@gmail.com


Article: 104424
Subject: Re: Xilinx Floating Point C Simulation aka VHDL/Verilog --> C Conversion?
From: "Simon Heinzle" <sheinzle@inf.ethz.ch>
Date: Tue, 27 Jun 2006 13:01:12 +0200
Links: << >>  << T >>  << A >>
Hi John and cds,

> People simulate for two reasons ... to prove correctness, and to
> evaluate timings and performance. The translation from HDL to C is
> primarily simulation to verify correctness, especially where cores are
> involved. Timing/performance simulation requires a very tight
> integration with the target tool chain and architecture, something lost
> with generic C simulation of an HDL source.

We have an arithmetic C model with standard IEEE single precision floats. 
However, in our FPGA implementation we use several different (custom) 
floating point formats, mainly due to the limited resources.

The C model is used to generate stimuli vectors for the HDL simulation. 
Surely we play tricks to quantize the intermediate results of the single 
precision operations, but the results often differ (in a few bits) from the 
HDL simulation, which is quite annoying (and not practical for automated 
testing).

In short: I'm just looking for a bit-accurate (non cycle-accurate) model of 
the Floating Point Operators from Xilinx.

Thanks,

Simon





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