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Has anybody managed to compile the Xilinx cable drivers for Linux kernel 2.6 available here: http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=22648 ftp://ftp.xilinx.com/pub/utilities/M1_workstation/linuxdrivers.2.6.tar.gz with kernel 2.6.16? The problem is with windrvr6 driver. After ./configure and ./make I get a bunch of errors: /lib/modules/2.6.16.18/build/include/asm/rwsem.h: In function '__down_read': /lib/modules/2.6.16.18/build/include/asm/rwsem.h:105: error: syntax error before 'KBUILD_BASENAME' /lib/modules/2.6.16.18/build/include/asm/rwsem.h: In function '__down_write': /lib/modules/2.6.16.18/build/include/asm/rwsem.h:157: error: syntax error before 'KBUILD_BASENAME' /lib/modules/2.6.16.18/build/include/asm/rwsem.h: In function '__up_read': /lib/modules/2.6.16.18/build/include/asm/rwsem.h:194: error: syntax error before 'KBUILD_BASENAME' -- TIA & Regards, Wojtek ZabolotnyArticle: 104326
wich kind of simulator should i download or purchase for include in simulation the ram genarated with core generator?thanksArticle: 104327
thanks for help blisca <blisca@tiscali.it> wrote in message 449a8f47$0$3120$4fafbaef@reader1.news.tin.it... > how can i do to make it work with this old devices?experimenting with an old > board i need to add xcs30 and i need a tool(older impact versions) for > programming it,i guess that treatin it as an xc2s30 is not the right way to > proceed > Thanks to everyone > Diego > >Article: 104328
I have found the following site: http://gentoo-wiki.com/HOWTO_Xilinx which also discusses the 2.6.16 issues: http://gentoo-wiki.com/Talk:HOWTO_Xilinx However after downloading and unpacking the http://www.jungo.com/download/WD702LN.tgz I've modified the CFLAGS in redist/makefile in slightly simpler way - just changing/adding two definitions in CFLAGS: -DKBUILD_MODNAME=\"windrvr6\" -DKBUILD_BASENAME=\"windrvr6\" So the problem with the original version was: 1. old version of windrvr6 source which caused udev problems 2. wrong definition of KBUILD_MODNAME 3. lack of KBUILD_BASENAME definition -- HTH & Regards, WojtekArticle: 104329
As outputs driven low, IOBs can be a reasonable ground. It's not a precise ground but similar to adding a low value resistor to your other PCB. If your other device is a low current device (I'm looking at using this scheme for <1mA powered microphones) then it's a ground for all intents and purposes. If you want to carry significant power, you may have issues. The I-V characteristics for the low-driven output type you implement will determin how low an equivalent resistor you have. "Jaime Andrés Aranguren Cardona" <jaime.aranguren@gmail.com> wrote in message news:1151093919.431293.317490@u72g2000cwu.googlegroups.com... > Hi, > > Is it possible to programmatically configure pins of an Spartan3 or 3E > as ground signals? I mean, not only configure them as input signals, > but as real ground signals connected to the ground signal on another > PCB. > > Regards, > > JaaC >Article: 104330
Jaime Andr=E9s Aranguren Cardona wrote: > Is it possible to programmatically configure pins of an Spartan3 or 3E > as ground signals? Yes, an active Low output represents a low impedance to ground, somewhere around 10 Ohm. You can easily measure this by pulling the pin to Vcc through a 100 Ohm resistor, and measuring the pin voltage. Users have also used such an output in the opposite way: Connect the pin to the pc-board ground, and thus reduce the ground-bounce by providing additional connections between chip ground and pc-board ground. Peter Alfke, XilinxArticle: 104331
For these cases I would do a multiplication by 3 or 5 and a division by powers of two by shifting down. Should be faster and simpler. Peter Afke ================ agou wrote: > hi, there > > in my project, i need to do some multiplication. and i optimized the > multiplicand to numbers like 0.75, 0.625. I wonder would the > synthesizer automatically detect them like 0.75 = 1 - 1/4, 0.625 = 1/2 > + 1/8, or i need to code it manually in this way? > > does it differ across different synthesizer? i am using xilinx > synthesizer. > > thanks > ZhaoyiArticle: 104332
Yes (Ralf). That is precisely what I am looking for - How can I apply stimulus from a PC?. Can you give me some examples of how the PC can interface to the FPGA? Ralf Hildebrandt wrote: > Let me add: After the simulation tests the real hardware tests at the > FPGA have to be done either using some pins and applying the stimuli > from another device, like a personal computer or using a synthesized > testbench, that has to be build additionally to the design. > > > RalfArticle: 104333
MM wrote: > Hi all, > > I was wondering if anyone would be willing to share their experiences with > regards to what can be done when a design containing an EDK submodule fails > to meet timing after another IP core has been added to one of the buses? In > the latest particular case I added an opb2plb bridge and that broke the > timing. The OPB bus already runs at half of the PLB rate, and the PLB rate > is 100 MHz. > > Also, are there any estimates of how many loads can be added to PLB and/or > OPB at various rates? I'm surprised that more people don't have this complaint. I struggled with this last year, and was only able to make timing by getting a copy of PlanAhead and heavily floorplanning my design. I had to go so far as to take a module like PLB_EMAC and floorplan each individual sub-module. In a typical PPC design, we have PLB_EMAC (or PLB_GEMAC), PLB_SDRAM, some PLB_BRAM, a PLB_IPIF, OPB2PLB bridge, OPB_EMC, OPB_GPIO and a couple of OPB_UARTs. The PLB & OPB buses run at 100MHz in a V2P20, V2P30 or V2P50. Once you have a good floorplan the timing problems go away. --- Joe Samson Pixel VelocityArticle: 104334
"Joseph Samson" <user@example.net> wrote in message news:RL%mg.122559$dW3.104421@newssvr21.news.prodigy.com... > > I'm surprised that more people don't have this complaint. I struggled > with this last year, and was only able to make timing by getting a copy > of PlanAhead and heavily floorplanning my design. I had to go so far as > to take a module like PLB_EMAC and floorplan each individual sub-module. > In a typical PPC design, we have PLB_EMAC (or PLB_GEMAC), PLB_SDRAM, > some PLB_BRAM, a PLB_IPIF, OPB2PLB bridge, OPB_EMC, OPB_GPIO and a > couple of OPB_UARTs. The PLB & OPB buses run at 100MHz in a V2P20, V2P30 > or V2P50. Once you have a good floorplan the timing problems go away. Thanks a lot Joe! AFAIK PlanAhead is quite expensive (not sure though)... Is it an essential tool to get the job done in your opinion? /MikhailArticle: 104335
"anand" <writeanand@gmail.com> wrote in message news:1151019005.013194.112220@i40g2000cwc.googlegroups.com... >I am planning on buying either a Xilinx Spartan or Altera Development > Kit to test out some designs on FPGA. (I am New to FPGAs). > > Question: > > Once the design has been downloaded into the FPGA, how do I apply > stimulus and test the design? I believe several methods are possible, > but I would like one where both the stimulus (is applied in) and the > response (is checked) using a high level language like C or C++. > Are there any C/C++ "APIs" that allow the FPGA pins to be "wiggled"? > That way I can write C or C++ code to run a real "app". > To be precise :-) yes you can use a C API to talk to your design without using external stimuli/logic analyser etc. However, this is not commonly done and will mean extra $$$. I would however follow Mike's advice to first test your design to death using a testbench before downloading it to your FPGA. Using a simulator is a much better environment than debugging the actual hardware. To answer the precise remark, you can use a product called Dialite from Temento (there are probably others as well) to add stimuli and monitor instruments (small synthesizable blocks) around your core. You then use the JTAG/Custom port + supplied C API (or Tcl and Perl) to drive the stimuli and to read the monitor instruments. Thus in effect you have virtual hardware environment around your core connected to a C API. Hans www.ht-lab.comArticle: 104336
Eric <jonas@mwl.mit.edu> wrote: > > I got it from : > > http://www.rogerstech.force9.co.uk/ > > http://www.rogerstech.force9.co.uk/xc3sprog/index.html > > (seems to be the webpage of the author...) > > > > Sandro > Wow, I swear I started with the same copy. I don't know how that > happened... try again? Revision 2 should be the latest latest. What is the Sourceforge Web Address? http://xc3sprog.sourceforge.net/ is available, but seems empty. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 104337
Peter Alfke wrote: > Jaime Andr=E9s Aranguren Cardona wrote: > > Is it possible to programmatically configure pins of an Spartan3 or 3E > > as ground signals? > > Yes, an active Low output represents a low impedance to ground, > somewhere around 10 Ohm. You can easily measure this by pulling the pin > to Vcc through a 100 Ohm resistor, and measuring the pin voltage. > > Users have also used such an output in the opposite way: > Connect the pin to the pc-board ground, and thus reduce the > ground-bounce by providing additional connections between chip ground > and pc-board ground. > Peter Alfke, Xilinx Peter; So this is what happens when a CPLD pin is set as a PGND? =20 -Dave PollumArticle: 104338
When I first unpacked my S3Esk and tried it out, I used Chipscope on a WinXP system to download bitstreams. Chipscope is pretty agnostic about drivers, firmware etc and doesn't usually insist on updating. I tried installing the USB drivers on an FC3 Linux system (2.6.12.1-1373_FC3 kernel) with WebPack 8.1. I got the windrvr6 installed, ran Impact and it saw the S3Esk but insisted on updating the firmware. Impact eventually got to 92% and bailed on the update, leaving the CPLD programming unfinished. Further action in Impact on Linux resulted in repeated attempt/failure to update. Putting the S3Esk on WinXP+Impact updated the firmware and worked fine. Taking it back to Linux resulted in repeated attempts to update the already updated firmware. My motherboard is fairly old and the on-board USB is 1.1, so the driver was complaining that it wanted to be plugged into a USB2.0 port. When I hooked it to a USB2.0 on a PCI card then it started at high speed but then backed off to full speed. Then iMPACT couldn't open it up. I see others have gotten Linux + USB cable working. Anyone gotten the S3E Starter kit working? ThxArticle: 104339
Uwe Bonnes wrote: > Eric <jonas@mwl.mit.edu> wrote: > > > I got it from : > > > http://www.rogerstech.force9.co.uk/ > > > http://www.rogerstech.force9.co.uk/xc3sprog/index.html > > > (seems to be the webpage of the author...) > > > > > > Sandro > > > Wow, I swear I started with the same copy. I don't know how that > > happened... try again? Revision 2 should be the latest latest. > > What is the Sourceforge Web Address? > http://xc3sprog.sourceforge.net/ is available, but seems empty. > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- Uwe, I'm sorry, the main project site is at: http://sourceforge.net/projects/xc3sprog I was meaning to put up something in the web space of the project but I haven't had time to yet. ...EricArticle: 104340
ekrads@gmail.com wrote: > Yes (Ralf). That is precisely what I am looking for - How can I apply > stimulus from a PC?. This strongly depends on your application and your available tools. In general your stimuli are generated by bit-banging. You could e.g. write a software that pulls up and down the pins of a RS232 connector. Or you could transmit data packages (via RS232, USB or whatever) to a receiver inside the FPGA (you need to build such one!) and apply "pre-computed" stimuli to your device under test. > Can you give me some examples of how the PC can interface to the FPGA? You should not start with such a difficult task. You should first write a VHDL simulation testbench and test your design with this one. Then you should think about dedicated test hardware to test your design in the real world inside an FPGA. Getting hardware to run is something that comes very late in the design process. I spend months until I only touched my first FPGA. Afterwards I worked for years without touching the hardware that I have modeled. (My testpattern where applied via a microcontroller at a tester. I have never seen this tester.) First model, then simulate, then synthesize and simulate again (the netlist) and then you are almost done. Only after these steps hardware is needed. RalfArticle: 104341
Hello folks, I have done FPGA design some years ago using a Schematic Design tool from Xilinx, so I am not totally "green". What I now want to do is to specify a design in VHDL and synthesize it into an FPGA. I am doing this as a hobby venture, so I can't pay thousands of $$ for design software. Can the experts of this newsgroup suggest a demo board and free/cheap software that fulfill those requirements ? Maybe a board from Xilinx and their ISE software? (I could not find out whether ISE actually includes VHDL synthesis...) As an alternative, I would be willing to specify my design in C if there is a free/cheap synthesis tool...Article: 104342
frankgerlach@gmail.com wrote: >I have done FPGA design some years ago using a Schematic Design tool >from Xilinx, so I am not totally "green". What I now want to do is to >specify a design in VHDL and synthesize it into an FPGA. I am doing >this as a hobby venture, so I can't pay thousands of $$ for design >software. Can the experts of this newsgroup suggest a demo board and >free/cheap software that fulfill those requirements ? Maybe a board >from Xilinx and their ISE software? (I could not find out whether ISE >actually includes VHDL synthesis...) As an alternative, I would be >willing to specify my design in C if there is a free/cheap synthesis >tool... The free Webpack software includes VHDL and Verilog synthesis. -- Phil Hays (Xilinx, but speaking for himself)Article: 104343
Hi Frank, I am interested in the same thing as you are now (building hardware on FPGAs for hobby, on low budget). I want to use this to learn HW design and more importantly, microarchitecture specification to achieve desired performance. For starters., I have done some research already on (project ideas, books to buy, HW and SW to buy etc). I also have about 6 years in SoC Verification and know Verilog / digital design pretty well. Let me know if you are interested in pursuing this "hobby" together. -Anand frankgerlach@gmail.com wrote: > Hello folks, > I have done FPGA design some years ago using a Schematic Design tool > from Xilinx, so I am not totally "green". What I now want to do is to > specify a design in VHDL and synthesize it into an FPGA. I am doing > this as a hobby venture, so I can't pay thousands of $$ for design > software. Can the experts of this newsgroup suggest a demo board and > free/cheap software that fulfill those requirements ? Maybe a board > from Xilinx and their ISE software? (I could not find out whether ISE > actually includes VHDL synthesis...) As an alternative, I would be > willing to specify my design in C if there is a free/cheap synthesis > tool...Article: 104344
hey all, We are working on platform studio trying to make multicore processors. Theres one error "Multisource on signal " and v are not able to tackle it yet. So please reply and help us move ahead.. thanks in advance cheers SAVSArticle: 104345
basically we are using ddr ram and the multi source error is coming for the signal sys_clk in dcm module....... thanx again SAVS.Article: 104346
anand wrote: ... > Verification and know Verilog / digital design pretty well. Let me know > if you are interested in pursuing this "hobby" together. Hi Anand, that is a very good idea ! Send me your email address to fgerlach AT gmail.com !Article: 104347
Wouldn't it also be possible to use the parallel port of a PC to drive the inputs of the FPGA and read back the output signals ? (Of course, some TTL chips might be necessary in addition to that) The PC would also drive the clock of the FPGA in order to "slow down" the circuit.Article: 104348
MM wrote: > "Joseph Samson" <user@example.net> wrote in message > news:RL%mg.122559$dW3.104421@newssvr21.news.prodigy.com... > > Thanks a lot Joe! AFAIK PlanAhead is quite expensive (not sure though)... Is > it an essential tool to get the job done in your opinion? > I'm sure that there are experts here who could floorplan a design with pencil and paper and get great results, I couldn't. The 30-day free trial was enough to convince me that it was a tool I wanted to keep. I wouldn't say it is essential for everyone or even every PPC system designer, but it is a great tool for understanding the timing errors you're getting and making changes to eliminate those errors. --- Joe Samson Pixel VelocityArticle: 104349
frankgerlach@gmail.com schrieb: > Wouldn't it also be possible to use the parallel port of a PC to drive > the inputs of the FPGA and read back the output signals ? (Of course, > some TTL chips might be necessary in addition to that) The PC would > also drive the clock of the FPGA in order to "slow down" the circuit. This is possible but not very usefull. A clean simulation is much easier and much more usefull. So learn it the right way from the beginning on. No need to reinvent the wheel. Regards Falk
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