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amirhossein.gholamipour@gmail.com kirjoitti: > Hi guys, > I'm trying to do post place and route simulation and generate vcd file > to estimate the power with XPower. I tried behavioral simulation and > the system was working fine. > > Thanks alot beforehand, > > Amir By the way, why do you perform post P&R simulation for power analysis? Isn't functional simulation activity output enough? Do you know if post P&R simulation really gives a benefit over functional simulation for power analysis? AnttiArticle: 105076
On 13 Jul 2006 01:49:22 -0700, antti.tyrvainen@luukku.com wrote: >amirhossein.gholamipour@gmail.com kirjoitti: > >> Hi guys, >> I'm trying to do post place and route simulation and generate vcd file >> to estimate the power with XPower. I tried behavioral simulation and >> the system was working fine. >> >> Thanks alot beforehand, >> >> Amir > >By the way, why do you perform post P&R simulation for power analysis? >Isn't functional simulation activity output enough? >Do you know if post P&R simulation really gives a benefit over >functional simulation for >power analysis? > >Antti With current FPGAs where routing delay can be more than half of the total delay, p&r results can be quite important in power. How long a route is and how many buffers it goes through certainly impacts the power consumption.Article: 105077
mk kirjoitti: > > > >By the way, why do you perform post P&R simulation for power analysis? > >Isn't functional simulation activity output enough? > >Do you know if post P&R simulation really gives a benefit over > >functional simulation for power analysis? > > > >Antti > > With current FPGAs where routing delay can be more than half of the > total delay, p&r results can be quite important in power. How long a > route is and how many buffers it goes through certainly impacts the > power consumption. Yes, but does the power tool really need post P&R simulation .vcd for that? Isn't P&R netlist enough? Can't you use functional .vcd together with post P&R netlist? AnttiArticle: 105078
Jan Hansen wrote: > Use windows. Several of the Xilinx tools dont work on unix/linux anyway, so > why bother ? Linux are shit compared to Windows when it comes to user > friendlyness, so why bother ? Linux are for communists and "NERDS". Exactly. And if you're not convinced read this article http://www.shelleytherepublican.com/2006/05/03/linux-and-windows-compared-the-facts.aspxArticle: 105079
On 13 Jul 2006 03:18:17 -0700, antti.tyrvainen@luukku.com wrote: > >mk kirjoitti: > >> > >> >By the way, why do you perform post P&R simulation for power analysis? >> >Isn't functional simulation activity output enough? >> >Do you know if post P&R simulation really gives a benefit over >> >functional simulation for power analysis? >> > >> >Antti >> >> With current FPGAs where routing delay can be more than half of the >> total delay, p&r results can be quite important in power. How long a >> route is and how many buffers it goes through certainly impacts the >> power consumption. > >Yes, but does the power tool really need post P&R simulation .vcd for >that? >Isn't P&R netlist enough? > >Can't you use functional .vcd together with post P&R netlist? > >Antti I am not sure what you mean by functional simulation here. If you mean rtl simulation, the answer is no; the nets and the gates (including replicated flops etc) have to match to get an accurate number. If you mean p&r netlist without the associated SDF back-annotation, that would be ok, you don't need timing annotated simulations. VCD gets the changes in the design so you have to simulate what ever is happening in the chip, not necessarily with timing.Article: 105080
Has anyone VHDL code for accessing the DDR SDRAM on this Spartan 3E starter kit? http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-SPAR3E-SK-US -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 105081
jhouse@btmd.com wrote: > Mikhail - > > Thanks for the suggestions, they seem to have worked. My question now > is how was I supposed to know to add these options to the MPD file? I've made several peripherals with user_logic in Verilog. I've never had any problems with the tools as you describe. User_logic.v is always placed in the .pao for me, and I've never had to edit my .mpd file. --- Joe Samson Pixel VelocityArticle: 105082
Finally we have the ethernet modules in stock that lots of you are asking for. Apologies to those of you that have been waiting but we have had a few problems getting an assembly slot. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.ukArticle: 105083
Pasacco wrote: > Thankyou all for nice comments and pointer. > > Each writer (processor), accessed its own address space, > point-to-point connection might be better. > > I need another comment and pointer. > Problem now I have is "how to connect each distributed memory to I/O". > Since the input/output data is "streamed" (or serial) in the > application I consider, I do not have idea how to "transfer" block of > input streamed data to processor-private memory and vice versa. > I 've thought of these things, but not yet there --:. Thankyou I'm not quite sure what you mean. If you have a piece of shared memory, as soon as one processor writes to an address, the other processor can read it. All you need to do is to make the reader aware that the data is ready to be read. This can be done by polling or by interrupt. The writer can write the data, then when the data block is complete, write to a location to indicate the data is ready. This location either needs to be a counter so that the reader can uniquely tell when new data has arrived, or it can be a semaphore with the reader clearing the flag once the data has been read and the buffer is again empty. The same shared memory block can support transfers in either direction. You refer to "streaming" the data to processor-private memory. This sounds more like DMA than it does shared memory. The writing processor writes the data into a private memory buffer and sets up a DMA. The DMA hardware reads the private memory and writes the data to the other processor's private memory. You still need a semaphore of some type to coordinate the transfers and each processor needs to control the address for the DMA. But now each private memory needs to have multiple ports or your DMA has to provide a crossbar to connect all the different ports. This might be much more complicated than the point to point shared memory. It should be a lot easier to just use the intermediate shared memory between each processor pairwise and you only need dual port memory.Article: 105084
Hi All, I am seeking for following information regarding Virtex-II FPGA: 1. Is it possible to know exact delay information of each type of segment (signle line, double, hex lines etc.) present in Virtex-II? 2. Is it possible to now exact delay information of Programmable Interconnect Point(PIP) present between any two segments in Virtex-II? I tried to get above information from Data Sheet provided by Xilinx but did not get it. I will be very thankfull if somebody can give me pointers to get the above information. Regards, ManojArticle: 105085
Kees Bakker wrote: > Jan Hansen wrote: > > > Use windows. Several of the Xilinx tools dont work on unix/linux anyway, so > > why bother ? Linux are shit compared to Windows when it comes to user > > friendlyness, so why bother ? Linux are for communists and "NERDS". > > Exactly. And if you're not convinced read this article > http://www.shelleytherepublican.com/2006/05/03/linux-and-windows-compared-the-facts.aspx Hilarious ;) I certainly would hope the author intended it as a joke ...Article: 105086
Your comments are shit ... you still bothered to post them ... I guess we must all be stupid then ... Jan Hansen wrote: > Use windows. Several of the Xilinx tools dont work on unix/linux anyway, so > why bother ? Linux are shit compared to Windows when it comes to user > friendlyness, so why bother ? Linux are for communists and "NERDS". > > > "Rainer Buchty" <buchty@atbode100.lrr.in.tum.de> wrote in message > news:e8vu3k$b59$1@news.lrz-muenchen.de... > > Hello everyone, > > > > I recently got one of the HW-SPAR3E-SK eval boards and am trying to > > get ISE/IMPACT under Linux to talk to it; I have ISE8.2 installed, > > the actual Windriver compiled nicely and is also loaded: > > > > windrvr6 110208 0 > > usbcore 68044 1 [windrvr6 usbserial usb-uhci ehci-hcd] > > > > Also /dev/windrvr6 exists: > > > > crw-rw-rw- 1 root root 254, 0 2006-07-11 11:15 /dev/windrvr6 > > > > However, IMPACT just doesn't see the board. Checking the syslog, I find > the > > following when plugging in the board's USB cable into the PC: > > > > Jul 11 12:18:02 kernel: usb.c: USB disconnect on device 00:1d.7-5 address > 3 > > Jul 11 12:18:04 kernel: hub.c: new USB device 00:1d.7-5, assigned address > 4 > > Jul 11 12:18:04 kernel: usb.c: USB device 4 (vend/prod 0x3fd/0xd) is not > claimed by any active driver. > > > > What am I doing wrong? > > > > Kind regards, > > RainerArticle: 105087
Frank Buss wrote: > Has anyone VHDL code for accessing the DDR SDRAM on this Spartan 3E starter > kit? I've tried the Xilinx CORE Generator with MiG 1.5 but when I try to click on "Generate" for the MT46V32M16P-75 (I can't select the part "MT46V32M16-6T F", which is soldered on my board, so I selected the slowest part I found), the log says multiple times: | Verifying proximity rules for local clock distribution... | Rule violated...trying different locations due to rule violation... and later: | Could not find the pins for all the data(2.5V) and data strobe(2.5V) . | Pin allocation ...failed. And on the button where I can click for boards for other Xlinx FPGAs, there is the text "No board files". The CORE Generator looks nice, but I would be happy with just one working CORE or VHDL code for the DDR SDRAM on the Spartan 3E starter kit. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 105088
On a sunny day (13 Jul 2006 05:22:24 -0700) it happened "Sylvain Munaut <SomeOne@SomeDomain.com>" <246tnt@gmail.com> wrote in <1152793344.639776.248500@m79g2000cwm.googlegroups.com>: > >Kees Bakker wrote: >> Jan Hansen wrote: >> >> > Use windows. Several of the Xilinx tools dont work on unix/linux anyway, so >> > why bother ? Linux are shit compared to Windows when it comes to user >> > friendlyness, so why bother ? Linux are for communists and "NERDS". >> >> Exactly. And if you're not convinced read this article >> http://www.shelleytherepublican.com/2006/05/03/linux-and-windows-compared-the-facts.aspx > >Hilarious ;) I certainly would hope the author intended it as a joke ... The author is a f*cking imbecile who thinks it is to his advantage demonstrating he is one. LOLArticle: 105089
I just tried the proceedure once again, with version 8.1 of the tools, and yes you are correct the user_logic.v was in the PAO, but again, the two options: OPTION STYLE = HDL OPTION RUN_NGCBUILD = TRUE We're not placed in the MPD file. Are these options required? jhouse@btmd.com wrote: > Mikhail - > > Thanks for the suggestions, they seem to have worked. My question now > is how was I supposed to know to add these options to the MPD file? I > created the shell of the peripheral using the EDK Create Peripheral > wizard, added a bit of Verilog code using the ISE and then re-imported > the modified peripheral using import peripheral EDK wizard. All of > that resulted in the following options being placed in the MPD file: > > ################################################################### > ## > ## Name : opb_DVIReceiver > ## Desc : Microprocessor Peripheral Description > ## : Automatically generated by PsfUtility > ## > ################################################################### > > BEGIN opb_DVIReceiver > > ## Peripheral Options > OPTION IPTYPE = PERIPHERAL > OPTION IMP_NETLIST = TRUE > OPTION HDL = MIXED > OPTION CORE_STATE = ACTIVE > OPTION IP_GROUP = MICROBLAZE:PPC:USER > > Which resulted in the error mentioned in my original post. Per your > suggestion, I manually edited the MPD file and added two of the options > you suggested (the option HDL MIXED was already there) resulting in the > following: > > OPTION IPTYPE = PERIPHERAL > OPTION IMP_NETLIST = TRUE > OPTION HDL = MIXED > OPTION CORE_STATE = ACTIVE > OPTION IP_GROUP = MICROBLAZE:PPC:USER > OPTION STYLE = HDL > OPTION RUN_NGCBUILD = TRUE > > Which, as I said, seems to be working. I really feel that Xilinx needs > to document all of the little tricks that have to be done in order to > use a Verilog based custom peripheral. > > Thanks for the help, > > Jim > > MM wrote: > > Jim, > > > > Have you looked into the MPD file for your peripheral? I am guessing, but > > the relevant options are probably as follows: > > > > OPTION HDL = MIX > > OPTION STYLE = HDL > > OPTION RUN_NGCBUILD = TRUE > > > > /Mikhail > > > > > > <jhouse@btmd.com> wrote in message > > news:1152719230.706099.6480@i42g2000cwa.googlegroups.com... > > > Hello - > > > > > > I am trying to write a custom peripheral using Verilog and version 8.1 > > > of the Xilinx tool kits (ISE and XPS). It is my understanding that > > > only the user_logic component of the peripheral can be developed in > > > Verilog, not sure if that is correct or not. Anyway, I used the XPS > > > create custom peripheral tool to create the skeleton of the peripheral. > > > I was careful to select the option to generate the user_logic stub in > > > Verilog rather than VHDL. At which point I received a dialog box > > > warning that the Verilog stub will be limited capabilities, I went > > > ahead with the Verilog stub. Then, using the ISE, I added the > > > required ports etc to the top level VHDL code and added my Verilog code > > > to the user_logic component. > > > > > > Once I confirmed all of the syntax was correct, I went back to XPS and > > > attempted to import the existing peripheral back into the project. I > > > selected the standard options. I also selectd the 'MIXED' option > > > for the question asking which HDL languages were used to implement the > > > peripheral. > > > > > > I also realized that for some reason the create custom peripherial > > > wizard did not seem to include my user_logic module in the PAO file. > > > So I manually edited the file and added the following line: > > > > > > lib opb_DVIReceiver_v1_00_a user_logic Verilog > > > > > > I was a bit surprised that I had to do this, because in the past, > > > I've created customer peripherals in VHDL and found that the > > > user_logic entry was automatically placed into the PAO file. Anyway, I > > > completed the import custom peripheral wizard and then added the IP to > > > my XPS project. I specified the addresses, and tied in the required > > > ports etc. All SEEMED well. However when I tried to generate the > > > bitstream, I received the following error: > > > > > > ERROR:NgdBuild:604 - logical block > > > 'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type > > > 'user_logic' > > > could not be resolved. A pin name misspelling can cause this, a > > > missing edif > > > or ngc file, or the misspelling of a type name. Symbol 'user_logic' > > > is not > > > supported in target 'virtex2p'. > > > > > > I have searched the net for information regarding this error message > > > and found several mentions of it, however none of which seemed to help. > > > > > > There MUST be some information somewhere that explains how to import > > > custome peripherals that make use of a user_logic component written in > > > Verilog, but I have yet to be able to find anything. I would GREATLY > > > appreciate it if someone out there could point me in the right > > > direction. > > > > > > Thanks in advance, > > > > > > Jim > > >Article: 105090
Pasacco wrote: > Each writer (processor), accessed its own address space, > point-to-point connection might be better. If the address spaces do not overlap - why do you need a multi-port memory? If they don't overlap you need n single port memories. Do you really need to write simultaneously to the memory? Isn't it impossible to block and delay a memory access if one processor writes data? Some guys say that even the need for a dual-port memory is the sign for a bad designed architecture. Ok - we know that this is not true every time but you should think about if you really need a multi-port memory. (What happens if you have to move your design from the FPGA to an ASIC and dual-port memories are too expensive?) RalfArticle: 105091
Antti schrieb: > Hi > > Xilinx XCELL (First Quarter 2006) has an articel that says that the > VHDL code > is available from Micron website > > http://www.xilinx.com/publications/xcellonline/xcell_56/xc_pdf/p062-063_56-nand.pdf http://www.micron.com/support/email/product/nand_vhdl_software_agreement the NAND ECC VHDL code is available from the above link Antti is talking tohimselg againArticle: 105092
jhouse@btmd.com wrote: > I just tried the proceedure once again, with version 8.1 of the tools, > and yes you are correct the user_logic.v was in the PAO, but again, the > two options: > > OPTION STYLE = HDL > OPTION RUN_NGCBUILD = TRUE > > We're not placed in the MPD file. Are these options required? They're not in any of my .MPD files. --- Joe Samson Pixel VelocityArticle: 105093
Hi, Does anyone have experience using Universal Scan to program the flash on Xilinx's ML403? Universal Scan should use the JTAG port on the FPGA (Virtex4) to program the flash. I'm having difficulties to get it to work. Any suggestions? ThanksArticle: 105094
"John Adair" <g1@enterpoint.co.uk> wrote: >I think a flat board finish is good thing and one that does not have >any nasty oxidising habits. We have done a reasonable amount of testing >on some of Broaddown2 boards that have been around our lab for about 2 >years. Those particular boards have a siliver finish and not the hard >gold finish that would have been optional and whilst there is an >obvious level of aging on the finish on the ones we have tested there >don't appear to be any problems in any connections. > >What I would not do with a GFZ connector is use them in harsh >environments. That said we don't expect our development boards to be >subject to such use although ocasionally we do hear reports of boards >ending up in some very strange places that we didn't expect. In another era I repaired boards from a main-frame computer. Some boards had modules that used a similar construction like the GFZ connector. Early modules used some sort of silicone with carbon traces, later on these where replace by silicon with gold wires. Still, both versions needed cleaning every now and then. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 105095
jhouse@btmd.com wrote: > Hello - > > I am trying to write a custom peripheral using Verilog and version 8.1 > of the Xilinx tool kits (ISE and XPS). It is my understanding that > only the user_logic component of the peripheral can be developed in > Verilog, not sure if that is correct or not. Anyway, I used the XPS > create custom peripheral tool to create the skeleton of the peripheral. > I was careful to select the option to generate the user_logic stub in > Verilog rather than VHDL. At which point I received a dialog box > warning that the Verilog stub will be limited capabilities, I went > ahead with the Verilog stub. Then, using the ISE, I added the > required ports etc to the top level VHDL code and added my Verilog code > to the user_logic component. > > Once I confirmed all of the syntax was correct, I went back to XPS and > attempted to import the existing peripheral back into the project. I > selected the standard options. I also selectd the 'MIXED' option > for the question asking which HDL languages were used to implement the > peripheral. > > I also realized that for some reason the create custom peripherial > wizard did not seem to include my user_logic module in the PAO file. > So I manually edited the file and added the following line: > > lib opb_DVIReceiver_v1_00_a user_logic Verilog > > I was a bit surprised that I had to do this, because in the past, > I've created customer peripherals in VHDL and found that the > user_logic entry was automatically placed into the PAO file. Anyway, I > completed the import custom peripheral wizard and then added the IP to > my XPS project. I specified the addresses, and tied in the required > ports etc. All SEEMED well. However when I tried to generate the > bitstream, I received the following error: > > ERROR:NgdBuild:604 - logical block > 'opb_dvireceiver_0/opb_dvireceiver_0/USER_LOGIC_I' with type > 'user_logic' > could not be resolved. A pin name misspelling can cause this, a > missing edif > or ngc file, or the misspelling of a type name. Symbol 'user_logic' > is not > supported in target 'virtex2p'. > > I have searched the net for information regarding this error message > and found several mentions of it, however none of which seemed to help. > > There MUST be some information somewhere that explains how to import > custome peripherals that make use of a user_logic component written in > Verilog, but I have yet to be able to find anything. I would GREATLY > appreciate it if someone out there could point me in the right > direction. > > Thanks in advance, > > Jim > Ha! I went through the same thing when I started with my own peripherals. There is alot of practical stuff not documented. Here is my general flow: Use wizard to create templates Write Verilog code, simulate, etc. MANUALLY edit .mpd and .poa files to add any new verilog files for my source run the import wizard, telling it to use the mpd or poa file that I edited. import the peripheral. I don't like the limited availability (and the big warning message abouyt to not use verilog) verilog examples. It seems that they might dump verilog support.... -EliArticle: 105096
> How many I/O pins does that take? I'm not sure that question makes a whole lot of sense. On the SGI box I was getting 128bits per clock cycle at 200MHz on a 2v6000. The number of pins is irrelevant. The sort algorithm was only running at 100MHz. And it doesn't need to run that fast because it requires at least a few clock cycles to build up enough data to make the sort worth it.Article: 105097
George.Y.Ma@gmail.com schrieb: > Hi, > > Does anyone have experience using Universal Scan to program the flash > on Xilinx's ML403? > Universal Scan should use the JTAG port on the FPGA (Virtex4) to > program the flash. I'm having difficulties to get it to work. Any > suggestions? > > Thanks I tried universalscan with S3e sample pack board. never got it working. writing a custom application that does the nor flash programming (either over boundary scan or using BSCAN primitive) was way easier. AnttiArticle: 105098
> On the SGI box I > was getting 128bits per clock cycle at 200MHz on a 2v6000. Actually, I was just thinking, on my Starbridge HC box, I can get 128bits x 4 memory channels x 66MHz. 512@66MHz = 34Gb/s. 128@200MHz = 25Gb/s. Can anybody outrun 34Gb/s input to their FPGA these days? I know that using all the rocket i/o / LVDS / whatever that current chips should support input rates significantly faster than that -- but who actually has a board that implements it? What rate is SRC getting with their direct FSB connection? I still dream about a board using an HTX slot, or even a cheap board with some large Spartans and 4 PCIe in and 4PCIe out (10Gb/s each direction for a few hundred $). These sort algorithms are all worthless if you cannot get your data in and out of the chip fast enough.Article: 105099
Has anyone worked with national instruments ADC08D1500 development board?? This board has a Virtex-4 FPGA that does some processing. For ref: www.xilinx.com/publications/magazines/io_02/xc_pdf/p009-013_2io-national.pdf (this is the xilinx publication, that national site has a manual--> not that helpful) I am trying to incorporate some blocks in it and check the outputs using the future expansion I/Os. For starters, I decided to include a DCM that divides the clock frequency(100 MHz) and provide it on the future board expansion pins. Surprisingly, I am not even able to observe the clock waveform or the dividied clk waveform generated by the local oscillator coherently. Can someone suggest any pointers. Thanks, Vivek
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