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Came across some USB FPGA information at the following sites. http://www.atrandomresearch.com/usbp http://pages.cpsc.ucalgary.ca/~walpole/525/FRIESS%20and%20MCNEIL/index.html http://norum.homeunix.net/~carl/usbp/ The Cypress FX2 chips seems to be a popular USB controller used. Also seen the FTDI in action, easier to use but not as much flexibility. Digilent and Opal Kelly boards have USB interfaces. But you can't mess around with the code. Also the GnuRadio folks did a good job with a set of open source code and developed a USB/FPGA board to support the software radio. It also uses the FX2 but has an Altera device. Vhdl.eu wrote: > Hi Dave, > > Maybe you can look at FTDICHIP website they have boards with USB connections > to FPGA's > http://www.ftdichip.com/Products/EvaluationKits/FPGA.htm > > > Kind Regards, > http://www.vhdl.eu > > > > "Dave Farrance" <DaveFarrance@OMiTTHiSyahooANDTHiS.co.uk> wrote in message > news:c8ci82t7ns08cbn70qq5ipe5mtg8i4vua6@4ax.com... > > "John Adair" wrote: > > > >>Have a look at this module > >>http://www.enterpoint.co.uk/moelbryn/modules/usb_ps2.html in conjunction > >>with our Raggedstone1 product. Basically the module is a voltage > >>limiter(bus > >>switch) on the USB lines leaving the logic to be implemented in the FPGA. > > > > Thanks to everybody that helped me in this thread. I've decided to buy > > the above product. > > > > -- > > Dave FarranceArticle: 105151
On Fri, 14 Jul 2006 15:41:15 +0000, John_H wrote:
> Resurrecting an old thread while so many people are off to vacation?
>
> This forum would have significantly less traffic and the general quality of
> information and help exchanged on this board would suffer if those two
> Xilinx employees were told to stop posting here.
>
> Austin can be as annoying at times when he's gung-ho about communicating the
> things *he* believes in; they may seem like total marketing rubbage but it
> seems to me he just has strong feelings on the matters. His interaction can
> be caustic at times as well. But taking the good with the bad his presence
> here has been invaluable, in my humble opinion.
>
> Why you have issues with Peter Alfke is beyong me. Not only is he
> professional, resourceful, and extremely helpful but he presents himself
> here calmly and conservatively even in the face of dire flames and worse.
> If more people could present his professionalism and the strong desire to
> help that both these men contribute to this forum, I would be a happier
> engineer.
>
> I'm glad that I only have one person in my kill file considering how long
> I've been interacting with the newsgroup. Feel free to add Ausitn, Peter,
> even myself to your own kill file.
>
> Many thanks to all the others who help make this a constructive place to
> advance FPGA design.
>
> - John Handwork
Exactly!
~Dave~
Article: 105152Have a look at BYO partitioning software (http://www.byo-solutions.com/) you can download a free version, Hans www.ht-lab.com <shalza.mittal@gmail.com> wrote in message news:1152870965.385818.46790@s13g2000cwa.googlegroups.com... > Hi, > I am interested to learn more about techniques for design partition > across multiple FPGAs. > Can someone provide me with useful pointers about it > > Thanks a lot > Shalza >Article: 105153
To give you an idea how important a reset is, google for the WIRE mission, this 70Million dollar satellite was lost due to an incorrectly designed reset circuit...... Hans. www.ht-lab.com "Thomas Reinemann" <thomas.reinemann@aucotronics.de> wrote in message news:e981ph$ur5$1@news.boerde.de... > Hello, > > usually a reset signal is applied to put the FFs of an FPGA into a known > state. Just some days ago I had a discussion. Someone's point of view > is, that a reset is not necessary, since the FF's output will be always > zero, after applying the voltage. Does this happen in FPGAs really, > especially in a Spartan3? > > Bye TomArticle: 105154
Hans wrote:
> To give you an idea how important a reset is, google for the WIRE mission,
> this 70Million dollar satellite was lost due to an incorrectly designed
> reset circuit......
A poor reset circuit crashed several ferries
into the docks in Puget Sound.
-- Mike Treseler
______________________________________________
http://catless.ncl.ac.uk/Risks/9.69.html#subj2
"As part of the state's Department of Transportation, Washington State
Ferries in Seattle operates 24 vessels, encompassing a variety of
control systems. No others have had the problems of the six boats in
the Issaquah class, which are unique in having variable-pitch
propellors, one at each end of the boat. When the captain sets the
control handle positions for transit or movement near the dock, the
control system must set the appropriate propellor speed, pitch, and
clutch engagement. Variable pitch makes the craft extremely
maneuverable, able to move sideways and turn on the spot.
Many of the problems could be traced to the vendor, Propulsion Systems
Inc. (PSI), which went bankrupt in 1981 and was then bought by the
ferry builder, the now-defunct Marine Power and Equipment Co. "The
problem is not so much with digital controls," said Davis, "as with
horribly shoddy control system design."
Article: 105155Hi all, I have serious problems with V4FX12MM phy interrupt line. There is no indication in MiniModule User Guide that interrupt is connected to FPGA, but in schematics it is clearly seen that is connected to LOC = K5. I connected interrupt controller to this IO pin but no sign of activity (and I did set proper PCS register). Any help would do. GuruArticle: 105156
> I am interested to learn more about techniques for design partition > across multiple FPGAs. Traditionally people have tried to come up with auto-partitioners that are somehow smart enough to split up connections between chips. The scope of that problem is too large. I propose you do it this way: First, you have to define a dataset as partitionable. You cannot break apart objects unless they are connected by this specific dataset that is allowed to be broken. You'll need some communication core that goes with that dataset on both ends of the transfer. Then your partition software will automatically insert those communication cores in after it decides to separate a certain line with the breakable dataset. Um. I'm not sure I'm describing this very well. Does that make sense? So for example, suppose you have a dataset that is made of some data bits, an enable bit, a clock, and a busy signal going the opposite direction. That dataset is breakable because you can send the data, clock, and enable to a fifo on the far chip; that fifo can send back an almost busy signal to stop data from being sent. A simpler case would be a control line that is stable ages before it is needed; your separation objects for those will just be buffers and pads.Article: 105157
Hi Brannon, Thank you for sharing your information with us. You are experienced expert in this regard. I appreciate your work and I have never seen a project with such huge resource demand. I was said a v2-6000 costs nearly $8K. By the way, I cannot find 'bitonic' name in Microsoft Encarta computer dictionary. What does it mean? Weng Brannon wrote: > > Can you release your design running frequency for 64*64 bitonic sorting > > and what type of Xilinx chip or larger is to be used? > > So here are my results. First, I've never ran 64x64. I didn't mean to > imply that I could -- just that it was possible. I can run at 100MHz on > a 2v6000 with 16x64bit. It should run twice that fast on a V4. I > compiled a 32x64bit and got this result: 50837 LUTs and 72720 FFs. > That's larger than my chip. I compiled the 64x64bit version and got > 140461 LUTs and 199888 FFs. That's pretty darn big. It includes > registers for parallelizing the input which is coming in at 64bits per > clock for those examples. I'm sure my implementation is not the most > efficient possible, but I still think you'll need a pretty large chip > to do any kind of serious parallel sorting.Article: 105158
I'm having a problem with data logging. I need to grab (and analyze) about 60 bits of data at about 120 MHz. I'm running out of depth in my logic analyzer, which has 64M, or 128M if I use the PacqMem code that Tek provides. I'd really like to grab to a depth of 256M or more. Does anybody make an FPGA board that would allow me to do this? I would need a couple of sockets for DDR SDRAM, a USB or Ethernet interface (to get the data to the PC) and a bunch of IO connectors. It would be perfect if it had four 50-pin shrouded headers with pins-out appropriate for logic analyzer test probes. I know it's a long shot. Thanks PeteArticle: 105159
Hi Jonathan, Thank you for your thorough understanding the Batcher algorithm and its program in C. WengArticle: 105160
Weng Tianxiang wrote: > Hi Brannon, > Thank you for sharing your information with us. You are experienced > expert in this regard. I appreciate your work and I have never seen a > project with such huge resource demand. I was said a v2-6000 costs > nearly $8K. 2v-6000-4 is $2k. Don't pay any more than that for one. > By the way, I cannot find 'bitonic' name in Microsoft Encarta computer > dictionary. What does it mean? I have no idea what 'tonic' is refering to. I got all my information including the exact hardware implementation from this page: http://www.inf.fh-flensburg.de/lang/algorithmen/sortieren/bitonic/bitonicen.htmArticle: 105161
Pete We may get close with our Broaddown2 product. The only "but" is we need to do some long outstanding work on the DDR2 socket to prove it works for memory. There are some pinning issues with some DDR cores but we do have a core we designed and used before that we think will work. Just needs some manpower to tidy up and try it out. The probe head connections can be done as simple add-on modules. We have sufficient I/O to make it work. If you don't mind doing most of the work it is a project I would not mind supporting. Contact me offline if you wish to persue it. Any of the public emails on our website can be used to contact me. John Adair Enterpoint Ltd. Pete Fraser wrote: > I'm having a problem with data logging. > I need to grab (and analyze) about 60 bits of data at about 120 MHz. > I'm running out of depth in my logic analyzer, which has 64M, > or 128M if I use the PacqMem code that Tek provides. > I'd really like to grab to a depth of 256M or more. > > Does anybody make an FPGA board that would allow me > to do this? I would need a couple of sockets for DDR SDRAM, > a USB or Ethernet interface (to get the data to the PC) and > a bunch of IO connectors. It would be perfect if it had > four 50-pin shrouded headers with pins-out appropriate > for logic analyzer test probes. I know it's a long shot. > > Thanks > > PeteArticle: 105162
Hi - On Fri, 14 Jul 2006 14:13:33 +0200, Thomas Reinemann <thomas.reinemann@aucotronics.de> wrote: >Hello, > >usually a reset signal is applied to put the FFs of an FPGA into a known >state. Just some days ago I had a discussion. Someone's point of view >is, that a reset is not necessary, since the FF's output will be always >zero, after applying the voltage. Does this happen in FPGAs really, >especially in a Spartan3? > >Bye Tom Whether or not you need a reset depends on your design and the application. If you have nothing more than, say, a data pipeline that will eventually flush itself out, and your application is insensitive to the garbage that the pipe emits initially, you may not need a reset at all. But if your circuit has control, perhaps in the form of finite state machines, relying on the FPGA to correctly initialize state can be dangerous. FPGAs generally use a very slow global net to initialize device state--so slow, in fact, that there's no way to guarantee when the deassertion of the initialization signal arrives at each flip-flop relative to the clock's active edge. If it arrives at just the right time (or just the wrong time, depending on your perspective), some FSM flip-flops may be inhibited from transitioning while others are not, and away you go into a bogus state. You can design FSMs that always eventually transition to a valid state, but sometimes it's easier and better to guarantee that you never enter a bogus state in the first place. The following article describes how FSMs can be corrupted by inputs that are asynchronous to the FSM clock. http://www.cambriandesign.com/2006/02/synchronizing-fsm-inputs.html Once you realize that the FPGA initialization signal is asynchronous, you'll understand the problem. Bob Perlman Cambrian Design Works http://www.cambriandesign.comArticle: 105163
Folx, At work, we encode tons of video and some/most have fairly short TTM requirements. It is all Web-destined and sooner we get it out, the better it is for us and consumers alike. So we use SW that supports variety of video format and encode video in Flash/WM and other formats. Now the problem statement: it is dead slow. We use latest-greatest in computer tech (latest AMD and Intel CPUs), but still even @ lower Web rez, the encoded happen at slower than real-time. By now, the video compression algorythms are prolly well perfected and it is unreasonable to expect any breaktrhoughs there. The situation will improve somewhat as Intel's Woodcrests/Conroe become available, but still. So about the only way one can accelerate the process is by HW acceleration. As suprising as it is, there doesn't appear to be any products out there ! While most cell phones these days have HW-accelerated video DEcodes, there's nothing for encoding. I know some folx here have pretty good idea as to what might be possible with FPGAs, as far FFT/DCTs are concerned. Do you think a board can designed (price does NOT matter) that can rediacally improve the situation ? the market is ripe for something like that. Of course, one would need to make sure there is a clear API and major vendors enable their codes to work with it. Something like PCI-X or PCIEx4, with (a few of ?) Virtex4 on it, may be 512MB of fastest SRAM for buffering. Input would be say DV25 or MPEG2, output: MPEG4, Flash 8, WM 9/10, in 500x300 rez or thereabouts. So ... put it together and laugh all the way to the bank :) Market is 10s of thou, easily. You can ask 15-20K for something like that, assuming it radically cuts encoding time. Ideas ?Article: 105164
Rashid wrote: > So about the only way one can accelerate the process is by HW > acceleration. As suprising > as it is, there doesn't appear to be any products out there ! While > most cell phones these days have HW-accelerated video DEcodes, there's > nothing for encoding. Searching at Google: http://www.google.com/search?hl=de&q=hardware+video+encoder shows some graphics cards, which has hardware encoders. And of course, if price doesn't matter, for professional television broadcasting there are some realtime hardware encoders for MPEG4 etc. available. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 105165
Thnx for google :) . Of course I looked, before, long and hard :), could not find the stuff I am looking for. I guess I should qualify request - it is more of transcoding solution. Dealing with preexisting DV/MPEG files that need to be flipped into dift format(s). So there, one'd face a double problem: decoding pre-existing, most-of-the-time compressed format and re-encoding to a different one. With DSP performances of today's FPGAs in multiple GMACs and parallel possibilities (up to 512 DSP slices in top V4s) I figured it might be a good fit for this application. Also, FPGAs being programmable in matter of millisecs these days, one can prolly tailor processing for particulars of a format @ hand ... Frank Buss wrote: > Rashid wrote: > > > So about the only way one can accelerate the process is by HW > > acceleration. As suprising > > as it is, there doesn't appear to be any products out there ! While > > most cell phones these days have HW-accelerated video DEcodes, there's > > nothing for encoding. > > Searching at Google: > > http://www.google.com/search?hl=de&q=hardware+video+encoder >Article: 105166
Rashid schrieb: > Folx, > [] > Something like PCI-X or PCIEx4, with (a few of ?) Virtex4 on it, may be > 512MB of fastest > SRAM for buffering. > > Input would be say DV25 or MPEG2, output: MPEG4, Flash 8, WM 9/10, in > 500x300 rez or thereabouts. > > So ... put it together and laugh all the way to the bank :) Market is > 10s of thou, easily. You can ask 15-20K for something like that, > assuming it radically cuts encoding time. > > Ideas ? 15KUSD is only sufficient (maybe) to make 1 or 2 rounds of high-end proto PCBs with LARGE Xilinx FPGA's on it. And making the PCB is only a fraction of the actual costs. The minimum NRE is more likely 250K USD for your project. Add some profit too and you end up paying 0.5M USD or more. To make it attractive you should be willing to pay 1M USD or more. I'ts defenetly not something 2 students glue together as last year project. You are not going to find anyone who 'puts it together' and takes your 25KUSD with a smile. hm after reading your post, the 15-20K was meant as sale price of one ready made unit? Thats more realistic if there is guaranteed sale of 50pcs at that price. But someone still has to pay up front the NRE costs which are not small. AnttiArticle: 105167
On a sunny day (16 Jul 2006 09:06:42 -0700) it happened "Antti" <Antti.Lukats@xilant.com> wrote in <1153066002.164481.311270@h48g2000cwc.googlegroups.com>: >Rashid schrieb: If you want to use FPGA, have a look here: http://www.altera.com/technology/dsp/applications/video_imaging/dsp-vid_index.html There is H264 main profile encoder IP mentioned too.Article: 105168
Generally anything you can do in software can be done in a hardware FPGA design. Usually much faster in the FPGA and other techniques like parallel processing can be used to enhance speed further. Usually the main deciding factor is cost, if performance is the issue then usually the FPGA wins. We have done major parts of a video conferencing system this way in the past and other get FPGA co-processing applications are common too. As for a board to start with have a look at our Broaddown4 product. John Adair Enterpoint Ltd. Rashid wrote: > Folx, > > At work, we encode tons of video and some/most have fairly short TTM > requirements. > It is all Web-destined and sooner we get it out, the better it is for > us and consumers > alike. > > So we use SW that supports variety of video format and encode video in > Flash/WM and > other formats. > > Now the problem statement: it is dead slow. We use latest-greatest in > computer tech > (latest AMD and Intel CPUs), but still even @ lower Web rez, the > encoded happen at > slower than real-time. By now, the video compression algorythms are > prolly well perfected > and it is unreasonable to expect any breaktrhoughs there. The situation > will improve somewhat as Intel's Woodcrests/Conroe become available, > but still. > > So about the only way one can accelerate the process is by HW > acceleration. As suprising > as it is, there doesn't appear to be any products out there ! While > most cell phones these days have HW-accelerated video DEcodes, there's > nothing for encoding. > > I know some folx here have pretty good idea as to what might be > possible with FPGAs, > as far FFT/DCTs are concerned. Do you think a board can designed (price > does NOT matter) > that can rediacally improve the situation ? > > the market is ripe for something like that. Of course, one would need > to make sure there > is a clear API and major vendors enable their codes to work with it. > > Something like PCI-X or PCIEx4, with (a few of ?) Virtex4 on it, may be > 512MB of fastest > SRAM for buffering. > > Input would be say DV25 or MPEG2, output: MPEG4, Flash 8, WM 9/10, in > 500x300 rez or thereabouts. > > So ... put it together and laugh all the way to the bank :) Market is > 10s of thou, easily. You can ask 15-20K for something like that, > assuming it radically cuts encoding time. > > Ideas ?Article: 105169
Hi http://www.xilant.com/downloads/aceplayer_1_0.zip small utility to play back Xilinx ACE files can be used to test the ACE files without the need to copy them to the CF card - Cable III is supported. please let me know if the tool has issues - it does seem to work both with original files generated by impact as also with ACE compressed files. AnttiArticle: 105170
"Rashid" <rashid.karimov@gmail.com> wrote: >Folx, > >At work, we encode tons of video and some/most have fairly short TTM >requirements. >It is all Web-destined and sooner we get it out, the better it is for >us and consumers >alike. > >So we use SW that supports variety of video format and encode video in >Flash/WM and >other formats. > >So about the only way one can accelerate the process is by HW >acceleration. As suprising >as it is, there doesn't appear to be any products out there ! While >most cell phones these days have HW-accelerated video DEcodes, there's >nothing for encoding. There is plenty of stuff for encoding video in hardware (like mpeg4 compression). -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 105171
Antti wrote: > Rashid schrieb: > > > Folx, > > > [] > > Something like PCI-X or PCIEx4, with (a few of ?) Virtex4 on it, may be > > 512MB of fastest > > SRAM for buffering. > > > > Input would be say DV25 or MPEG2, output: MPEG4, Flash 8, WM 9/10, in > > 500x300 rez or thereabouts. > > > > So ... put it together and laugh all the way to the bank :) Market is > > 10s of thou, easily. You can ask 15-20K for something like that, > > assuming it radically cuts encoding time. > > > > Ideas ? > > 15KUSD is only sufficient (maybe) to make 1 or 2 rounds of high-end > proto PCBs with LARGE Xilinx FPGA's on it. And making the PCB is only a > fraction of the actual costs. > > The minimum NRE is more likely 250K USD for your project. > Add some profit too and you end up paying 0.5M USD or more. > To make it attractive you should be willing to pay 1M USD or more. > > I'ts defenetly not something 2 students glue together as last year > project. You are not going to find anyone who 'puts it together' and > takes your 25KUSD with a smile. > > hm after reading your post, the 15-20K was meant as sale price of one > ready made unit? Thats more realistic if there is guaranteed sale of > 50pcs at that price. But someone still has to pay up front the NRE > costs which are not small. > > Antti Antii Calculations are correct. But you can find a ready solution from matrox video editing cards. http://www.matrox.com/video/home.cfm Most of them could be the solution for your needs. With Matrox RT.X100 Xtreme Pro (among other functions ) with Matrox MediaExport provides hardware-accelerated simultaneous batch encoding of Windows Media/RealMedia streaming formats and MPEG-1/MPEG-2 multimedia formats with multiple resolutions, bit rates, and frame rates. RT.X10 and most of the other cards provide the above functionality. FPGA projects can provide lightining fast solutions for specific tasks but are VERY expensive to develop and need specialist enginners (hopefully among us in this newsgroup) to develop the products. Regards, Viron. Viron.Article: 105172
Hi everyone,
I am trying to 'or' a 2K vector in Virtex4. Looking at the problem as
a first approximation, it would need 6 levels of 4 input lookup
tables. So far I have tried XST but it seems to be using the initial
512 LUT4s and then 56 levels of MUXCY. Any ideas why it's using the
MUXCYs? They seem to be quite fast at 45ns each but number of levels
is quite high. I'm curious what the timing would look like if I could
force it to use only LUT4s but I really don't want to code it by hand
and I am too lazy to write a perl script to do it either. Any
suggestions ?
Thanks.
PS Here is what I am using as a test module. I am trying to map it to
a virtex4-10.
module orlt(clk, in, out);
input clk;
input [2047:0] in;
output out;
reg [2047:0] inr;
reg out;
wire outw;
orl u0(inr, outw);
always @(posedge clk)
begin
out <= outw;
inr <= in;
end
endmodule
module orl(in, out);
input [2047:0] in;
output out;
wire out = |in[2047:0];
endmodule
Article: 105173We are looking for a consultant for a project that involves an FPGA to implement our data manipulation algorithm to scale up to 5000 simultaneous sessions and interface with our Opteron system via either PCI or Hypertransport. Please contact me if interested as soon as possible. hrocarina@gmail.com Regards, HRArticle: 105174
mk wrote: > Hi everyone, > I am trying to 'or' a 2K vector in Virtex4. Looking at the problem as > a first approximation, it would need 6 levels of 4 input lookup > tables. So far I have tried XST but it seems to be using the initial > 512 LUT4s and then 56 levels of MUXCY. Any ideas why it's using the > MUXCYs? They seem to be quite fast at 45ns each but number of levels > is quite high. I'm curious what the timing would look like if I could > force it to use only LUT4s but I really don't want to code it by hand > and I am too lazy to write a perl script to do it either. Any > suggestions ? I was thinking, what is hard about this??? Then I looked at your code and realized that you are not using VHDL. In VHDL you can use a GENERATE statement to lay out the functional elements exactly how you want them with looping to define it all without the tedium. Isn't there a similar construct in Verilog?
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