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> The obvious is to check your wiring. "Unknown device" may mean that > the TMS or TDI signal is not making it to the FPGA. Can you chain > multiple devices together? If so do you still see the 3S1500? Do > the 3S200's still show up as "unknown"? This would seem to point > to the TMS signal. Are you using the latest version of iMPACT? > Yes we chained the devices together and the larger FPGA was not recognized.The 3S200's still show up as "Unknown". I am using ISE 7.1i. Exactly what does the TMS signal mean? The larger FPGA device although recognized, doesnt produce result when configured. The outputs were floating. I believe the device was not even configured. Any pointers on what all to test now? Thanks SubhasriArticle: 105501
Hi, Our latest prototype board doesnt produce any output and even a simple module to output '1's and '0's on some pins did not work. Impact configured the program successfully though. The impact log file seemed to have a different report now than when it was tested on 2 other boards. On the first two boards (where the results were ok) the log file is // *** BATCH CMD : // *** BATCH CMD : setCable -port lpt1 Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 6.2.2.2. LPT base address = 0378h. ECP base address = 0778h. Cable connection established. // *** BATCH CMD : setMode -bs Finish loading cdf file c:\xilinx\bin\test\const800patternramp/Const800PatternRamp.ipf. // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -ss // *** BATCH CMD : setMode -sm // *** BATCH CMD : setMode -bsfile // *** BATCH CMD : setMode -dtconfig // *** BATCH CMD : setMode -cf GUI --- Read System ACE CF Mode... // *** BATCH CMD : setMode -mpm GUI --- Read System ACE MPM Mode... // *** BATCH CMD : setMode -pff GUI --- Read PROM Formatter Mode... // *** BATCH CMD : setMode -bs // *** BATCH CMD : Program -p 1 PROGRESS_START - Starting Operation. Validating chain... Boundary-scan chain validated successfully. '1':Programming device... '1': Reading status register contents... CRC error : 0 RESERVED : 0 DCM locked : 1 DCI Matched : 1 legacy input error : 0 status of GTS_CFG_B : 1 status of GWE : 1 status of GHIGH : 1 value or MODE pin M0 : 1 value or MODE pin M1 : 0 value or MODE pin M2 : 1 value of CFG_RDY (INIT_B) : 1 DONEIN input from DONE pin : 1 ID_ERROR : 0 RESERVED : 0 RESERVED : 0 INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 0111 1011 1000 0000 0000 0000 0000 done. INFO:iMPACT:579 - '1': Completed downloading bit file to device. INFO:iMPACT:580 - '1':Checking done pin ....done. '1': Programmed successfully. PROGRESS_END - End Operation. Elapsed time = 26 sec. ***** Closing iMPACT program. ***** On the new board where there was no output, the log file is ---------------------------------------------------------------------- // *** BATCH CMD : // *** BATCH CMD : setCable -port lpt1 Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 6.2.2.2. LPT base address = 0378h. ECP base address = 0778h. Cable connection established. // *** BATCH CMD : setMode -bs Finish loading cdf file c:\xilinx\bin\constout640x480/ConstOut640x480.ipf. // *** BATCH CMD : setMode -bs // *** BATCH CMD : setMode -ss // *** BATCH CMD : setMode -sm // *** BATCH CMD : setMode -bsfile // *** BATCH CMD : setMode -dtconfig // *** BATCH CMD : setMode -cf GUI --- Read System ACE CF Mode... // *** BATCH CMD : setMode -mpm GUI --- Read System ACE MPM Mode... // *** BATCH CMD : setMode -pff GUI --- Read PROM Formatter Mode... // *** BATCH CMD : setMode -bs // *** BATCH CMD : Program -p 1 PROGRESS_START - Starting Operation. Validating chain... Boundary-scan chain validated successfully. '1':Programming device... '1': Reading status register contents... CRC error : 0 RESERVED : 0 DCM locked : 1 DCI Matched : 1 legacy input error : 0 status of GTS_CFG_B : 0 status of GWE : 0 status of GHIGH : 1 value or MODE pin M0 : 1 value or MODE pin M1 : 0 value or MODE pin M2 : 1 value of CFG_RDY (INIT_B) : 1 DONEIN input from DONE pin : 0 ID_ERROR : 0 RESERVED : 0 RESERVED : 0 INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0011 0001 1011 0000 0000 0000 0000 0000 done. INFO:iMPACT:579 - '1': Completed downloading bit file to device. INFO:iMPACT:580 - '1':Checking done pin ....done. '1': Programmed successfully. PROGRESS_END - End Operation. Elapsed time = 39 sec. ***** Closing iMPACT program. ***** The status of GTS_CFG_B and GWE are different. Is this of significance? Thanks Subhasri.KArticle: 105502
Sean Durkin wrote: > manu wrote: > > Hello, > > for the moment, I use SVN to manage different versions of te VHDL code > > of my projects. > > I'd like to manage my xilinx projects based on my VHDL code too. > > Until now, I just put the <project>.ise and <project>.ucf files under > > version control and it was enough to be rebuild the whole project. > > Now, I've added an embedded processor to my ISE design and I'm a bit > > confused because there a huge set of automatically generated files. I'd > > like to keep under version control just the minimum set of files > > required to rebuild the whole project. I think there's at least the > > <project_up>.xmp, <project_up>.mhs and <project_up>.mss files, but is it > > enough ? > Theoretically, those should be enough, plus your pcores-directory (in > case you have created your own peripherals) and the directory where you > store your application code (the C-code for your program). > > Putting anything else in the repository will not work smoothly, because > EDK deletes whole directory trees when you clean up the project to have > it synthesize again. > > The implementation directory for example... usually I would like to > check in the created netlist files, but once you re-run the EDK flow, > EDK deletes the directory including the hidden CVS directories, so your > usual CVS client gets really confused... And once again, Xilinx shows their complete antipathy towards any sort of version control .... -aArticle: 105503
Kyle, > Is the UCF file that I'm using generated by EDK, or did someone from > memec hand sculpt this? The UCF file has been written manually. The pin assignments have to match the board's schematics. > Maybe I have to import this into an ISE project to get the big picture? Not really. ISE is required if your embedded design is going to be a part of a bigger design. Then it makes sense to have top level design in ISE. Otherwise it is easier to stay in EDK. EDK will call required ISE routines in background. > And I thought the gpio output > was 32 bit, so why in the UCF file is there only 10 pins assigned to > the gpio output port(s)? That's because they didn't care to declare it as a 10 bit port. Since there are only 10 pins assigned physically in the UCF file the tools trim the rest during build time. Take a look at the MHS file. In the top it has external ports section, which lists all of the external IOs in your design. All of these need to have LOC constraints in the UCF file to be routed correctly for your board. Watch for the names to match. Also, looking at the MHS file you can figure out how these IOs connected to various blocks in your design, e.g. how the GPIO pins connected to the GPIO module. Watch the bit order, sometimes it can be confusing. Hope this helps, /MikhailArticle: 105504
Also, make a habit to look at your project_name.par file when the tools have run their course. See that all your constraints have been met, in particular that the number of IOs equals the number of LOC'ed IOs, etc.. /MikhailArticle: 105505
Brian McFarland wrote: > It's an I/O interface that will be constantly receiving and > transmitting something at 270 Mbps both directions using 8B/10B > encoding. Which means potentially, we could want the card to transmit > and receive 27 MB/s. However, in this particular application, rate of > the real data will be closer to just 2MB/s. If there's a latency due > to buffering & block tranfers, it's probably not a concern as long I > can have large enough FIFOs on the FPGA that they never become empty > while I'm filling the PC side buffer. The whole reason for this > interface is to modify the input data stream and send it back out and > the delay caused by CPU time is probably going to be considerably more > -- although i'm not sure how much processing it will take because our > customers are writing the software that does it and I have no direct > way to contanct their developers. It's a bit difficult to give an accurate answer with the above-mentioned "requirements specification". ;) It's going to depend on how much latency you can tolerate. If you were able to wait for a few KB to be accumulated on each side before transferring, you'd have absolutely no problem achieving your 27MB/s in each direction. Of course, that introduces large delays in your stream. OTOH if the application isn't tolerant to large latencies and, for example, you needed to do single 32-bit PIO transactions, then we've seen fetches from *memory* on the back-end of the PCI core take up to 20 PCI clocks to complete on the host (shave a few clocks off if your data is in a register or read-ahead FIFO, for example). That brings your throughput down to around 5MB/s - total! There's a lot of latency introduced when pushing data through the PCI core FIFOs in each direction. Obviously if you can stream large chunks that latency becomes insignificant w.r.t. throughput. PCI retries on posted reads also add to the equation. Nutshell - you need to work out *exactly* what latencies you can tolerate. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 105506
Brian McFarland wrote: > -- although i'm not sure how much processing it will take because our > customers are writing the software that does it and I have no direct > way to contanct their developers. In that case my response would be that I don't have sufficient detail in the requirements to propose a solution. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 105507
I am new to FPGA's and am designing my first circuit in Xilinx ISE. I have two 'building block' symbols on my schematic. The first has a 16-bit wide output, the second has a 16-bit wide input. Is there an easy way to connect the two buses in one fell swoop, or do I have to add 16 wires to my schematic?Article: 105508
Hi Nevo, just add a wire between the bus output and input. It automaticly becomes a bus of the correct width. When you check the properties the net neme shuld be something like XLNI_1(15:0) which is a default name. You can change the name as you like, but should keep the bus delimiter unchanged. have a nice synthesis Eilert Nevo schrieb: > I am new to FPGA's and am designing my first circuit in Xilinx ISE. > > I have two 'building block' symbols on my schematic. The first has a 16-bit wide output, the second has a 16-bit wide input. > > Is there an easy way to connect the two buses in one fell swoop, or do I have to add 16 wires to my schematic?Article: 105509
Hi Gurus,
I am new to EDK and embedded software
please help me...
I am trying some example and test applications using EDK.
I have following Queries...
1. I have my application written in C, I want to view its assembly
output instead of .elf
where I can set the option to get assembly output....?
2. presently all the applications are running through internal BRAM.
If I want to map the application or part of application in external
sdram
how do I do it...?
Thanks and Regards,
Kida
Article: 105510sunwei388@gmail.com wrote: > Siva Velusamy wrote: > >>Check your trigger conditions. In the trigger window, apart from >>specifying the value for each trigger, you also have to mention exactly >>which trigger condition (or a boolean combination of conditions) needs >>to be enabled. >> >>/S >> >>Frank van Eijkelenburg wrote: >> >>>I try to use the opb/iba unit of chipscope to monitor the opb bus within >>>a simple edk design. I took the chipscope lab example as start point. I >>>am able to see the OPB signals in chipscope, but I can not set a trigger >>>point. For example, I want to trigger at a certain address 0xFFFFXXXX. >>>If I wait for the triggercondition, the behaviour is the same if no >>>condition is set (like the immediate trigger button is clicked). Another >>>problem is: I don't see assembly or c-source code in the listing window. >>>Do I have to tell chipscope where it can find sources? What could be wrong? >>> >>>In the lab example there are three control ports instantiated at the >>>ICON unit while only two ports are connected. I have two control ports >>>instantiated and connected, because ISE failed at the unconnected >>>control port (in the map phase). >>> >>>Any ideas? >>>Frank > > > Hello Frank, Siva, > > I am also working on chipscope but it doesn't work. The error message > is very strange and I suppose it is an assertion error. I use EDK8.1 > SP2, ISE8.1 SP3 and Chipscope 8.1SP3. Can you tell me what is your > configuration? Thanks a lot. > > Sunwei > EDK8.1.1, ISE8.1.3, ChipScope8.1.3 I don't have an error message (if I remove one control port from the ICON unit, but triggering doesn't work and no assembly code is shown in the listing window. FrankArticle: 105511
vlsi_kida@math.net schrieb: > Hi Gurus, > > I am new to EDK and embedded software > please help me... > > I am trying some example and test applications using EDK. > I have following Queries... > > 1. I have my application written in C, I want to view its assembly > output instead of .elf > where I can set the option to get assembly output....? > read the manual of mb-objdump > 2. presently all the applications are running through internal BRAM. > If I want to map the application or part of application in external > sdram > how do I do it...? read the manual of gnu linker or look at some examples that run from ext mem > > > Thanks and Regards, > KidaArticle: 105512
Subhasri krishnan schrieb: > Hi, > Our latest prototype board doesnt produce any output and even a simple [] > The status of GTS_CFG_B and GWE are different. Is this of significance? > > Thanks > Subhasri.K in your log for failing there is also DONEIN input from DONE pin : 0 meaning the FPGA is not configured at all, so first troubleshoot until you get done=1 then look further. the GWE is also important, but start troubleshooting done=0 issue Antti http://antti-brain.comArticle: 105513
Frank van Eijkelenburg wrote: > I try to use the opb/iba unit of chipscope to monitor the opb bus within > a simple edk design. I took the chipscope lab example as start point. I > am able to see the OPB signals in chipscope, but I can not set a trigger > point. For example, I want to trigger at a certain address 0xFFFFXXXX. > If I wait for the triggercondition, the behaviour is the same if no > condition is set (like the immediate trigger button is clicked). Another > problem is: I don't see assembly or c-source code in the listing window. > Do I have to tell chipscope where it can find sources? What could be wrong? > > In the lab example there are three control ports instantiated at the > ICON unit while only two ports are connected. I have two control ports > instantiated and connected, because ISE failed at the unconnected > control port (in the map phase). > > Any ideas? > Frank I find out how to trigger at a certain address (the example is not complete and clearly in the explanation). I have to connect the trigger out from the ILA unit to the trigger in of the IBA unit. In the ILA I can set the trigger at address 0xFFFFXXXX ANDed with a one at the Trace_AS signal. And in the IBA unit I set the trigger at the trigger in port. I arm the trigger of the IBA first and then the trigger of the ILA it works fine. However, I don't see any assembly code. Another problem is (I think with the same cause), I don't see the names of the signals in the ILA unit, while I did an import of the correct .cdc file. Any suggestions or experience with this? FrankArticle: 105514
Hi, I'm a student, I want calculate the CRC of a standard bitstream (Spartan II) Xilinx in C. I read xilinx's document( specially xapp176) and i'm applied the CRC algorithm at stream of 36 bit: address register 4bit data stream 32 bit. Example i apply the CRC algorithm at: Write the CMD Register: RCRC address=4 data stream=0x00000007 Write the FLR Register: D address=11 data stream=0x0000000d Write the COR Register: Configuration options address=9 data stream=0xXXXXXXXX Write the MASK Register: CTL MASK address=6 data stream=0x00000000 Write the CMD Register: SWITCH address=4 data stream=0x00000009 Write the FAR Register: Frame address address=0 data stream=0x00000000 Write the CMD Register: WCFG address=4 data stream=0x00000001 cycle of 22544 time Write the FDRI Register: DATA address=2 data stream=0xXXXXXXXX Write the FAR Register: Frame address address=0 data stream=0x02000000 cycle of 910 time Write the FDRI Register: DATA address=2 data stream=0xXXXXXXXX Write the FAR Register: Frame address address=0 data stream=0x02020000 cycle of 896 time Write the FDRI Register: DATA address=2 data stream=0xXXXXXXXX Now there is a write to CRC, I calculate a CRC value but is different of ISE value. I continue with other comand,i calculate the second CRR,so this is different. I make some error? Any idea to risolve my problems? Thanks. FrancescoArticle: 105515
Hi all, For I think software engineer is more near to the application, they "may think more thank hardware engineer". And "software engineering" is a research topic (they have a lot of methodology like design pattern). But I haven't find any book named "hardware engineering" (and hardware design and verification method is based on software experience, for example, SystemVerilog is something like C++). Anyone finish a good book about "hardware engineering" will be known by hardware engineer all of the world. Thanks! Davy Davy wrote: > Hi all, > > Is there some hardware RTL book like "Code Complete" by Steve > McConnell? > > Thanks! > DavyArticle: 105516
update: check Avivo=99 Video Converter from ATI http://www.ati.com/technology/avivo/technology.html Various sites have checked and reported significant improvements in encoding time. Google it to find relative links. Viron. viron wrote: > > But you can find a ready solution from matrox video editing cards. > http://www.matrox.com/video/home.cfm > Most of them could be the solution for your needs. > With Matrox RT.X100 Xtreme Pro (among other functions ) with Matrox > MediaExport provides hardware-accelerated simultaneous batch encoding > of Windows Media/RealMedia streaming formats and MPEG-1/MPEG-2 > multimedia formats with multiple resolutions, bit rates, and frame > rates. > > RT.X10 and most of the other cards provide the above functionality. > > FPGA projects can provide lightining fast solutions for specific tasks > but are VERY expensive to develop and need specialist enginners > (hopefully among us in this newsgroup) to develop the products. >=20 > Regards, > Viron.Article: 105517
Francesco Verdicchio schrieb: > Hi, > I'm a student, I want calculate the CRC of a standard bitstream > (Spartan II) Xilinx in C. I read xilinx's > document( specially xapp176) and i'm applied the CRC algorithm at > stream of 36 bit: [] > I make some error? > > Any idea to risolve my problems? > > Thanks. > > Francesco Franseso, the bitstream CRC calculation works as described in Xilinx docs. So yes if you cant calculate it properly then you have made an error and you must resolve the problem you have. each write to CRC register clear the CRC so it restarts again. also check that you have proper bit-order in the CRC in my algorithm I need todo 16 bit swap, but that depends on how you calculate the CRC. Antti http://antti-brain.comArticle: 105518
Hi peoples, This could be a stupid question and I sincerely hope not. I'm not a coder -- I'm a EE signal/systems kid who's picked up the skill lightly over the years out of neccessity (never really did it as a hobby often either). Not to say I don't like coding -- just never had the time to explore it so much in my free time. ANYWAYS. Onto the question -- it's geared towards those who work with xilkernel. I have the whole pthread/mutex/semaphore thing down, but the shared-memory API documentation is...lacking. I know how to instantiate it and call the functions, etc., but how do I <i>write</i> and <i>read</i> data from it!? There is a data struct, but it does not contain a payload/buffer -- just some basic information about the shared memory. I've also googled around quite a bit for xilkernel shared memory stuff, but with absolutely no luck finding anything tangible that could help me out. So -- any xilkernel coders out there who've worked with shared mem who might be able to help me? Thanks for your time all! -Scott NovichArticle: 105519
Hi Kida, not sure about the first one. For your second question, you can use XPS to customize the linker script: Software -> Generate Linker Script. Alternatively you can code it by hand. The linker script contains what memories all the software sections sit in. You must include your other memories as EDK-compliant peripherals in the system before they will appear in the GLS wizard drop-downs. I hope that can at least point you in the right direction. -scott vlsi_kida@math.net wrote: > Hi Gurus, > > I am new to EDK and embedded software > please help me... > > I am trying some example and test applications using EDK. > I have following Queries... > > 1. I have my application written in C, I want to view its assembly > output instead of .elf > where I can set the option to get assembly output....? > > 2. presently all the applications are running through internal BRAM. > If I want to map the application or part of application in external > sdram > how do I do it...? > > > Thanks and Regards, > KidaArticle: 105520
NEVERMIND. function void* shmat returns the start addr. of the shared mem. segment on success. I always understand things moments after I email/post about them -- does this happen to anyone else? Sorry. -Scott MKULTRA2@gmail.com wrote: > Hi peoples, > This could be a stupid question and I sincerely hope not. I'm not a > coder -- I'm a EE signal/systems kid who's picked up the skill lightly > over the years out of neccessity (never really did it as a hobby often > either). Not to say I don't like coding -- just never had the time to > explore it so much in my free time. > > ANYWAYS. Onto the question -- it's geared towards those who work with > xilkernel. I have the whole pthread/mutex/semaphore thing down, but the > shared-memory API documentation is...lacking. I know how to instantiate > it and call the functions, etc., but how do I <i>write</i> and > <i>read</i> data from it!? > > There is a data struct, but it does not contain a payload/buffer -- > just some basic information about the shared memory. I've also googled > around quite a bit for xilkernel shared memory stuff, but with > absolutely no luck finding anything tangible that could help me out. > > So -- any xilkernel coders out there who've worked with shared mem who > might be able to help me? Thanks for your time all! > -Scott NovichArticle: 105521
Hello everyone, I would like to ask if it is possible to generate 2Khz clock signal from 50Hz main frequency using an ADPLL. I have tried SN297 circuit implementation, but couldn't achieve it. Many thanks in advance, RasitArticle: 105522
manu <manuel.pezzin@free.fr> wrote: >Hello, >for the moment, I use SVN to manage different versions of te VHDL code >of my projects. >I'd like to manage my xilinx projects based on my VHDL code too. >Until now, I just put the <project>.ise and <project>.ucf files under >version control and it was enough to be rebuild the whole project. >Now, I've added an embedded processor to my ISE design and I'm a bit >confused because there a huge set of automatically generated files. I'd >like to keep under version control just the minimum set of files >required to rebuild the whole project. I think there's at least the ><project_up>.xmp, <project_up>.mhs and <project_up>.mss files, but is it >enough ? >Any idea ? Use: ls -uAlF ,ie the last access time of the file(s). Quite hand sometimes to find out which files that are actually used. might differ for posix systems.Article: 105523
Phase-Locked Loops : Design, Simulation, and Applications (Professional Engineering) (Hardcover) by Roland E. Best Chapter 6. HTH, Syms. "raso" <rasit.sahin@yahoo.co.uk> wrote in message news:1153823652.202609.67390@m79g2000cwm.googlegroups.com... > Hello everyone, > > I would like to ask if it is possible to generate 2Khz clock signal > from 50Hz main frequency > using an ADPLL. I have tried SN297 circuit implementation, but couldn't > achieve it. > > Many thanks in advance, > > Rasit >Article: 105524
On a sunny day (25 Jul 2006 03:34:12 -0700) it happened "raso" <rasit.sahin@yahoo.co.uk> wrote in <1153823652.202609.67390@m79g2000cwm.googlegroups.com>: >Hello everyone, > >I would like to ask if it is possible to generate 2Khz clock signal >from 50Hz main frequency It is important to filter the mains frequency first from spikes and the like. Then perhaps create a pulse at zero crossing to drive the PLL.
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