Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Hi get it there http://www.xilant.com/downloads/xMB32_bundle.ZIP that version was fetched from rapidshare, info about it was at circuitcellar forums, http://bbs.circuitcellar.com/phpBB2/viewtopic.php?p=11186& i just made a duplicate from rapidshare (link at the bottom of the cc forum messages) so there is no need to deal with the rapidshare download annoyance. I have not yet tested this core, so no idea how useable it is, AnttiArticle: 105301
homoalteraiensis wrote: > 1) "Learn about semaphores" > > I know about semaphores, but according to my understanding it is a > feature of a dp ram to be accessed the same time from both sides. If > I'd implement a semaphore based access, there would be no need to use a > dual ported ram, would it? The data that appears is totally wrong, > having nothing to do with old data, as expected. > > Anyway, I''ll camoe back to this issue later. > > > 2) "Upgrade to 6.0 SP1" > > Thanks, yes, I am with 6 SP1 now but the same experience. I also think, > that it is a matter of physical timing. I will do a back annotation sim > on order to find out. In cases like this, it can help to look at the corruption. It is unlikely to "having nothing to do with old data, as expected". eg try gray code style old/new changes, and see if the corruption ever goes outside the changed bit(s). The failure rate (how many ppm?) can also help give clues to the failure mechanism. -jgArticle: 105302
I was just shown how to infer a Xilinx BRAM with a constant array. I used a counter to address it. Is there anyway to infer a FIFO so that the internal counters of the FIFO are used? type i2c_type is( NOP,START,STOP,ZERO,ONE,ACK,REPEAT,HALT ); signal i2c_data : i2c_type; type init_array_type is array(natural range <>) of i2c_type; constant i2c_data_array : init_array_type := ( STOP, START, ONE,ZERO, ACK, START, NOP, REPEAT ); Brad Smallridge aivisionArticle: 105303
Hello! I am a beginner in VHDL programming. i am programming an Xilinx XC9572XL at the moment, and i have so far used VHDL programming. I am a little bit unsure, if i can combine VHDL and Shcematic, so a part of the circuit is described by Schematic, and another by VHDL. Is it possible, and how do i "bind" these things together ?? When i add a new source as an Schematic and compile, it only uses the VHDL file and ignore the Schematic-file.. Can somebody tell me how i do this, or give me a link to a site that descibes it ? I have looked at Xilinx' site, but found nothing... Regards, Per Jensen, Demmark.Article: 105304
Brad Smallridge wrote:
> I was just shown how to infer a Xilinx BRAM with a constant array. I used a
> counter to address it. Is there anyway to infer a FIFO so that the internal
> counters of the FIFO are used?
You can infer counters and a dpram to construct a fifo.
Here's an outline.
http://groups.google.com/groups/search?q=write+your+own+fifo+pop_head_ptr
-- Mike Treseler
Article: 105305heinerlitz@gmx.de wrote: > Hello, > > we have a Virtex4 FPGA and are looking for availlable hardware sorting > algorithms. I couldnt find anything @opencores.org however I guess that > it has been worked on this subject. > > The Virtex4 supports 2 PowerPCs and lots of Block RAMs so everything > seems to be there. Are there any projects and what speeds could be > estimated for sorting 64 bit integers? > > thx Heiner > How many objects and how many bits in each for the sort? How many clocks do you have to complete the sort? Are the results accessed sequentially or asa table? These are some of the important questions you need to answer before you can determine how best to sort the data.Article: 105306
>This is my experience with anything PCI related, so I'm still not very >clear on whether I can get away with a target, or if I'll need to >mastering/DMA capabilities. I know that theoretically, the max tranfer >rate of the bus is 133 MB/s w/ 33MHz systems. The intended customer of >this thing is going for low cost, so I'm not going to assume that it >will be used with a computer that supports 66Mhz or 64-bit transfers. >Ideally, I would like to be able to guarantee 54 MB/s with pretty much >equal I/O rates (27MB/s into and out of the device). The key idea is that most CPUs (or host bridges) only transfer one word (32 bits) per transaction when it is reading/writing to a PCI target. Look at the timing diagrams for simple target transfers. How many cycles do they take? 54 is 40% of 133, so you have to do a whole transaction in 2 cycles. It just isn't going to happen. My only one-word-per-transaction observation is several/many years old. Things might be better now. I wouldn't bet on it without seeing a nice picture on a scope. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 105307
Brian McFarland wrote: > I know that theoretically, the max tranfer > rate of the bus is 133 MB/s w/ 33MHz systems. That's the raw rate based purely on the signaling. Once you add the PCI protocol on top of that, which includes arbitration phases etc, IIRC the maximum *theoretical* data transfer rate is more like 120MB/s. Having said that, I've worked on a design which included an Altera PCI core and a DMA bus master transferring large chunks. In a *desktop* PC running Win2K, the *sustained* throughput was around 100MB/s. FWIW IIRC the same hardware under Linux didn't get much over 80MB/s, but that's another story. > Ideally, I would like to be able to guarantee 54 MB/s with pretty much > equal I/O rates (27MB/s into and out of the device). Most of the time, > rates should be lower than that, but just about the max I could ever > need it to be. What type of transfers are you looking at? Will it be PIO (single byte/word/dword) transfers? Initiated by the PC? Or DMA, initiated by the card? Is the data isochronous 27MB/s? Or can it be buffered and transferred periodically in large chunks? Your answers to the above questions will determine the suitability or otherwise of any potential solution. As Eric pointed out elsewhere in this thread, typically host PCI chipsets won't burst more than a single cache line. And even that requires attention to how you configure your PCI memory space. Single host reads can be very inefficient, as often the target must disconnect whilst the data is fetched. In the meantime, the bus is free for other peripherals to grab. For example, with the opencores PCI core (for which *all* reads are posted), we're seeing reads disconnected *twice* before the third succeeds, albeit on a non-intel platform where the host can be quite slow to retry. In a nutshell, if you're bus-mastering DMA in reasonable chunks, then 54MB/s should be easily achievable. If not, then you need to characterise your transfer profile before I could comment any further. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 105308
Dan wrote: > Ed McGettigan wrote: > > Are you sure that you set up the >JTAG chain properly in iMPACT when you > generated the ACE file? The >chain should be defined as > > XCF32P -> XC4VSX35 -> XC95144XL > > How do I set up the JTAG chain in iMPACT? What I see on the iMPACT is: > > xc4vsx35 myfile.bit -> XCCACE-TQ144I Since you haven't described the full chain for iMPACT, the software isn't creating a valid ACE file for your chain to bypass the other devices. When you are in the iMPACT main window you need to either select the toolbar icon for "Add Device" or right mouse button click to "Add a device". You need to create the same chain in the tool as exists on the board first, then you can go ahead and assign your bit file to the SX35 and generate an ACE file. EdArticle: 105309
heinerlitz@gmx.de wrote: > Hello, > > we have a Virtex4 FPGA and are looking for availlable hardware sorting > algorithms. I couldnt find anything @opencores.org however I guess that > it has been worked on this subject. > > The Virtex4 supports 2 PowerPCs and lots of Block RAMs so everything > seems to be there. Are there any projects and what speeds could be > estimated for sorting 64 bit integers? > > thx Heiner It all depends on what type of data you have, is it already sorted almost correctly, or soso, or fully random. look at Knuths texts for the algorithms. If you need to sort a huge array of integer keys I favor the radix sort, for 64 bit values, use 8 passes with 256 variable length output buckets whose total size will be same as initial array.. The time will go towards 16N memory cycles which may use the fastest rate of memory access, potentially at DDR rates even. Its is just like sorting a telephone book where you take the initial say random name list and put all the names beginning with 'a' into the 'a' bucket and similar for other letters. In this case you have 256 letters. On 2nd pass inspect 2nd letter. Every time you have say 16 'a' words you bag them and put them into the 'a' pile. You want to do mostly reads and mostly writes as bursts rather than interleaving reads & writes. Blockrams can be used as your letter bags. Its get more interesting when you figure how to manage the buckets. BlockRams can be usefull for holding blocks of each letter. 1 Blockram with 256 64b words would only hold 1 word buffer for each of the 256 buckets. So 16 Blockrams would hold 256 buckets of 16 words deep. You want them to be as deep as possible to reduce the cost of bucket management. You could think of these Blockram buckets as soft 256 Fifos (16 word deep) into main memory. Only when each letter bucket fills do you need to have to write it out and find a new place to write it. One way to do that is to assume the input data is matched by a similar sized output array which is broken into 16 word cells. Add to that a link list to manage the cells, then its is a matter of managing 256 link list heads and a simple table that will need 1 word per cell. If you get really good at this, with small buffers for inputs and outputs, you can effectively do this inplace in main memory, though many will use separate in and out buffers. Every time 16 words are read in, that cell is added to a free list. On avg, you write 1 of the 256 letter cells for every cell you read in. Memory cost is therefore N+N/16 for 16 word deep buffers. Ofcourse you should proto this in C/whatever and observe its operation. The HDL code will look similar. John Jakson transputer guyArticle: 105310
"homoalteraiensis" <fpgaengineerfrankfurt@arcor.de> wrote in message news:1153325559.258147.44130@p79g2000cwp.googlegroups.com... > > 1) "Learn about semaphores" > > I know about semaphores, but according to my understanding it is a > feature of a dp ram to be accessed the same time from both sides. If > I'd implement a semaphore based access, there would be no need to use a > dual ported ram, would it? The data that appears is totally wrong, > having nothing to do with old data, as expected. > You're instinct is right, learning more about semaphores will be of no help in this particular situation. > Anyway, I''ll camoe back to this issue later. > > > 2) "Upgrade to 6.0 SP1" > > Thanks, yes, I am with 6 SP1 now but the same experience. I also think, > that it is a matter of physical timing. I will do a back annotation sim > on order to find out. > Timing sim runs don't always catch things either. If it's a timing problem then static timing analysis is what you need to solve the problem. Quartus is already providing that info, but since you said you tried running it slower (not sure how slow or if it was slow enough per the static timing analysis) so it might not be a timing problem either which would then leave it as some form of Quartus bug which is why submitting a bug report to Altera would help. KJArticle: 105311
Hi Per Jensen, All the schematics are converted to VHDL or Verilog (look at the source's properties dialog). You can see the generated HDL code by double-clicking the "View HDL functional model" in the "Design Utilities" in the process window. To add an instance of a schematic to an HDL code double-click on "View HDL instantiation tamplate" in the "Design Utilities" in the process window, copy, paste and modify the code to the destination module (verilog) or architecture (VHDL). To add an instance of a schematic to another schematic: close all schematic windows, in the processes window double-click the process "generate schematic symbol" in the "Design Utilities". than open a schematics and in the categories window there will be a new category with the path of your project as the name, enter this category and choose the needed generted by you symbol. I hope that this helped! Per Jensen wrote: > Hello! > > I am a beginner in VHDL programming. i am programming an Xilinx XC9572XL > at the moment, and i have so far used VHDL programming. > > I am a little bit unsure, if i can combine VHDL and Shcematic, so a part > of the circuit is described by Schematic, and another by VHDL. Is it > possible, and how do i "bind" these things together ?? When i add a new > source as an Schematic and compile, it only uses the VHDL file and > ignore the Schematic-file.. > > Can somebody tell me how i do this, or give me a link to a site that > descibes it ? I have looked at Xilinx' site, but found nothing... > > Regards, > Per Jensen, > Demmark.Article: 105312
On Sun, 16 Jul 2006 05:15:36 -0700, Rashid wrote: > At work, we encode tons of video and some/most have fairly short TTM ... > So we use SW that supports variety of video format and encode video in > Flash/WM and other formats. > > Now the problem statement: it is dead slow. We use latest-greatest in Texas Instruments' DaVinci chips may be just the ticket. $20-$70 price range, containing an ARM and a DSP core. Codecs run on the DSP while ARM runs the I/O. I think they have a development board for few thousand US$. Their development env. is Linux based, which suits me just fine.Article: 105313
RHDL 0.5.0 has been released! What is it? ============== RHDL (Ruby Hardware Description Language) is a DSL (Domain Specific Language) for describing and simulating digital circuits. It looks very similar to VHDL. RHDL is built entirely in Ruby: no lexers or yaccs were harmed (or even created) in the development of RHDL. It's a nice example of Ruby's capabilities for creating DSL's (the secret is Ruby's anonymous code blocks - something lacking in some of those other open source, object oriented scripting languages out there.) Where does it live? ===================== http://rhdl.rubyforge.org/ User guide at: http://rhdl.rubyforge.org/UsersGuide.html What's changed: ================= RHDL now has at least 50% more Ruby metaprogramming goodness! The DSL has been changed to remove some of the Ruby-isms that were in RHDL's previous incarnations (class, super - these are now gone replaced with the model declaration). Examples have been updated to reflect the new 'syntax' and many unit tests have been added (more still needed). Other changes: * <= has replaced << for signal assignment ( <= has lower operator precedence which is a good thing) * lte (less than or equal) method has been introduced now that <= has been taken for assignment (gte - greater than or equal - method has also been introduced for signals for orthogonality with lte) * models instead of classes - see docs and examples. Big change to the RHDL syntax. Hopefully it makes things less confusing for non-Ruby programmers who want to use RHDL. * named argument associations in model constructors (again, see docs and examples) [oh, and model constructors themselves are created for you now (more of that metaprogramming goodness!) so you don't have to define an initialize method.] * inputs, outputs, generics (see docs/examples) * lots of unit tests added (but more are still needed) * bug fixes * lots of other stuff I'm forgetting about... The Future: ============== In future releases RHDL will (hopefully) interoperate with BLIF (Berkeley Logic Interchange Format) and also be translatable to VHDL. More docs and examples coming as well... How much would you pay for all of this? ======================================= Send cash, checks, MacBook Pros to me at... oh, wait, actually it's free and under the same license as Ruby. Damn - I really was looking forward to that MacBook Pro. PhilArticle: 105314
Phil Tomson schrieb: > RHDL 0.5.0 has been released! [] > How much would you pay for all of this? > ======================================= > Send cash, checks, MacBook Pros to me at... oh, wait, actually it's free > and under the same license as Ruby. Damn - I really was looking forward to > that MacBook Pro. > > Phil Hope you get your MacBook Pro - sent you a very small Paypal donation (hope your c-a-f email address is valid?) Antti http://antti-brain.comArticle: 105315
I think the reset statement was the solution to what I was out for. Sometimes the problems are so simple that you can't see the solution straight away.. /Johan Gabor wrote: > Johan Bernspång wrote: >> Gabor, thanks! >> Of course a reset statement would prevent ISE from turning the registers >> into SRLs. >> I also found out, by browsing through some old course notes from X that >> duplicated registers named reg_1, reg_2 etc are mapped into the same >> slice. They should be named reg_a, reg_b and so forth. Maybe that will >> help as well. >> >> /Johan > > Also look in the Mapping Options for "disable register ordering" if > this > is a problem. In the old days, slice packing was done by the mapper. > Now I'm not sure how much difference this makes if you allow the > XST synthesis to pack logic into slices. There may be a similar > setting for XST, but I couldn't find it. > > Regards, > Gabor > >> Gabor wrote: >>> Any register with a reset term should not infer SRL, since there >>> is no asynchronous (or synchronous) reset on distributed RAM. >>> So normally just adding the asynchronous reset process for the >>> pipeline stages and not for the slower stages should get the job >>> done. I've noticed that XST likes to use SRL whenever possible, >>> and it will warn you about large registers that don't fit into SRL >>> due to reset requirements. >>> >>> Johan Bernspång wrote: >>>> Hi all, >>>> >>>> I'm building a design where I want ISE (8.1) to extract the shift >>>> registers in some parts, i.e. where I have inferred SRL counters etc, >>>> and not to extract them in other parts. For instance where I have coded >>>> multiple stages of pipelining in order to obtain timing closure. Has >>>> anybody done this? Partial shift register extraction, that is. >>>> >>>> The design is occupying about 50% of a Virtex-2 2000 and running mostly >>>> at 200 MHz. This is why I need to insert some pipelining between >>>> different stages in the signal path. My intention is to add a few stages >>>> to enable ISE to divide the routing in shorter bits. >>>> >>>> Any input is highly appreciated >>>> >>>> /Johan -- ----------------------------------------------- Johan Bernspång, xjohbex@xfoix.se Research engineer Swedish Defence Research Agency - FOI Division of Command & Control Systems Department of Electronic Warfare Systems www.foi.se Please remove the x's in the email address if replying to me personally. -----------------------------------------------Article: 105316
Hi Very first Virtex-5 test reports, tested with OpenFire (32bit Risc, MicroBlaze clone) targetting V5VLX50-3 (fastest speed grade) System clock constrained to 200MHz and .... ? ISE reports timing is met! all I had todo was enabling xplorer script (its not integrated fully with ISE) the timing was met on round 1 already. if non xilinx optimized 32 Bit softcore RISC can run at 200MHz, not bad. Sure the test setup was using only BRAMs for code-data storage and had only single FSL link as connection to external world, still a "screaming-streaming" softcore that takes 2% of logic and runs at 200MHz is pretty cool I think. AnttiArticle: 105317
Antti wrote: > if non xilinx optimized 32 Bit softcore RISC can run at 200MHz, not > bad. Sure the test setup was using only BRAMs for code-data storage and > had only single FSL link as connection to external world, still a > "screaming-streaming" softcore that takes 2% of logic and runs at > 200MHz is pretty cool I think. If you need only 2% it would be really cool to implement 50 parallel cores in one FPGA. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 105318
"Brad Smallridge" <bradsmallridge@dslextreme.com> wrote in message news:12bt8m01ibk3n74@corp.supernews.com... >I was just shown how to infer a Xilinx BRAM with a constant array. I used >a counter to address it. Is there anyway to infer a FIFO so that the >internal counters of the FIFO are used? You can use lpm_fifo (single clock FIFO) or lpm_fifo_dc (dual clock fifo). These are fully parameterized standardized functions in the LPM library and they will be portable to different target architectures and you won't have to bother (re)writing code to implement a FIFO. KJArticle: 105319
We have mentioned Tarfessock1 before and now at the last point where we can add features for the board. You know have the last chance to ask for things you might want in this Cardbus format card so do ask. Currently the spec on the card is as follows: Dual Spartan-3E (Device 1 notionallly fixed covering Cardbus interface etc), Device2 programmable from Device1 or SPI prom. Device 2 = XC3S1200 or XC3S1600 4 ch DAC 8 ch A/D O/P JTAG - looks like parallel port + cable3 for programming outside target boards. Supported by Device1. 1 serial RS232 interface outside world for MicroBlaze support etc. 1 internal serial (TTL) also possible to Device2. 4 ch RS485 serial controllable half duplex. SDRAM + second SPI Flash on Device2 Approx 70 5V tolerant I/O to outside world. Switched 3.3V O/P to supported external modules that don't need to be powered all the time (i.e. for running in the wild on laptop battery etc). We are using a 120 pin connector to support all these features and there will be breakout board/s available to better pitches. We are currently still on schedule for a September launch. John Adair Enterpoint Ltd. - Soon to be Home of Tarfessock1. The Spartan-3E Cardbus Development Board. http://www.enterpoint.co.ukArticle: 105320
Hi, In adition to filter and fft creation, Tyd-IP Code Generator now generates VHDL for NCO design. Demo may be downloaded from website. http://www.tyder.com BobArticle: 105321
"Frank Buss" <fb@frank-buss.de> wrote in message news:q00un4e7pes4$.dq3b878hyk9z.dlg@40tude.net... > Antti wrote: > >> if non xilinx optimized 32 Bit softcore RISC can run at 200MHz, not >> bad. Sure the test setup was using only BRAMs for code-data storage and >> had only single FSL link as connection to external world, still a >> "screaming-streaming" softcore that takes 2% of logic and runs at >> 200MHz is pretty cool I think. > > If you need only 2% it would be really cool to implement 50 parallel cores > in one FPGA. > ... cool and hot! :-) Antti, Any idea where the timing improvement is coming from? Ben mentioned the othyer day that the carry chain is 20ps / LUT; I guess that doesn't hurt! Cheers, Syms.Article: 105322
Hi, I build a DDR2 controller using the Mig 1.5. In functional simulation everything works without problems (as alwayys). In the hardware implementation it does not work. I used the synthesizable testbench which is provided by the Mig. My design is driven by a 200Mhz Refclock and 125MHz system clock. I used chipscope and oscilloscope to figure out the following: -All clocks (200, 90, 50) work properly. Also clk0 which controlls most part of the ddr2controller module. -I can messure the correct RAM clock on the PCB -After the reset WDF FIFO is empty and the internal writeWDF signal toggles untill the WDF almost full signal goes active. It stays high forever. - The other signals on the PCB (or on chip using chipscope) especially (ras, cas, we, cs) do not toggle at all. SO data is never written to the ram and never read out. The FIFO just runs full. Did anybody experience similar problems and can help? The xilinx design only uses synchronous resets. These are regarded like normal signals by the router and hence do not meet the timing (high fan out probably). Is this ok? How are resets treated in FPGAs anyway? I always use asynchronous reset so they dont interfere with timing issues. Can i tell XST in anyway that it should treat reset signals properly? How to tell XST to make a reset tree synthesis? Could it be due to the FIFO16 bug? I dont think so, as it doesnt run at all. The controller should at least try to access the RAM several times, right?Article: 105323
Hi all, I would like to know before upgrade if EDK8.1i is compatible with ISE8.2i. Thanks in advanceArticle: 105324
Hi everyone, I am looking to buy a board that has the following features: 1. High-speed ADC 2. Xilinx Virtex-2Pro or Virtex-4 FPGA with Rocket I/O capability I looked at the Xilinx development boards (the matrix_Xdev_board brochure) and could not find one with Rocket I/O and the ADC. The closest product I have with a high-speed ADC and an FPGA is National Semiconductor's ADC08D1500 Dev board(arnd $3800). However, I want to Rocket I/O as well to communicate with other FPGA boards and sensors or peripherals connected to it. Please let me know if you know of a product that has these features. Thanks in advance, Vivek
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z