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mk wrote: > accessing the internal memory with '.' (verilog's hierarchical access > operator i am assuming) will not work after p&r. you have to use the > memory as a memory ie give an address at its ports and get the data > from the data ports. as you say "block ram model" is just a model. But why?. I am a beginer in this... I thought that the post par model is only a verlog description (with delay for component and routing included). Why cant we access an internal variable in the simulation?Article: 103451
Or please tell me a method to combine two internal variables (mem in the RAMB16 block). Situation is i have to xor mem variable from 16 RAMB16 blocks and show it as an array 32x64. I am able to view this through the waveform window.Article: 103452
Yes, You can use the xmd and chipscope at the same time. This allows crosstriggering between chipscope and processor debugger. There is an example of using ChipScope with MB/MDM on our website. http://www.xilinx.com/ise/embedded/chipscope_ex_81.zip Göran Bilski saumyajit_tech@yahoo.co.in wrote: > Hi Peter, > > I wanted to know few things from your explaination. > > 1) Did you mean that you can use both Debugger (xmd) and Chip scope at > the same time? > > 2) You mentioned a nice point saying " stop the processor on a > Chipscopre trigger event or trigger ChipScope on a software > breakpoint" > > How do you do this ? I am verymuch curious to know more about this. > If you can send me some links, then it will be really nice. > > Regards, > saumyajit > > > > Peter Ryser wrote: > >>XMD and ChipScope DO coexist on the same JTAG chain. You can even >>cross-trigger, i.e. stop the processor on a Chipscopre trigger event or >>trigger ChipScope on a software breakpoint to get a complete picture of >>your hardware/software system at the time of the event. >> >>- Peter >> >>Ben Jones wrote: >> >>>Hi Joel, >>> >>>"Joel" <jceven@gmail.com> wrote in message >>>news:1149173927.595412.96800@h76g2000cwa.googlegroups.com... >>> >>> >>>>Xilinx gurus, >>> >>> >>>>I want to use a ChipScope ILA or 2 in an EDK design. >>>>... >>>>What say you Xilinx gurus out there? >>> >>> >>>What version of EDK are you using? >>> >>>To the best of my knowledge, the chipscope ILA, IBAs and VIO modules are >>>available in the EDK IP catalog (under "Debug"). You can drop these in just >>>like any other IP block (you need to add a chipscope "ICON" block and wire >>>that up too). >>> >>>Not sure whether the debugger and chipscope will co-exist on the same JTAG >>>chain (I'm fairly sure they won't). I believe you can get round this by >>>means of a debugger connection over RS232, using an XMD "stub" - but don't >>>quote me on that; I never did it! >>> >>>Cheers, >>> >>> -Ben- >>> >>> > >Article: 103453
Mentor's Precision RTL support a subset (including interfaces) of SV, I am not sure if there are any others (I am a VHDL person :-) You can ask them for a 30 day evaluation license, Hans www.ht-lab.com "Luke" <lvalenty@gmail.com> wrote in message news:1149114433.143873.130760@g10g2000cwb.googlegroups.com... >I really wish I could use SystemVerilog to develop RTL in ISE. Do any > of the Xilinx folks around know if there there are any plans for this? > I've been using SV for some time now and like it much more than either > VHDL or plain old Verilog. If there was a beta tester program I would > love to use it and file bug reports. > > -Luke >Article: 103454
In the post par model i observed that the variables are started with '\' sign. Also instantiations are also started with this sign like X_RAMB16 \RR/ram etc. Why this sign is in front of all variables ???Article: 103455
Excellent answer. I'll design it in now. Thanks. Roger. "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:e5n49p$cq03@cliff.xsj.xilinx.com... > Roger wrote: >> I'm planning on using the TXPOLARITY and RXPOLARITY attributes in the >> RIOs on a Virtex-II Pro device (via Aurora cores) to swap the function of >> the N and P lines in order to help improve the path of PCB tracks to an >> edge connector. >> >> Has anyone used this polarity swapping capability before? Does it work >> OK? Are there any "undocumented features" or pitfalls that I should know >> about before designing the board in this way? >> > > There is no difference when asserting the TXPOLARITY and RXPOLARITY inputs > on the Virtex-II Pro MGTs other than a logical inversion of the data > stream to > accommodate P/N pin swaps. The Aurora core includes detection logic in > the > receiver portion and will automatically switch the RXPOLARITY state if it > needs to in the initialization state. > > The only "pitfall" to watch for is to make sure that you properly document > your schematic so that when someone else picks it up a few years down the > road they know that you did this intentionally and don't curse your name > after spending 3 weeks debugging why the link didn't work. > > Ed McGettigan > -- > Xilinx Inc.Article: 103456
For the academics out there we are please to announce an offer, in conjunction with our partners Synplicity(R) Inc., of free tools. Under our University Access Program (UAP) universities can now buy one of Raggedstone1 lab packs and get a free 5 year Synplify Pro and Identify license. License is a non-commercial only use and subject to US export regs etc. etc.. For UAP details go http://www.enterpoint.co.uk/uap/uap.html. John Adair Enterpoint Ltd. http://www.enterpoint.co.ukArticle: 103457
Hi, I would like to know if there is a away to change the random seed used by the Xilinx tools ? I would like to do this in order to compare the results of multiple place and routes. Regards AltafArticle: 103458
Generally latency and delay would be just different perspectives. Regarding your question on why a latency of 0 is provided... - In case one has a need to change the latency value or remove the block (when 0 delay is needed between 2 signals), it is easier to just setting a parameter to 0, instead of deleting it and re-adding it if needed later on. Also since sysgen designs can be created using matlab APIs, it makes it easier and faster to just change a property and not having to delete a block and redraw a block. It is provided as a convenience to designers. --hemang "Fizzy" <fpgalearner@gmail.com> wrote in message news:1149211987.152172.169510@g10g2000cwb.googlegroups.com... > Why system generator block accepts delay block with zero latency. I > always thought latency is actually the delay if that's right delay > block should have minimum of 1 latency. Is my understanding is wrong if > not than can some buddy tell me what is the difference between latency > and delay and why delay block can have zero latency > > Thanks >Article: 103459
Peter Alfke wrote: > How many angels can dance on the tip of a pin? Rats! I've been counting the ones dancing on the head of the pin. :-) MarcArticle: 103460
Marc Guardiani wrote: > Peter Alfke wrote: > > How many angels can dance on the tip of a pin? > > Rats! I've been counting the ones dancing on the head of the pin. :-) > > Marc I googled and found this: "Let's get a couple things straight. First, you're misquoting the saying in question. According to unimpeachable sources, it's not how many angels can dance on the head of a pin, it's how many can do it on the point of a needle--which, of course, makes more sense. Second, the earliest citation I can find is from a book by Ralph Cudworth in the 17th century, which is a suspiciously late in the day." from "The Straight Dope" "Head of a needle" never seemed to convey the intended meaning... Peter AlfkeArticle: 103461
Should be no problem.Article: 103462
Under MAP or PAR properties (right click) change the "Starting Placer Cost Table (1-100)" You could also try enabling Multi Pass PAR... -Brandon the.gaffar@googlemail.com wrote: > Hi, > > I would like to know if there is a away to change the random seed used > by the Xilinx tools ? > > I would like to do this in order to compare the results of multiple > place and routes. > > > Regards > > AltafArticle: 103463
Dear FPGA Pros, I have a problem installing WebPack on Linux. While Xilinx recommends RedHat, I would like to use one of the free distributions. I tried Fedora Core 5, which I believed is the closest to RedHat I could get. Unfortunately, install fails, while searching for libstd++.so.5 Fedora comes with version 6.0.8. So here are my questions: - did you have any success using a free Linux distribution? - which distribution did you use? - any other hints? Thank you, best regards Felix -- Dipl.-Ing. Felix Bertram http://www.bertram-family.com/felixArticle: 103464
On Fri, 02 Jun 2006 21:43:01 +0200, Felix Bertram wrote: > Dear FPGA Pros, > > I have a problem installing WebPack on Linux. While Xilinx recommends > RedHat, I would like to use one of the free distributions. I tried > Fedora Core 5, which I believed is the closest to RedHat I could get. > > Unfortunately, install fails, while searching for libstd++.so.5 > Fedora comes with version 6.0.8. > > So here are my questions: > - did you have any success using a free Linux distribution? > - which distribution did you use? > - any other hints? > > Thank you, > best regards > > Felix You have to install the compatibility libraries, search for compat-libstdc in yumex.Article: 103465
Looks like I have a few more hurdles before getting started with my Spartan 3e board. This time, I seem to be having trouble generating models with Core Generator. I am using the Xilinx ISE 7.1i webpack - not sure if that makes a difference of not. Although I'm not sure if it applies to 7.1i, I read that 8.1i has problems with spaces in the path names, so I made sure to install ISE to a path with no spaces. (C:\MyData\Xilinx\ISE_71i). The Core Generator project is likewise stored in C:\MyData\Xilinx\Coregen. So far, I can do simple builds in pure VHDL with good results (I can even program the bitstream into the target board with impact) However, trying to create models in coregen results in an exception error for some (I don't ever see the customization screen) and for others, like the FIFO model I need, I get all the way through the process, only to see this: Customizing IP... Finished Customizing. Generating IP... ERROR:coreutil - IO error when creating files for XST synthesis! ERROR:coreutil - Failure to generate output products Finished Generating. And some actually seem to work. I can create a distributed memory model perfectly fine: Generating IP... Generating Implementation files. Generating the VHDL wrapper. Generating the VHDL instantiation template. Generating the SYM file. Generating ISE symbol file... Generating NGC file. Finished Generating. Successfully generated dist_mem. Customizing IP... Finished Customizing. I can also create DCM models as well. I haven't tried everything, but it seems kind of hit&miss. Any clues? I need a FIFO model for a serial transciever I am porting over from an Altera design. The FIFO is a single clock, 8-bit wide, 512 locations deep, model with almost full & almost empty. For reference, I have ISE 7.1i (webpack) with SP4 installed, and IP update 3. I have tried both versions of Fifo Generator installed (2.1 and 2.2) and both produce the same errors. Thanks (again) -SethArticle: 103466
Is it possible to add a USB interface to the WRT54G board (a Linksys broadband router)? I found the following schematics ... http://www.allaboutjake.com/network/linksys/wrt54g/hack/ http://www.semiconductors.philips.com/pip/isp1521.html#support Thanks.Article: 103467
be.geek@gmail.com wrote: > Is it possible to add a USB interface to the WRT54G board (a Linksys > broadband router)? > > I found the following schematics ... > > http://www.allaboutjake.com/network/linksys/wrt54g/hack/ > http://www.semiconductors.philips.com/pip/isp1521.html#support > > Thanks. > You should be able to add a USB interface to anything, even a trailer hitch. What is your question anyway?Article: 103468
Using Xilinx ISE 7.1i, service pack 4, IP update 3 Windows 2000 Pro Tutorial: "ISE Quick Start Tutorial" When creating the Test Bench, "Design Simulation", page 9 of "qst.pdf", in the secion "Adding Expected Results to the Test Bench Waveform", the tutorial says I should see an item: "Generate Expected Simulation Results", but the closest thing in my Processes for Source pane is "View Generated Test Bench", with a question mark in front of it. Well, I'm an experimenter, so I clicked it. The generated VHDL code showed up, and the question mark turned to a green checkmark. Then, the tutorial says, "The Expected Results dialog box will open." Well, I get the waveform editor, but no waveforms (other than the ones I'd already entered a few steps before), and nothing that looks like an ordinary dialog box with a "Yes" button. What should I do? I've looked on the Xilinx site, in their "answers database", and I've searched both groups by google, and haven't seen anything addressing this particular situation. Thanks, RichArticle: 103469
In article <1149302584.290941.306900@i39g2000cwa.googlegroups.com>, be.geek@gmail.com wrote: > Is it possible to add a USB interface to the WRT54G board (a Linksys > broadband router)? Depends a lot as to whether you are doing it out of need or for the fun of it. The US Robotics 5461 is built with similar hardware and runs open source Linux-based firmware so you could get inside and play. Complete with USB. Bought mine supposedly for $15 from CompUSA after rebates. Maybe all the rebates will actually be honored? Some have arrived, others have not. http://www.usr.com/products/networking/wireless-product.asp?sku=USR5461Article: 103470
The easiest way is to add an ethernet to USB converter. (Not the typical USB to ethernet adapter.) These are typically marketed to connect USB printers to a network. (PS to DK: The WRT54 is also Linux based, and the source and tools are available on the web) But spending the $15 on a router that already has all the interfaces makes a lot of sense.Article: 103471
Hi I have a question. What is the difference between Logic Cells and Slices on an FPGA? I have noticed that on the Virtex-II Pro that the amount of Slices = amount of Logic Cells * 4/9 Thanks MichielArticle: 103472
Dear all, I am implementing FLOATING point FIR filter with LATTICE
structure.
For this project i want 32bit Floating Point ADDER and
MULTIPLIER in VHDL.
Please tell me how and from where i can get the VHDL code for the
same.
THAKING YOU ALL.
Shivkaran Ravidas
Article: 103473Felix Bertram <flx@bertram-family.com> wrote: >Dear FPGA Pros, >I have a problem installing WebPack on Linux. While Xilinx recommends >RedHat, I would like to use one of the free distributions. I tried >Fedora Core 5, which I believed is the closest to RedHat I could get. >Unfortunately, install fails, while searching for libstd++.so.5 >Fedora comes with version 6.0.8. >So here are my questions: >- did you have any success using a free Linux distribution? >- which distribution did you use? >- any other hints? I use ISE under FreeBSD-6.0/i386 (32bit) without any major problems. The only things that doesn't work out of the box is launching pdf's and transfering .bit to physical chip. And these things are not that hard to fix. I downloaded the complete .sh file. And then extracted the contents, and worked it from there. ktrace was helpful =)Article: 103474
Hi. I want to get my brain around USB interfaces, how to design the hardware and the software, and eventually to find what economic hardware solutions are available, and how USB hardware interfaces can be arranged to make the best use of generic USB drivers to minimise problems associated with driver installation. It's not something that I've been able to investigate in the time-limited projects that I've done as an electronic designer, and so I've tended to use RS485 interfaces or other alternatives. I've decided that It's high time that I understood USB, so I'll pick up the knowledge by occasionally dabbling with it at home over a period of a few months which is something that works OK for me. I'm not very good at reading screeds of technical description and retaining it in my memory, so I need to get my hands dirty with some experimental design and coding that I can interact with to get the concepts anchored in my mind. I'm reasonably competent in C, C++, VHDL and Verilog, and can code quite swiftly. To kick off, I'd like to get an FPGA board with a RAM-based FPGA that can be configured via a serial or USB cable to a laptop. For my experiments, the board also needs a USB interface that passes the raw USB data stream directly to the FPGA, or it should be easily convertible to do so. The FPGA needs to be big enough to hold open-source HDL USB interfaces and to hold models that mimic the interfaces to common USB equipment like flash keys, printers and modems. Any suggestions? I'm aiming to keep the cost reasonable - $100 to $150 say - and I'm prepared to put up with the limitations of free software such as the speed-crippled Modelsim HDL simulator. -- Dave Farrance
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