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Messages from 115450

Article: 115450
Subject: Re: question about DCM in virtex5: fails the maximum period check
From: "Peter Alfke" <alfke@sbcglobal.net>
Date: 11 Feb 2007 14:11:54 -0800
Links: << >>  << T >>  << A >>
You should not drive a DVM with 20 MHz, but you have many
alternatives:

Use two DCMs, one to divide 100 MHz into 20 MHz,
the other one to convert 100 MHz into 60 MHz.
 (Simultaneously divide by 5 and multiply by 3)

Or, if you worry about phase coherency:
Use one DCM to convert 100 MHz into 60 MHz,
use a counter or a second DCM to divide 60 MHz into 20 MHz.
Peter Alfke
===========


On Feb 11, 10:59 am, "cathy" <h...@njit.edu> wrote:
> Hello, all
>
> I simulate my design in modelsim and it works fine. But when I put it
> on board, the result it wrong. I noticed the following warning in
> the .mrp file complaining about DCM and I don't know what it will
> affect the result.
>
> The system uses a DCM with "PARAMETER C_CLKDV_DIVIDE = 5.000000" to
> generated a 20Mhz signal from the input clk pin (100MHz in ML501
> xilinx board) and work as the master clock
> for microblaze.  A coprocessor is connected with microblaze and part
> of the design needs a syncronized 3x clock signals. So I used a DCM to
> generated the 3 times clock over the master clock. But when I do the
> implementation, the following warning is given:
>
> My question is:
> 1, will the mean that the syncronized 3x clock generation failed?
> Then why it just a warning, but not error?
> 2, What does it mean and how can I avoid it?
>
> Thanks a lot,
> Cathy
>
> --------------------------------------------------------------------------- -----------------
> WARNING:Timing:3234 - Timing Constraint
>    "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
>    TS_sys_clk_pin * 5 HIGH 50%"
>     fails the maximum period check for input clock
>    MB0DLMBCntrl_BRAM_PORT_BRAM_Clk to DCM
>    ...../dcm3_inst/DCM_INST because the period
>    constraint value (50000 ps) exceeds the maximum internal period
> limit of
>    20001 ps.   Please reduce the period of the constraint to remove
> this timing
>    failure.
> WARNING:Timing:3236 - Timing Constraint
>    "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
>    TS_sys_clk_pin * 5 HIGH 50%"
>     fails the maximum period check for output clock
>   ..../dcm3_inst/CLKFX_BUF from DCM
>   ....t/dcm3_inst/DCM_INST because the period
>    constraint value (16666 ps) exceeds the maximum internal period
> limit of
>    10001 ps.   Please reduce the period of the constraint to remove
> this timing
>    failure.
> WARNING:Timing:3236 - Timing Constraint
>    "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
>    TS_sys_clk_pin * 5 HIGH 50%"
>     fails the maximum period check for output clock
>    .../dcm3_inst/CLK0_BUF from DCM
>   .../dcm3_inst/DCM_INST because the period
>    constraint value (50000 ps) exceeds the maximum internal period
> limit of
>    31251 ps.   Please reduce the period of the constraint to remove
> this timing
>    failure.
> WARNING:Timing:3234 - Timing Constraint
>    "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
>    TS_sys_clk_pin * 5 HIGH 50%"
>     fails the maximum period check for input clock
>    MB0DLMBCntrl_BRAM_PORT_BRAM_Clk to DCM
>    ...../dcm3_inst/DCM_INST because the period
>    constraint value (50000 ps) exceeds the maximum internal period
> limit of
>    20001 ps.   Please reduce the period of the constraint to remove
> this timing
>    failure.
> WARNING:Timing:3236 - Timing Constraint
>    "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
>    TS_sys_clk_pin * 5 HIGH 50%"
>     fails the maximum period check for output clock
>    ....t/dcm3_inst/CLKFX_BUF from DCM
>    ..../dcm3_inst/DCM_INST because the period
>    constraint value (16666 ps) exceeds the maximum internal period
> limit of
>    10001 ps.   Please reduce the period of the constraint to remove
> this timing
>    failure.
> WARNING:Timing:3236 - Timing Constraint
>    "TS_dcm_0_dcm_0_CLKDV_BUF = PERIOD TIMEGRP "dcm_0_dcm_0_CLKDV_BUF"
>    TS_sys_clk_pin * 5 HIGH 50%"
>     fails the maximum period check for output clock
>    ..../dcm3_inst/CLK0_BUF from DCM
>    ..../dcm3_inst/DCM_INST because the period
>    constraint value (50000 ps) exceeds the maximum internal period
> limit of
>    31251 ps.   Please reduce the period of the constraint to remove
> this timing
>    failure.K0_BUF from DCM
> ..../dcm3_inst/DCM_INST because the period
>    constraint value (50000 ps) exceeds the maximum internal period
> limit of
>    31251 ps.   Please reduce the period of the constraint to remove
> this timing
>    failure.



Article: 115451
Subject: Re: CLOCK GENERATOR
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Mon, 12 Feb 2007 11:27:23 +1300
Links: << >>  << T >>  << A >>
Peter Alfke wrote:
> On Feb 11, 9:21 am, "mahdi" <sagha...@gmail.com> wrote:
> 
>>Hi every body
>>I want to creat a VHDL code in order to generate 576 clocks.
>>The range of clocks frequency is [3 kHz to 75 kHz] and each of them
>>has 125 Hz frequency difference.
>>Can any body help me?I would appreciate it.
> 
> 
> Unless you use an analog PLL you will have some output jitter.
> Let's assume you can tolerate 4 ns of jitter ( one part in 3000 at
> your top frequency.)
> Then you build a 20 bit binary accumulator, continuously add the
> desired multiple of 125 Hz (i.e. the value between 24 and 600, but
> expressed in binary) to the LSB end of the accumulator.
> The MSB of the accumulator is your desired output frequency, provided
> you clock the accumulator with a clock frequency of 250 Hz times
> 2exp20, which is 262.144 MHz, a reasonable clock frequency which
> maximizes the jitter to less than 4 ns.
> If you modify the accumulator to be decimal, you can use a more
> convenient even clock frequency. Food for thought!
> This technique is called Direct Digital Synthesis, or DDS.
> Peter Alfke

Another alternative, is to search for Binary rate multiplier.

These devices are ideal for Hz-linear frequency generation,
you target 125Hz multiples, and as Peter says, choose N= 24..600 of 
that, so you need a 10 bit rate multiplier (can be binary, or decimal) 
and a post-scaler.
The post scaler reduces the jitter, so taking the 4ns example, that's
~250MHz of input clock. Peter's 262.144Mhz with a binary N/1024 RM, and 
/2048 (2^11) postscaler. or 256.00Mhz, if you use a decimal N/1000 RM, 
and a /2048 postscaler.
Modern FPGAs are good at adding, but I think the simpler structure of
the Rate Multiplier will out-speed the adder.
Not sure which would give lowest power ?

-jg




Article: 115452
Subject: Re: chipscope + mdm with microblaze ..
From: "motty" <mottoblatto@yahoo.com>
Date: 11 Feb 2007 15:49:16 -0800
Links: << >>  << T >>  << A >>
You should be able to pass the correct value for that parameter where
you instantiate the ILA.  However, you didn't say whether you are
using the core inserter or genrating the ICON and ILA and
instantiating them is the design.  My suggestion will work for the
later.



Article: 115453
Subject: Re: FPGA configuration direct from PLX
From: Peter Wallace <pcw@karpy.com>
Date: Sun, 11 Feb 2007 18:21:57 -0800
Links: << >>  << T >>  << A >>
On Sun, 11 Feb 2007 12:58:20 -0800, jim2345 wrote:

> Hi,
> 
> My apologies if this has been covered elsewhere - I did look!
> 
> I am trying to configure a Virtex 4 FPGA from a PLX 9656 using the two
> Useri/o pins in SelectMAP8 mode.
> I can use one to monitor the DONE bit and one to drive the RDWR line. My
> problem is I am not sure how to generate the CCLK to the FPGA so the
> config data is latched correctly,
> 
> anybody tried this?
> 
> thanks, jim
 
What we do is this: (with 9054. 9056 is probably similar)

CCLK <= Local Bus Clock
/CS from /DEN
Done and /PGM from Userio bits
RD/WR has pulldown

Peter Wallace

Article: 115454
Subject: Weird problem with WP 9.1sp1 and XC95144XL
From: Gavin Melville <gavin.melville@acclipse.co.nz>
Date: Mon, 12 Feb 2007 15:42:22 +1300
Links: << >>  << T >>  << A >>
Hi,

I've got a really strange problem with a XC95144XL.   It's a simple
design, all schematic based, and the device is not behaving -- but
only sort of.  Pins that are unused are turning into weak outputs,
some outputs work, and other don't (they may be high or low).   I have
data buses with 6 out of 8 pins working.   Change something and
recompile, reload and the results will be different eg. same data bus
but now 5 pins work correctly and 3 are high or low.  Most of the
internal logic seems to be working OK -- this only seems to affect IO
pins.

I've checked:

All pins (this is a TQ100 if that matters), including VCC/GND.
A few pins ar "fast", most are not, and the 3.3 V supply looks fine.
The download from a Parallel IV cable is verifyable, and repeated
downloads work (or fail to work) the same.
All the Fitter / Placer warnings make sense.
The equations in the reports are all correct.

If I add some unneeded logic ie. add a counter, clock it and feed one
output to an unused pin then the symptoms change.

Yes -- I do have it setup for the correct device.

Any bright ideas (or even some really silly ones)

While I hopefully wait for those I'm downloading 8.2 again.....


--

TIA,
Gavin Melville
gavin.melville@acclipse.co.nz

Article: 115455
Subject: Re: 1 Gbps - state of the art?
From: "Joel Kolstad" <JKolstad71HatesSpam@Yahoo.Com>
Date: Sun, 11 Feb 2007 19:37:50 -0800
Links: << >>  << T >>  << A >>
"Frithiof Andreas Jensen" <frithiof.jensen@die_spammer_die.ericsson.com> 
wrote in message news:epq3lk$415$1@news.al.sw.ericsson.se...
> If you can get the physical size of the circuit well below one wavelength 
> then
> things becomes "simply" DC again (Well worth doing if you, say, happen to 
> be
> building a RADAR front-end).

Yes, certainly... this is why Jim sometimes seems to have an easier job than 
those of us doing board-level design. :-)  I was quite humbled once to learn 
that a ~4"x10" PCB was having *significant* distributed behavior even down 
at HF (30MHz), but after adding up all the trace lengths it became clear 
that I had hit something over a quarter wavelength... oops!

I do remember reading how IC design generally uses lossy enough metals that 
after the "lumped" approximation no longer becomes valid, switching to an RC 
"transmission line" model is generally used, whereas with board-level design 
usually LC is often most appropriate at first.  (Eventually everything is 
RLC, of course, or just true transmission lines if you have a simulator that 
can deal with them -- SPICE sometimes has difficulty with lossy transmission 
lines).

---Joel



Article: 115456
Subject: Re: Weird problem with WP 9.1sp1 and XC95144XL
From: Jim Granville <no.spam@designtools.maps.co.nz>
Date: Mon, 12 Feb 2007 17:09:30 +1300
Links: << >>  << T >>  << A >>
Gavin Melville wrote:
> Hi,
> 
> I've got a really strange problem with a XC95144XL.   It's a simple
> design, all schematic based, and the device is not behaving -- but
> only sort of.  Pins that are unused are turning into weak outputs,
> some outputs work, and other don't (they may be high or low).   I have
> data buses with 6 out of 8 pins working.   Change something and
> recompile, reload and the results will be different eg. same data bus
> but now 5 pins work correctly and 3 are high or low.  Most of the
> internal logic seems to be working OK -- this only seems to affect IO
> pins.
> 
> I've checked:
> 
> All pins (this is a TQ100 if that matters), including VCC/GND.
> A few pins ar "fast", most are not, and the 3.3 V supply looks fine.
> The download from a Parallel IV cable is verifyable, and repeated
> downloads work (or fail to work) the same.
> All the Fitter / Placer warnings make sense.
> The equations in the reports are all correct.
> 
> If I add some unneeded logic ie. add a counter, clock it and feed one
> output to an unused pin then the symptoms change.
> 
> Yes -- I do have it setup for the correct device.
> 
> Any bright ideas (or even some really silly ones)

If you have an older design iteration archived, you could download that 
to check all the hardware is OK ?

You have checked the fitter pin-report to make sure it is not
moving pins about ?

There have been other postings here about Xilinx CPLD flows,
which suggest their PLD regression testing is, shall we say, "Casual".

-jg



Article: 115457
Subject: Re: ModelSim - Do Files
From: backhus <nix@nirgends.xyz>
Date: Mon, 12 Feb 2007 08:37:39 +0100
Links: << >>  << T >>  << A >>
Hi Pete,
the do-file generated by ise-pn is called *.fdo. There's another one 
called *.udo  (read: YOU-DO  :-) ) which will be called from the *.fdo file.
Just put some lines like

do my_waveform_format.do

etc. into that file. once it exists, it will not be overwrittten by 
ise-pn anymore.

Take a look into the *.fdo file to see when it is called, and what 
happens before and after.

The even better way is to rename the *.fdo file. (e.g. mysim.do)
Now you can start modelsim separately and call that file and modify it 
to your needs. As long as you don't add new files to your project you 
can even do changes to your vhdl or verilog sources if you need to and 
still use the same script for simulation again and again without ever 
leaving modelsim or need to have the ise tools running.

As long as the files are readable ASCII, use the magical powers of your 
commandline and text editor. :-)

Have a nice simulation
   Eilert


pete o. schrieb:
> Hopefully this won't have to be a lesson in Tcl. Here is my problem. I
> am using ModelSim
> with Xilinx ISE. I will make a simulation and arrange the signals in
> the order I would like them.
> If you hit "File" and then "Save" a box pops up asking "Save waveform
> formats?" and then it lists
> the path to the do file. I click OK and expect the waveform formats to
> be saved, and they are not.
> The reason they are not is that every time you re-run the simulation
> by clicking "Simulate Behavioral
> Model" an automatic do file is used and the waveforms revert to the
> default order. If you highlight
> "Simulate Behavioral Model" and hit "properties" there is an option to
> use a custom do file. If I try
> that I get to the "VSIM" prompt, but no luck after that. I assume the
> "automatic" option does a
> bunch of stuff for you. I'm guessing there is a command or set of
> commands that will allow
> you to run your simulations without making the waveform go back to the
> default order.
> Can someone help me with this? BTW, what if you wanted to have
> multiple do files?
> Would the solution be the same?
>                                              Thanks
> 

Article: 115458
Subject: Re: chipscope + mdm with microblaze ..
From: me_2003@walla.co.il
Date: 12 Feb 2007 00:39:42 -0800
Links: << >>  << T >>  << A >>
On Feb 12, 1:49 am, "motty" <mottobla...@yahoo.com> wrote:
> You should be able to pass the correct value for that parameter where
> you instantiate the ILA.  However, you didn't say whether you are
> using the core inserter or genrating the ICON and ILA and
> instantiating them is the design.  My suggestion will work for the
> later.

Hi motty,

I'm using the core inserter - its just more convenient that way.
Is there a way to pass this parameter when using the core inserter ?
Thanks, Mordehay.


Article: 115459
Subject: Re: generating VHDL code from Matlab code for DSP - wavelet image compression
From: Martin Thompson <martin.j.thompson@trw.com>
Date: Mon, 12 Feb 2007 08:53:02 +0000
Links: << >>  << T >>  << A >>
"EEngineer" <maricic@gmail.com> writes:

> On Feb 8, 4:40 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>> "EEngineer" <mari...@gmail.com> writes:
>> > I am interested in image processing of 128x128 image using wavelet
>> > transform compression, 12 bits per pixel, monochrome.
>>
>> At what sort of frame rate?
>>
>> Cheers,
>> Martin
>>
>> --
>> martin.j.thomp...@trw.com
>> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://www.conekt.net/electronics.html
>
> Frame rate expected is 30fps.
>

That doesn't terribly fast for that small size of image, only 0.5M
pixels/sec.  You can get a lot done in an FPGA in the length of time
one pixel takes to comes along (assuming they're evenly spread of the
time of course!).  

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

   

Article: 115460
Subject: Problem with floating inputs on LVDS ports
From: Magne Munkejord <Magne.Munkejord@student.uib.no>
Date: Mon, 12 Feb 2007 10:26:11 +0100
Links: << >>  << T >>  << A >>
Hello,

I have a design with several LVDS transceivers. The design works well 
when all ports are connected but once some ports are unconnected I start 
receiving garbage from the floating inputs. I use the IBUFDS primitives 
with "DIFFTERM = TRUE" on a Viretx4 LX chip for input buffers. I have 
tried to use pullup- and pulldown constraints from Xilinx ISE 
constraints editor but then I get this warning from ISE:

WARNING:PhysDesignRules:732 - Unexpected differential configuration for 
comp serial_in_lvds_N<1>/serial_in_lvds_N<1>. Adding a pullup, pulldown, 
or keeper to a differential IO can create signal integrity problems and 
can violate specifications.

Some ports are still giving my garbage when they are unconnected.

If anyone have any suggestions on how to handle unconnected ports please 
let me know. Thank you!

Magne

Article: 115461
Subject: Picobalze in the FPGA
From: "Himlam8484" <creativeperson8584@gmail.com>
Date: 12 Feb 2007 02:22:09 -0800
Links: << >>  << T >>  << A >>
Hi people,


i am a new person in the FPGA field. I have just made something with
IC from Xilinx( just make a FPGA'sboard at home). I know it worked
well when i check it with some program.I started to learn to control
it.It is said that There is a processor inside FPGA called Picoblaze.
I try to program for it, but i have no following thing.

I can program with the C software, then use a C compiler to compile it
then load into FPGA. I do not know if this process is Ok or not. i
also want to know when programming in C, Should i use the standard C
language or Use the  Picoblaze languge but written in C.

does everyone make me clear somethings mentioned above. I would like
clarify why i can asked the stupid questions. I did them because i am
only a hardware designer.

I am looking forward hearing from everbody soon,


Himlam8484


Article: 115462
Subject: Building Coaxial transmission line on PCB?
From: "Geronimo Stempovski" <geronimo.stempovski@arcor.de>
Date: Mon, 12 Feb 2007 12:10:43 +0100
Links: << >>  << T >>  << A >>
I think transmitting high-speed signals is very easy when you have a 
360-degree ground reference, round conductors,
and no other nearby signals like in coaxial cables. My aim is to design PCB 
tracks as much like a coaxial cable as
possible. Anyone tried this before? Is it possible with regular FR4, anyway? 
Thanks for your help.

Gero 



Article: 115463
Subject: Re: Weird problem with WP 9.1sp1 and XC95144XL
From: "Benjamin Todd" <benjamin.toddREMOVEALLCAPITALS@cernREMOVEALLCAPITALS.ch>
Date: Mon, 12 Feb 2007 12:23:11 +0100
Links: << >>  << T >>  << A >>
I remember in one of the previous releases of ISE where the JEDEC file 
creator was completely wrong for the XC9500. It inverted all the outputs. 
Makes CPLD design very challenging when you start questioning the tools not 
the design.
Ben

"Jim Granville" <no.spam@designtools.maps.co.nz> wrote in message 
news:45cfe7fc$1@clear.net.nz...
> Gavin Melville wrote:
>> Hi,
>>
>> I've got a really strange problem with a XC95144XL.   It's a simple
>> design, all schematic based, and the device is not behaving -- but
>> only sort of.  Pins that are unused are turning into weak outputs,
>> some outputs work, and other don't (they may be high or low).   I have
>> data buses with 6 out of 8 pins working.   Change something and
>> recompile, reload and the results will be different eg. same data bus
>> but now 5 pins work correctly and 3 are high or low.  Most of the
>> internal logic seems to be working OK -- this only seems to affect IO
>> pins.
>>
>> I've checked:
>>
>> All pins (this is a TQ100 if that matters), including VCC/GND.
>> A few pins ar "fast", most are not, and the 3.3 V supply looks fine.
>> The download from a Parallel IV cable is verifyable, and repeated
>> downloads work (or fail to work) the same.
>> All the Fitter / Placer warnings make sense.
>> The equations in the reports are all correct.
>>
>> If I add some unneeded logic ie. add a counter, clock it and feed one
>> output to an unused pin then the symptoms change.
>>
>> Yes -- I do have it setup for the correct device.
>>
>> Any bright ideas (or even some really silly ones)
>
> If you have an older design iteration archived, you could download that to 
> check all the hardware is OK ?
>
> You have checked the fitter pin-report to make sure it is not
> moving pins about ?
>
> There have been other postings here about Xilinx CPLD flows,
> which suggest their PLD regression testing is, shall we say, "Casual".
>
> -jg
>
> 



Article: 115464
Subject: Re: NGDBuild error
From: Sean Durkin <news_feb07@durkin.de>
Date: Mon, 12 Feb 2007 12:44:19 +0100
Links: << >>  << T >>  << A >>
quad wrote:
> Hello
> I'm working on Xilinx virtex II Pro FPGA kit.I generated netlist for
> OR gate using JHDL, with a1 and a2 being inputs, and op being the
> output.
> I also created the following User constraint file: (not sure if the
> given constraints are right!)
> 
>                            NET "a1" LOC="AC4";
>                            NET "a2" LOC="AC3";
>                            NET "op" LOC="AA6";
> 
> Using Xilinx ISE, i gave the command: (i'm particular abt not using
> the GUI, as i need to call the cmds programmatically)
>                         ngdbuild -p xc2vp30-ff896 -uc or_gate.ucf
> or_gate.edn
> 
> Here i get the following warning:
> WARNING:NgdBuild:483 - Attribute "LOC" on "op" is on the wrong type of
> object.
This is not an error, this is more or less "normal". It just tells you
that you can't assign an IO standard to a net, since a net is something
internal to the FPGA, and there are no IO standards there. You can only
assign an IO standard to something that connects to the outside world,
like an IO buffer.
But usually this isn't a problem, since the tools are smart enough to
follow the path of the net to the IO buffer and then attach the IO
standard attribute to that buffer.
So, this is nothing you need to worry about.

> ERROR:Pack:198 - NCD was not produced. All logic was removed from
> design. 
This on the other hand tells you that for some reason, your design
does not make sense to the tools at all so they removed all logic from
it. This is usually unrelated to the warnings above.
This usually happens when your design does not have any input/ouput
ports at all.
I'm not familiar with JHDL, but for VHDL designs, you have to either
manually instantiate IO buffers for your ports or tell the synthesis
tool to automatically do it for you. Either way, you need to have IO
buffers in the netlist you want to map and place and route.

So maybe if you instantiate an OBUF for "op" and IBUFs for "a1" and
"a2", that would fix the problem.

HTH,
Sean

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 115465
Subject: Re: Problem with floating inputs on LVDS ports
From: Sean Durkin <news_feb07@durkin.de>
Date: Mon, 12 Feb 2007 13:08:49 +0100
Links: << >>  << T >>  << A >>
Magne Munkejord wrote:
> Hello,
> 
> I have a design with several LVDS transceivers. The design works well
> when all ports are connected but once some ports are unconnected I start
> receiving garbage from the floating inputs.
Well, what do you expect them to give you? If they are not connected,
and neither pulled to ground nor to VCC, you get something in between,
and that depends on the temperature, humidity, moon phase, your karma,
whatever... That's why it's called "floating", because the input floats
somewhere in between. Most of the time somewhere around the middle
exactly where the decision threshold between 0 and 1 is, so sometimes
you get 0, other times you get 1, which translates to garbage.

As the warning states, if you do attach PULLUP or PULLDOWN primitives,
this might affect signal integrity. You might be OK with that, or it
might screw up your data, that's for you to decide. As you know, the
differential termination won't resolve the issue with the floating
inputs. So, pullups/-downs might be a solution, but only if it doesn't
affect signal integrity too much, which it seems to do in yout case
(since you still get garbage sometimes despite of the pullups).

> If anyone have any suggestions on how to handle unconnected ports please
> let me know.
Yes, ignore everything you get from floating inputs.

HTH,
Sean

-- 
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...

Article: 115466
Subject: Re: substracting a whole array of values at once
From: backhus <nix@nirgends.xyz>
Date: Mon, 12 Feb 2007 13:31:17 +0100
Links: << >>  << T >>  << A >>
Hi CMOS,
here's the solution you want:

Assume the two input matrices to be stored in two separate RAMs (e.G. 
Blockrams). Dual Ported, if necessary.

Connect a subtractor circuit to the DataOut of these RAMs.
The Output of that circuit is identical to the output of your Result-RAM

Now the result is virtually existent. If anyone has a doubt, just make a 
readout of the Result-RAM. The result will be there. :-)

Have a nice synthesis
   Eilert



Article: 115467
Subject: Re: Weird problem with WP 9.1sp1 and XC95144XL
From: gavin.melville@acclipse.co.nz
Date: 12 Feb 2007 04:48:43 -0800
Links: << >>  << T >>  << A >>
On Feb 12, 5:09 pm, Jim Granville <no.s...@designtools.maps.co.nz>
wrote:

> If you have an older design iteration archived, you could download that
> to check all the hardware is OK ?

Not for that device -- the design got too big.    The smaller one was
done with 8.2.03, and I've downloaded that now -- I'll try it
tomorrow.

> You have checked the fitter pin-report to make sure it is not
> moving pins about ?

Yes I have.   In some ways it's stranger than that -- take two pins
that should be a CPU databus (but are actually permanently low) -- if
I ground (internally) either one, the other works, however if I pull
either to VCC the other stays grounded.

> There have been other postings here about Xilinx CPLD flows,
> which suggest their PLD regression testing is, shall we say, "Casual".

As a user of about 10 different versions from DOS Viewlogic forward
I've never noticed that before.   I've always found the software to be
rock solid, well tested and clearly documented ;-)


Article: 115468
Subject: PETALINUX-COPY-AUTOCONFIG ERROR
From: "Pablo" <pbantunez@gmail.com>
Date: 12 Feb 2007 05:17:12 -0800
Links: << >>  << T >>  << A >>
Hello, I am trying to compile petalinux, but when I try to do
"petalinux-copy-autoconfig", an error appears. The problem is the
next:

24: function not found.

It seems like petalinux-copy-autoconfig does not detect system.xmp. I
have tried to put explicity but not.

Regards, Pablo


Article: 115469
Subject: Re: Building Coaxial transmission line on PCB?
From: John Fields <jfields@austininstruments.com>
Date: Mon, 12 Feb 2007 07:28:47 -0600
Links: << >>  << T >>  << A >>
On Mon, 12 Feb 2007 12:10:43 +0100, "Geronimo Stempovski"
<geronimo.stempovski@arcor.de> wrote:

>I think transmitting high-speed signals is very easy when you have a 
>360-degree ground reference, round conductors,
>and no other nearby signals like in coaxial cables. My aim is to design PCB 
>tracks as much like a coaxial cable as
>possible. Anyone tried this before? Is it possible with regular FR4, anyway? 
>Thanks for your help.

---
http://en.wikipedia.org/wiki/Microstrip


-- 
JF

Article: 115470
Subject: Master IPIF interface
From: vimes_ankh@yahoo.de
Date: 12 Feb 2007 05:30:52 -0800
Links: << >>  << T >>  << A >>
I have read the posts about setting up a master interface for the opb-
bus. But unfortunately I am not able to realize it, esp. the
connection to the 256MB RAM is very difficult for me to understand.

I would like to use the template of the wizard in edk 8.1, with which
I created a simple master-peripheral. There is a description of a 16-
byte flattened register which can be used for the master transaction.
For the very first start I just want to write only a one to the
beginning of my memory. Could anybody please post a very simple VHDL
Code, which uses this template and writes a number to the memory,
which starts in my case at 0x00000000.
Thank you very much.


Article: 115471
Subject: Re: Weird problem with WP 9.1sp1 and XC95144XL
From: Andreas Ehliar <ehliar@isy.liu.se>
Date: Mon, 12 Feb 2007 13:32:14 +0000 (UTC)
Links: << >>  << T >>  << A >>
On 2007-02-12, gavin.melville@acclipse.co.nz <gavin.melville@acclipse.co.nz> wrote:
> Yes I have.   In some ways it's stranger than that -- take two pins
> that should be a CPU databus (but are actually permanently low) -- if
> I ground (internally) either one, the other works, however if I pull
> either to VCC the other stays grounded.
>

The problem I had with a 9536 was "solved" by setting FSM extraction to
no in the Xilinx tool. I also got a report that enabling WYSIWYG mode
helped but I did not verify that myself since I had already gotten the
design to work.

/Andreas

Article: 115472
Subject: Re: Building Coaxial transmission line on PCB?
From: "Geronimo Stempovski" <geronimo.stempovski@arcor.de>
Date: Mon, 12 Feb 2007 14:39:30 +0100
Links: << >>  << T >>  << A >>

"John Fields" <jfields@austininstruments.com> schrieb im Newsbeitrag 
news:urq0t2533bdm5e2t2ui82b7fo8ppvsbqs8@4ax.com...
>
> http://en.wikipedia.org/wiki/Microstrip
>

Microstrip has absolutely nothing to do with the coaxial structure I had in 
mind. 



Article: 115473
Subject: Re: Building Coaxial transmission line on PCB?
From: "Meindert Sprang" <ms@NOJUNKcustomORSPAMware.nl>
Date: Mon, 12 Feb 2007 14:51:30 +0100
Links: << >>  << T >>  << A >>
"Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote in message
news:45d06e12$0$30327$9b4e6d93@newsspool1.arcor-online.net...
>
> "John Fields" <jfields@austininstruments.com> schrieb im Newsbeitrag
> news:urq0t2533bdm5e2t2ui82b7fo8ppvsbqs8@4ax.com...
> >
> > http://en.wikipedia.org/wiki/Microstrip
> >
>
> Microstrip has absolutely nothing to do with the coaxial structure I had
in
> mind.

But a microstrip will achieve the same results without the technical
difficulty of a real coaxial line. It is even easier to use
balanced/differential connections.

Meindert



Article: 115474
Subject: Re: Building Coaxial transmission line on PCB?
From: Fred Bloggs <nospam@nospam.com>
Date: Mon, 12 Feb 2007 13:56:37 GMT
Links: << >>  << T >>  << A >>

> I think transmitting high-speed signals is very easy when you have a 
> 360-degree ground reference, round conductors,
> and no other nearby signals like in coaxial cables. My aim is to design PCB 
> tracks as much like a coaxial cable as
> possible. Anyone tried this before? 

Nope- in all the decades of high speed PC circuit design, you are the 
first to think of it!

>Is it possible with regular FR4, anyway? 

Not even close, the "phase velocity," or speed to you, will be less than 
that of free space by a factor of 1/sqrt(epsilon-sub-r), so go figure.





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