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On Sat, 17 Feb 2007 08:17:07 -0800, John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> Gave us: >On Fri, 16 Feb 2007 19:52:36 -0800, MassiveProng ><MassiveProng@thebarattheendoftheuniverse.org> wrote: > >>On Sat, 17 Feb 2007 02:10:34 GMT, Vladimir Vassilevsky >><antispam_bogus@hotmail.com> Gave us: >> >>>Please find a quote or go take your pills. >> >> I got a pill for your ass, fuckhead. > >Still got that anal/fecal thing going, I see. I'm sure glad I wasn't >born with a fetish like that. Well, you're wrong, and that makes the fetish you were born with insisting on being stupid, and then showing your ass to the rest of the world.Article: 115726
On Sat, 17 Feb 2007 10:17:33 -0800, MassiveProng <MassiveProng@thebarattheendoftheuniverse.org> wrote: >On Sat, 17 Feb 2007 08:17:07 -0800, John Larkin ><jjlarkin@highNOTlandTHIStechnologyPART.com> Gave us: > >>On Fri, 16 Feb 2007 19:52:36 -0800, MassiveProng >><MassiveProng@thebarattheendoftheuniverse.org> wrote: >> >>>On Sat, 17 Feb 2007 02:10:34 GMT, Vladimir Vassilevsky >>><antispam_bogus@hotmail.com> Gave us: >>> >>>>Please find a quote or go take your pills. >>> >>> I got a pill for your ass, fuckhead. >> >>Still got that anal/fecal thing going, I see. I'm sure glad I wasn't >>born with a fetish like that. > > Well, you're wrong, and that makes the fetish you were born with >insisting on being stupid, and then showing your ass to the rest of >the world. I keep my posterior components discretely covered in public. And I'm as smart or a stupid as I was born, so am blameless in that respect. Luckily, the world seems to want my brand of stupidity, so it all works out. How is your brand of stupidity holding up? JohnArticle: 115727
bitsbytesandbugs@googlemail.com wrote: >Hi, >I'm very interested in starting to learn about fpgas. I tried finding >if there was anything about it at local colleges, but it seems a >little to specialised! Ouch.. ;) >I'm quite adept at software engineering (C++/ >Java etc...), but I haven't done any assembly, or worked very close >with any hardware in any sense (except for PC maintenance ;) >I've tried to do some rough research so that I would have some idea >before I asked questions, and it seems that there are two main >languages used (programming fpgas seems more popular than schematics >from what I've seen), Verilog and VHDL. From what I've seen from the >two languages, I think I'd prefer Verilog, but I can't work out if to >use Verilog 2005 and SystemVerilog? Is this again a matter of >perference or are there advantages and disadvantages to each? It seems >SystemVerilog has a few more features that aren't in Verilog, giving >it an edge over Verilog. If this is the case then perhaps >SystemVerilog is the best thing? >But it's here where things just disappear for me! I'm struggling with >where go to after this? I'm expecting a very steep learning curve, but >perhaps some resource (maybe a very good book on the subject for >complete newbies) giving some direction from here would be nice. *) Learn the language (grab a decent book and read at least one fully) *) View some code examples *) Play with the free tools (actel, xilinx, altera etc..) *) Learn some basic electronics. *) Buy a development board ($50-$150) *) Play with the board..Article: 115728
Recently I ordered a Nexys Spartan3-1000 / Cypress FX2 USB board from Digilent for work. It's been fun and I may well buy one personally, but like aways there are the suprises, the silly mistakes, and the 3 am still-doesn't-work-yets. First impression is consistent with what I saw on the web site - it's a nifty little board. The stock version has a smaller FPGA, but the S3-1000 is only $20 more (of course that meant I spent all night downloading a new Webpack) The new high density I/O connector finally has enough grounds (though confusingly the connector family is referred to as fx2 - not to be confused with the usb chip!) The mini-USB jack broke off the board within the first hour, and on examination is seems that the metal shield tabs never really soldered to the board. Not too hard to fix, though it took a ton of heat to get it soldered down, and even then it is more the solder I added to the board "encapsulating" the lugs than wetting them. It turns out the USB chip only has the 8 bits of port B connected to the FPGA, so FIFO transfers will have to be 8 bit. Probably not a problem, but one could wish for 16 bit. The other 8 bits include the JTAG signals, some control bits, and some unused bits. Digilent's Adept software can download .bit files using these. I was also able to program the board using an old digilent budget parallel cable from an s3kit. The expansion boards that plug in are spacious and worth getting more than one of. Unfortunately, plutting them in killed the jtag. Seeing the jtag is extended onto the expansion board I suspected long trace lengths and - it being Firday afternoon - simply chiseled them at the connector. That worked (wondering why there were 5 traces instead of 4) but turned out to be silly - turns out that plugging in the expansion board over-rides (via the 5th trace) a resistor controlling a gate shunting the expansion connector in other words, with the expansion connector plugged in, the jtag needs to have a shunt on the expansion board. Oh well, I can fix the expansion cards easily enough in the unlikely event I ever need JTAG out there. I then embarked on a hacking binge trying to download Cypress firmware and/or program the FPGA by using libusb on windows. 24 hours later, both work, via modified versions of the XUP & XC3SProg projects. Some discoveries: - at least under windows, must call usb_set_configuration() before usb_claim_interface(), had to modify the programs accordingly - for some reason, even building with MinGW g++ I get a reliance on cygwin1.dll - Digilent put a VID/PID eeprom on the board. Can modify the software to look for that VID/PID, or I finally just chiseled the trace across JP2 and am back to talking to cypress default VID/PID. I plan to install the jumper pins so I can quickly switch between compatability with the Digilent ADEPT software vs. homegrown efforts, and leverage the difference in identity to avoid any conflicts in having both digilent and libusb drivers installed on the computer. - I modified XUP and it's X3SProg ioxusb.cpp to use the Nexys jtag pin assignments to port PD instead of those of the s3ekit or usb programming cable it was written for. - PD6 controls a gate which puts the USB chip in the JTAG path. - PD7 controls the voltage regulator for the rest of the board. HOWEVER, the FPGA will run (via the protection diodes I assume) off the JTAG signals if you leave them driven with this shut down. I added a new command (0xff) to the xup <->firmware interface that tristates all of the jtag signals when configuration is done to avoid this. This also re-enables the jtag header on the board for other programming methods. My hacked up xup and XC3Sprog are a bit messy right now, but I may see about trying to contribute at least a description of the changes back to their authors. Of course I'm still not doing anything _useful_ with the board... but that may wait for Monday.Article: 115729
On Sat, 17 Feb 2007 08:34:30 -0800, Austin <austin@xilinx.com> wrote: >ricky, > >Peter and I take this issue of pricing and availability quite seriously. > >We have begun discussions on the issue. > >If you think you are upset by this, try to place yourselves in the shoes >of the hundreds of hardware ICDES folks, and hundreds of software folks, >and hundreds of production test and characterization engineers...you get >the picture. > >I went to some of the other nominee's websites, and on one, I could: >order a sample, order parts, have a representative contact me (the >buttons I could click on). 10K pricing was listed. I think there is >significant room for improvement here. I've said it before - not about Xilinx but about distributors; however it applies equally well to the online store: you'll know the store wants to help the small guy when you see a PayPal button... - BrianArticle: 115730
Some things here http://www.enterpoint.co.uk/techitips/techitips_useful_things.html that might held starting you off. If you want development boards then we have those too. For the must have cheaper addicts out there we have a special version of one of our Craignell modules coming that will support a power jack and arguably be the cheapest FPGA development board in the market. It should give the CPLD boards serious competition in price along with the 5V tolerance/CMOS compatability Craignell modules already offer. John Adair Enterpoint Ltd. - Home of Craignell.The Smallest Spartan-3E Development Board. On 16 Feb, 22:22, bitsbytesandb...@googlemail.com wrote: > Hi, > > I'm very interested in starting to learn about fpgas. I tried finding > if there was anything about it at local colleges, but it seems a > little to specialised! I'm quite adept at software engineering (C++/ > Java etc...), but I haven't done any assembly, or worked very close > with any hardware in any sense (except for PC maintenance ;) > > I've tried to do some rough research so that I would have some idea > before I asked questions, and it seems that there are two main > languages used (programming fpgas seems more popular than schematics > from what I've seen), Verilog and VHDL. From what I've seen from the > two languages, I think I'd prefer Verilog, but I can't work out if to > use Verilog 2005 and SystemVerilog? Is this again a matter of > perference or are there advantages and disadvantages to each? It seems > SystemVerilog has a few more features that aren't in Verilog, giving > it an edge over Verilog. If this is the case then perhaps > SystemVerilog is the best thing? > > But it's here where things just disappear for me! I'm struggling with > where go to after this? I'm expecting a very steep learning curve, but > perhaps some resource (maybe a very good book on the subject for > complete newbies) giving some direction from here would be nice. > > Thanks! :)Article: 115731
Jim Granville <no.spam@designtools.maps.co.nz> wrote: >Peter Alfke wrote: > >> Do you like Virtex-5 ? Then please vote for it... >> >> The editors of Electronic Design News think Virtex-5 is an innovative >> product; >> they have nominated for their 17th Annual EDN Innovation Awards: >> >> the Xilinx Virtex-5 Design Team for "Innovator of the Year," and >> >> the Virtex-5 LXT platform for "Innovation of the Year" (in the >> Digital ICs category) >> >> EDN is asking their readers to select the winner. >> >> · Learn more ( http://www.xilinx.com/prs_rls/2007/silicon_vir/ >> 0727_ednawards.htm ) >> >> · Vote now! ( www.edn.com/innovationballot.asp ) >> And confirm your vote as soon as you receive an automated email from >> EDN. >> >> Peter Alfke, Xilinx Applications, and proud of it ! > >I see a pretty small category : >( where do these guys get their candidates ? - could it be advertiser >revenue ? ) > They also miss a [none of the above] vote, so readers cannot indicate >if they agree with the shortlists. > >Digital ICs, programmable logic, and memory: > PEX 8548 PCI Express switch (PLX Technology) > MR2A16A MRAM (Freescale) > Virtex-5 LXT FPGAs (Xilinx) > >and since the award is for innovation : > >Adj. >1. innovative - ahead of the times; >2. innovative - being or producing something like nothing done or >experienced or created before; > >then the clear winner (by a large margin) is the MRAM. > >That's far closer to innovative than "another iteration in FPGAs" ? MRAM is not new either. Ramtron has been making similar parts for years. I think the PCI Express switch is the most innovative part because it links hardware like a real network. Since PCI express is a serial bus it can be extended by several feet, it might replace USB and firewire in the very near future. A PCI Express switch which has configurable ports is a key element for such a replacement. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 115732
Nico Coesel wrote: > Jim Granville <no.spam@designtools.maps.co.nz> wrote: >> >>then the clear winner (by a large margin) is the MRAM. >> >>That's far closer to innovative than "another iteration in FPGAs" ? > > > MRAM is not new either. Ramtron has been making similar parts for > years. Ramtron's devices are FRAM, which I believe use a different method. They have a volatile read, and smaller devices / slower speeds. Freescales devices are the first of a technology line. I also saw recent news from Hitachi/renesas that their Phase Change memory was in a real device http://home.businesswire.com/portal/site/google/index.jsp?ndmViewId=news_view&newsId=20070216005599&newsLang=en 20ns Tacc, and 416KB/s write speeds - no mention yet of joules/byte read, or yields, but a 4MBit/1.5V device is good to see. > I think the PCI Express switch is the most innovative part because it > links hardware like a real network. Since PCI express is a serial bus > it can be extended by several feet, it might replace USB and firewire > in the very near future. A PCI Express switch which has configurable > ports is a key element for such a replacement. So that moves Virtex-5 into last place ? -jgArticle: 115733
On Sat, 17 Feb 2007 07:37:06 -0500, CBFalconer <cbfalconer@yahoo.com> Gave us: >MassiveProng wrote: >> Vladimir Vassilevsky <antispam_bogus@hotmail.com> Gave us: >> >>> Please find a quote or go take your pills. >> >> I got a pill for your ass, fuckhead. > >This sort of foolish language will sooner or later get you PLONKed Like I give a fat flying fuck if you read my posts. From jaac@nospam-sanjaac.com Sun Feb 18 15:18:19 2007 Path: newssvr27.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!nntpserver.com!zeus.nntpserver.com!10.1.1.41.MISMATCH!pfilter-v0.1!not-for-mail From: Jaime Andres Aranguren Cardona <jaac@nospam-sanjaac.com> Organization: SanJaaC Electronics Subject: Theora vs. M-JPEG2000 Date: Sun, 18 Feb 2007 18:18:19 -0500 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2007.02.18.23.18.12.1877@nospam-sanjaac.com> Newsgroups: comp.dsp,comp.arch.fpga MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 13 NNTP-Posting-Date: 18 Feb 2007 22:24:30 GMT X-Complaints-To: abuse@teranews.com Xref: prodigy.net comp.dsp:225582 comp.arch.fpga:127177 Hello, Talking about video codecs, specifically Theora (www.theora.org) and M-JPEG2000, how do they compare in terms of compression ratio for a given quality? Being M-JPEG2000 based on still pictures and not taking advantage of interframe redundancies (from the very few I have read so far), is it viable for networking and storage applications? Kindest regards, JaaC -- Posted via a free Usenet account from http://www.teranews.comArticle: 115734
On 16 Feb., 23:45, "John_H" <newsgr...@johnhandwork.com> wrote: > Most synthesizers only support factor of 2 division. The XST manual (page > 479) states that arithmetic division is supported only for powers of 2 > > http://toolbox.xilinx.com/docsan/xilinx9/books/docs/xst/xst.pdf > > The FPGA hardware needed to implement dividers is pretty slow Hmm. It depends. I am annoyed that in XST for a two bit combinational divider I cannot write a <= b/3; At least division by a constant should be implemented by a synthesis tool. It is easy to implement for the tool vendor. That there might be better architectures is a design choice that the design can make anyway. The tool does not need to enforce that. Another example were it is very annoying: I am designing a protocol were the input clock is divided by k=2 or 5. All parameters (header length, etc.) can be expressed by formulas depending on k. Logic synthesis is pretty good today at figuring out that the formula is a function of a single bit. So this code: a <= 2 when mode='1' else 5; y <= 2365/a; z <= ... Has an area of 0. (Each bit of y will be equal to mode or its inverse and can be absorbed into the following luts). Nevertheless stupid tools force me to write muxes all over the place. Kolja SulimmaArticle: 115735
Thanks very much for your information everybody. It doesn't seem too daunting when you're surrounded by people who know what they're talking about! :) Re: Digilents tutorials, although the four they've got are fantastic, they seem a little sparse, also the remaining categories other than tutorials in the education section says "check back in the coming week", does anybody have any ideas on when this may be updated? John, thanks for the site, the UK makes it a bit more accessible for me. ;) Thanks again everybody. It is much appreciated.Article: 115736
We are currently proposing to do a FPGA based fm receiver using VHDL. We are newbies in the VHDL programming and we are currently reading books and journals about it. We are students in the Philippines. We would need some help in developing this project. We would appreciate it if someone would advise us in our thesis if we post some questions and if someone would give us ideas. Thanks in advance. You can contact me in these addresses rits11@gmail.com or heinrich_caagbay@yahoo.com. You can call me Rich.Article: 115737
Hi, What is the recommended way to get 4xClk from Clk? Xilinx recommends not to use cascaded DCMs for jitter & skew problems.. Then is there any recommended way to get this? Regards, JK From invalid@dont.spam Sun Feb 18 20:35:51 2007 Path: newssvr27.news.prodigy.net!newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!cyclone1.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny09.POSTED!933f7776!not-for-mail From: Phil Hays <invalid@dont.spam> Subject: Re: best way to get 4xclk User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2007.02.19.04.40.41.23825@dont.spam> Newsgroups: comp.arch.fpga References: <1171859230.153703.62390@a75g2000cwd.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 19 Date: Mon, 19 Feb 2007 04:35:51 GMT NNTP-Posting-Host: 71.112.133.239 X-Complaints-To: abuse@verizon.net X-Trace: trndny09 1171859751 71.112.133.239 (Sun, 18 Feb 2007 23:35:51 EST) NNTP-Posting-Date: Sun, 18 Feb 2007 23:35:51 EST Xref: prodigy.net comp.arch.fpga:127158 JK wrote: > Hi, > > What is the recommended way to get 4xClk from Clk? > > Xilinx recommends not to use cascaded DCMs for jitter & skew problems.. > > Then is there any recommended way to get this? What part? What input frequency? -- Phil Hays(Xilinx, but posting for myself)Article: 115738
Input frequecy is 50MHz. And required O/p frequency is 200 MHz. Regards, JK On Feb 19, 9:35 am, Phil Hays <inva...@dont.spam> wrote: > JK wrote: > > Hi, > > > What is the recommended way to get 4xClk from Clk? > > > Xilinx recommends not to use cascaded DCMs for jitter & skew problems.. > > > Then is there any recommended way to get this? > > What part? > > What input frequency? > > -- > Phil Hays(Xilinx, but posting for myself)Article: 115739
part is Virtex 2 Pro. Regards, JK On Feb 19, 9:35 am, Phil Hays <inva...@dont.spam> wrote: > JK wrote: > > Hi, > > > What is the recommended way to get 4xClk from Clk? > > > Xilinx recommends not to use cascaded DCMs for jitter & skew problems.. > > > Then is there any recommended way to get this? > > What part? > > What input frequency? > > -- > Phil Hays(Xilinx, but posting for myself)Article: 115740
rits11@gmail.com wrote: > We are currently proposing to do a FPGA based fm receiver using VHDL. > We are newbies in the VHDL programming and we are currently reading > books and journals about it. We are students in the Philippines. We > would need some help in developing this project. We would appreciate > it if someone would advise us in our thesis if we post some questions > and if someone would give us ideas. Thanks in advance. You can contact > me in these addresses rits11@gmail.com or heinrich_caagbay@yahoo.com. > You can call me Rich. > When you're done, you'll be impressive. You really have two problems that you need to solve. You'd like these to be separate, but they aren't. The two problems are: how to implement an FM receiver _at all_ in a digital system, and how to implement the digital algorithm on an FPGA using VHDL. I would suggest that you start by tackling the first problem without paying any attention to any difficulties that may crop up when you address the second. Once you get it working as an algorithm, then address how you're going to make it work on an FPGA (and be ready to make adjustments). I would suggest that you use SciLab or MatLab to do your algorithmic work, and test it in simulation. Were it me, I'd test it with vectors of real data, possibly ones that I had sampled with real ADCs with a real RF front-end using the real FPGA that I was going to use to do the demodulation. You can do a DSP algorithm in at least ten times fewer lines on one of these platforms than you can in an HDL. Using the mathematical packages to get the algorithm right will let you concentrate on the algorithm, not any peculiarities of your implementation. Once you get it working in SciLab, then figure out how to translate it into the HDL of your choice. Because you already understand the algorithm, know how it works, and know _that_ it works you'll be able to concentrate on the HDL implementation without distraction. When you run into problems with your algorithm not fitting well on an FPGA, use what you have learned about the algorithm and the FPGA to modify the algorithm _first_, re-simulate it and re-verify it. Then take your modified algorithm and proceed with implementing it. This way you'll _always_ be implementing a known-good algorithm on your FPGA, which can only be a good thing. -- Tim Wescott Wescott Design Services http://www.wescottdesign.com Posting from Google? See http://cfaj.freeshell.org/google/ "Applied Control Theory for Embedded Systems" came out in April. See details at http://www.wescottdesign.com/actfes/actfes.htmlArticle: 115741
Hi guys,
I am working in the FPGA's for the last one year. I never
doubted the working of the FPGA, but now i want to know whether there
is any procedure or methods available to test the FPGA. I mean whether
all the LUTs,mux,Carry chains,Switching Blocks etc are properly
working.
What is the procedure that FPGA manufactures doing to test it?.
>From my knowledge it is not a easy to test the FPGA completely.Am i
right?.
regards
subin
Article: 115742
Hi guys,
Our comany trying to buy a new board with V4lx200 or v5lx330.
>From the xilinx website it's recommended that 12GB memeory is required
to run MAP in ISE for these FPGAs. I would like to know any is
working in such boards. And what type of system will be needed for
this.
Does workstations like Dell Precesion 490 with 12GB ram will be
sufficient for this?
regards
subin
Article: 115743Use the frequency synthesis method: the Fx output gives you a multiplied and/or divided frequency. x4 is actually the default option, but you can also multiply by any integer up to 32 and simultaneously (!) divide by any integer up to 32. So you can take 50 MHz, multiply it by 29 and simultneously divide it by 17, to give you 82.352941 MHz, just to pick some really weird numbers. But you just want to multiply by4, which happens to be the default for the Fx output. Peter Alfke On Feb 18, 8:42 pm, "JK" <krishna.januman...@gmail.com> wrote: > part is Virtex 2 Pro. > > Regards, > JK > > On Feb 19, 9:35 am, Phil Hays <inva...@dont.spam> wrote: > > > JK wrote: > > > Hi, > > > > What is the recommended way to get 4xClk from Clk? > > > > Xilinx recommends not to use cascaded DCMs for jitter & skew problems.. > > > > Then is there any recommended way to get this? > > > What part? > > > What input frequency? > > > -- > > Phil Hays(Xilinx, but posting for myself)Article: 115744
Yes, comprehensive testing is very complicated, but we have one advantage: We can reconfigure the chips during testing, and we do that hundreds of times. That's why we joke that we actually sell "used FPGAs". Peter Alfke ============================== All FPGAs are tested 100% (or as close to 100% as we can get), On Feb 18, 9:10 pm, "subint" <subin...@gmail.com> wrote: > Hi guys, > I am working in the FPGA's for the last one year. I never > doubted the working of the FPGA, but now i want to know whether there > is any procedure or methods available to test the FPGA. I mean whether > all the LUTs,mux,Carry chains,Switching Blocks etc are properly > working. > What is the procedure that FPGA manufactures doing to test it?.>From my knowledge it is not a easy to test the FPGA completely.Am i > > right?. > regards > subinArticle: 115745
On Feb 19, 12:44 pm, Tim Wescott <t...@seemywebsite.com> wrote: > rit...@gmail.com wrote: > > We are currently proposing to do a FPGA based fm receiver using VHDL. > > We are newbies in the VHDL programming and we are currently reading > > books and journals about it. We are students in the Philippines. We > > would need some help in developing this project. We would appreciate > > it if someone would advise us in our thesis if we post some questions > > and if someone would give us ideas. Thanks in advance. You can contact > > me in these addresses rit...@gmail.com or heinrich_caag...@yahoo.com. > > You can call me Rich. > > When you're done, you'll be impressive. > > You really have two problems that you need to solve. You'd like these > to be separate, but they aren't. > > The two problems are: how to implement an FM receiver _at all_ in a > digital system, and how to implement the digital algorithm on an FPGA > using VHDL. > > I would suggest that you start by tackling the first problem without > paying any attention to any difficulties that may crop up when you > address the second. Once you get it working as an algorithm, then > address how you're going to make it work on an FPGA (and be ready to > make adjustments). > > I would suggest that you use SciLab or MatLab to do your algorithmic > work, and test it in simulation. Were it me, I'd test it with vectors > of real data, possibly ones that I had sampled with real ADCs with a > real RF front-end using the real FPGA that I was going to use to do the > demodulation. You can do a DSP algorithm in at least ten times fewer > lines on one of these platforms than you can in an HDL. Using the > mathematical packages to get the algorithm right will let you > concentrate on the algorithm, not any peculiarities of your implementation. > > Once you get it working in SciLab, then figure out how to translate it > into the HDL of your choice. Because you already understand the > algorithm, know how it works, and know _that_ it works you'll be able to > concentrate on the HDL implementation without distraction. When you run > into problems with your algorithm not fitting well on an FPGA, use what > you have learned about the algorithm and the FPGA to modify the > algorithm _first_, re-simulate it and re-verify it. Then take your > modified algorithm and proceed with implementing it. This way you'll > _always_ be implementing a known-good algorithm on your FPGA, which can > only be a good thing. > > -- > > Tim Wescott > Wescott Design Serviceshttp://www.wescottdesign.com > > Posting from Google? Seehttp://cfaj.freeshell.org/google/ > > "Applied Control Theory for Embedded Systems" came out in April. > See details athttp://www.wescottdesign.com/actfes/actfes.html Thank you sir, now we know how to deal with the future problems regarding the implementation using VHDL. At first we thought that we can already use VHDL without knowing Mathlab or Scilab but after reading your reply we considered the Mathlab and Scilab. Now we are planning to read books and practice using Mathlab or Scilab. We are unfortunate that in our curriculum we were not able to learn about these programs regarding the algorithms. Sir, do you have some tutorials or reading materials regarding Mathlab and Scilab so that we can use them in our thesis? Thank you again Mr. Tim Wescott for your post.Article: 115746
Thank you all for the timely support! Regards, JKArticle: 115747
Hi every one. I am newbie in FPGAs, although I can write VHDL. I already setup a copy of Cadence SPW 4.82 from my company to study FPGA myself. My OS is Scientific Linux 3.08 (clone of Redhat Enterprise 3.x). My purpose is to design in SPW by using fixed-pointed HDS, and generate to VHDL to FPGA board (etc. Xilinx). SPW can support co-simulation with C/C++ and VHDL, and I have some experiences with it. However, I am still in dark of how to generate and verify HDL code. My questions are: 1. Could you guys tell me what softwares should I have to simulate and verify VHDL in Linux? 2. Which FPGA board/component you recommend to build a decent system, for example wireless LAN 802.11n tranceiver? Thanks alot. ---sorry for my English ;)Article: 115748
Jon Elson wrote: > The distributors have warehouses full of non-RoHS compliant parts they > need to get > rid of before they can fill them back up with more stuff they won't be > able to move. The way I see it, they don't even have warehouses anymore in most cases. They forward your order to the chip manufacturer and put a new sticker on the package before they forward it to you. That's why you have lead times of 20 weeks and why it's so hard to get chips in decent quantities (i.e., not hundreds of thousands of parts), because that would require them to a) really stock some parts (because you can't bother the manufacturer with thousands of small orders for a handful of chips) and b) repackage them in the quantities ordered. And that's too much effort nowadays. They used to do it, and still do it for $1000 FPGAs, but I guess with the myriad of different packages, speed grades, RoHS/non-RoHS and so on, there's no way to stock nearly enough different parts... If you need things like cheap SDRAM-memory chips, you're screwed in most cases. Getting a few samples is OK, but after that it's buy 1000 or nothing. -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 115749
I have some very basic problems getting simple things to work on this platform. Is there a quirk of this product this i don't know about?? seem to have problems with counters and state machines..
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