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JK wrote:
> Hi Sean,
>
> Thank you for this info...
> So, In Virtex 4 to utilize max benift of these cores, we need to make
> reset - sync signal using Dual Flop synchronizers?
The problem is not only the reset signal itself, but the way it is
connected to your logic.
If you have something like this:
asynch_reset: PROCESS (clk, rst)
BEGIN
IF rst = '1' THEN
counter <= (others => '0');
ELSIF clk'event AND clk = '1' THEN
counter <= counter + 1;
END IF;
END PROCESS asynch_reset;
... you get a counter that can be reset at any time (even between clock
pulses), i.e. asynchronously. But it will only increment at a rising
clock edge.
Whereas if you write it like this:
synch_reset: PROCESS (clk)
BEGIN
IF clk'event AND clk = '1' THEN
IF rst = '1' THEN
counter <= (others => '0');
else
counter <= counter + '1';
END IF;
END IF;
END PROCESS synch_reset;
... you get a counter that can only be reset at a rising clock edge,
i.e. synchronously.
Now, in some cases, the two descriptions above can lead to totally
different synthesis results. The DSP48 hard macros in the Virtex4 for
example are designed for synchronous reset only. So if you have
asynchronous resets in your design, the synthesis tool might decide that
it cannot use a DSP48 in this case and instead build the counter out of
slice flip flops, which might be slower.
I don't know if that will have any effect on YOUR design, but it's worth
a try, and for Virtex4 and 5 it's generally a good idea to use
synchronous resets where possible.
Trying different parts from the same FPGA family will probably not help
much performance-wise, unless the FPGA is almost full and you're
switching to a bigger part.
--
My email address is only valid until the end of the month.
Try figuring out what the address is going to be after that...
Article: 115876On Feb 22, 11:35 am, "John_H" <newsgr...@johnhandwork.com> wrote: > "Peter Alfke" <a...@sbcglobal.net> wrote in message > > news:1172157421.210544.161220@q2g2000cwa.googlegroups.com... > > > On Feb 22, 5:06 am, "axr0284" <axr0...@yahoo.com> wrote: > >> Thanks for the answer everybody. It's a lot to take in for a newbie so > >> i'll probably have to do a little research on the different stuff in > >> John's reply but it's definitely a start. Thanks a lot, > >> Amish > > > Amish, > > you never told us the criticality of your timing detector. If you can > > tolerate an 8 ns detection error, then the interesting solution > > suggested by John is not required. But if timing is critical, it is a > > really superb solution. > > Peter Alfke > > I agree that the approach I suggested may be significant overkill. I > wouldn't suggest the approach for a newbie unless desperate for precision or > very confident in the ability to tackle a problem full of nuance. Many > seasoned engineers still don't design with the silicon target in mind, > producing quite functional but less than optimal code; often the ability to > retarget the code to a different family is justification enough to not think > at the silicon level. The tast I suggested - to show what precision could > be obtained - keeps the silicon at the forefront of most of the coding > decisions. > > With 2X the 125 MHz clock Peter suggested (without a DCM!) you get good > results without 2+ man-weeks of effort. If you could pull off the task I > suggested in 2 days, I'd graduate you far beyond newbie. If you're > interested in this type of technique for speed or precision, I'd suggest > reading XAPP 671 that has a delay structure similar to the ring oscillator > for high speed asynchronous data capture. > > - John_H I originally thought that timing would be critical but it would seem that the error would actually cause the signal to be stuck for a longer time which makes my life easier. 125 MHz is more than enough. I did really like John's solution and I will definitely keep it in mind if a problem requiring more precision comes up in the future. Thanks again, AmishArticle: 115877
NEC will exit the structured ASIC business http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=197008125 Is that 2 major players gone? How many more are there? - John_HArticle: 115878
John_H wrote: > NEC will exit the structured ASIC business > > http://www.eetimes.com/news/semi/showArticle.jhtml?articleID=197008125 > > Is that 2 major players gone? How many more are there? Carefull now, I can just feel Austin warming up .... :) -jg From dave@comteck.com Thu Feb 22 17:01:03 2007 Path: newsdbm04.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newshub.sdsu.edu!nx02.iad01.newshosting.com!newshosting.com!208.49.83.154.MISMATCH!uns-out.usenetserver.com!news.usenetserver.com!pc03.usenetserver.com!COMTECK.COM-a2kHrUvQQWlmc!not-for-mail From: Dave <dave@comteck.com> Subject: Re: Xilinx Platform Studio Evaluation Trial Expired (included in Spartan 3E Starter Kit) Date: Thu, 22 Feb 2007 20:01:03 -0500 User-Agent: Pan/0.14.2 (This is not a psychotic episode. It's a cleansing moment of clarity.) Message-Id: <pan.2007.02.23.01.00.51.661261@comteck.com> Newsgroups: comp.arch.fpga References: <1171023946.472850.59840@v33g2000cwv.googlegroups.com> <qhejoz9n87.fsf@ruckus.brouhaha.com> <ziggy-D2B0F4.06284922022007@news.isp.giganews.com> <erk5ga$ek41@cnn.xsj.xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit X-Complaints-To: abuse@usenetserver.com Organization: UseNetServer.com Lines: 13 X-Trace: 06d4345de3cf1e51d977311198 Xref: prodigy.net comp.arch.fpga:127309 On Thu, 22 Feb 2007 13:23:21 +0000, Ben Jones wrote: > EDK is an example of a "value add" product - you get accellerated design > time for processor-based SoC platforms, a whole bunch of peripheral IP, and > the MicroBlaze processor core as well. I would actually buy this if I just paid for it once. But having to pay $500 on a yearly basis just isn't feasible for me. I do this for a hobby and to keep at least some of my hardware knowledge. So, regretfully, I pass on the MicroBlaze and other IP. ~Dave~Article: 115879
Jim, I've said my piece. But thanks for thinking of me. AustinArticle: 115880
Hi everyone, I am newbie in FPGA; recently I decide to buy a FPGA board to study. I am considering two boards: 1. Virtex-4 MB (DS-KIT-4VLX60MB) with XC4VLX60 http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=DS-KIT-4VLX25MB&sGlobalNavPick=&sSecondaryNavPick= 2. Virtex-4 ML405 Embedded Platform (HW-V4-ML405-US) with XC4VFX20 http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.jsp?key=HW-V4-ML405-US My main target is to demonstrate some base-band demodulation systems (or part of it) such as Wireless LAN, and DSP. Easy-to-use and popular interface to PC and other board are also important. Several things that I am really confused here: -Price: Board 1 is cheaper. Correct me if I wrong, board 1 use standard RS-232 interface to console, while the kits from Xilinx using PC platform cable (adding ~140USD). -Performance: the different between LX and FX. Number of gates and slices in board 1 is larger than that in board 2. However, board 2 equips the embedded micro-processor, which may be interesting for studying and demonstrate. My feeling is that board 2 is just "a kit" and would be nice for studying and demo, while board 1 is more like "a development board". Please point out other things I should consider. I really need your opinions. I really appreciate that. Thanks in advance.Article: 115881
Austin wrote: > Jim, > > I've said my piece. Bummer, you've ruined my friday evening now :) > But thanks for thinking of me. I couldn't help it, right about the 3rd sentence of the press release, your name just popped into my head :) -jgArticle: 115882
No, it can't Göran "David" <pang.dudu.pang@hotmail.com> wrote in message news:1172159819.840074.274430@q2g2000cwa.googlegroups.com... > Hello, all: > > My question is: > > Can MicroBlaze and OPB run at one clock frequency and the OPB block > ram interface run at another? If it is possible, how can I realize it? > Can I change the BRAM_clk someway? > Or would you please refer me some useful documents about this > configuration? > > Thank you very much for your reply, > David >Article: 115883
On Feb 22, 10:54 pm, "Brad Smallridge" <bradsmallri...@dslextreme.com> wrote: > Tell us more. > > Are you using Xilinx? Do you have a dev board? > Are you using VHDL or Verilog > > In Xilinx you can use the Coregen wizard to generate > what they call an .XCO file, or something like that. > Input your clock frequency and click on the 2X output. > > "mahdi" <sagha...@gmail.com> wrote in message > > news:1172168667.047884.243590@a75g2000cwd.googlegroups.com... > > > Hi > > Can any body explain internal DCM and give me some information about > > it? > > Thank you Actually I'm using altra fpga(flex10k family).But I'm also interested in xilinx. And I'musing VHDL. Best wishes, MahdiArticle: 115884
On Feb 22, 9:34 pm, Ben Twijnstra <ben.twijns...@gmail.com> wrote: > mahdi wrote: > > Hi > > Is there a technique to 2x our input clock and as a general > > Is there a technique to create a clock with frequency of n*f_input_clk. > > (where n is a desired integer) > > Thank you > > With Xilinx, use a DCM. With Altera use an ALTPLL. Any other construct for > doubling a clock is very dependant on process, voltage and temperature, > i.e. the clock shape will change with voltage and temperature, and has a > wide spread between devices. > > Best regards, > > Ben Thanks Ben Can you explain ALTPLL. Actually I'm using altra fpga(flex10k family). Best wishes, MahdiArticle: 115885
Hi, I have a project based on MicroBlaze. Everything works fine, I debug software in SDK. But now I need to check in/out signals and transmission between IPs. So I add Chipscope ICON and ILA (I also tried with VIO) in EDK from IP Catalog (I also tried with Hardware/Debug Configuration). When I make Bitstream Generation it shows: ERROR:MDT - platgen failed with errors! I found something like that in xflow.log: "ERROR:MapLib:661 - LUT3 symbol "chipscope_icon_0/chipscope_icon_0/icon_inst/icon_1/u_icon/u_tdo_mux/no_lut6/ i4/fj/0/u_lut3" (output signal=chipscope_icon_0/chipscope_icon_0/icon_inst/u_icon/u_tdo_mux/no_lut6/i 4/t1_7) has input signal "chipscope_icon_0/control0<3>" which will be trimmed. See the trim report for details about why the input signal will become undriven." Thanks for any help, DominikArticle: 115886
Hi Everybody, I'm using a xc2vp4 FPGA from Xilinx which has 28 blocks of 18Kb (= 504 Kb = 63 KB) of BRAM. The problem is: using EDK is only possible to allocate a power of two size (in KB) for the BRAM !!! This means that I can only address 32KB of the 63KB available on FPGA... One possible (bad) solution to use all BRAM can be to create more BRAM controllers each one with a different size (32 + 16 + 8 + 4 + 2 + 1). The drawbacks of this approach in my opinion are: 1) Lot of logic used for all the controllers 2) Each code segment has to fit fine (to exploit the memory) in each bram. 3) If I have a code segment greater than 32KB there's no way to complete the design even if the FPGA has 63KB available... Nevertheless, EDK minimum BRAM size is 16KB !!!! So I can, at best, to use only 32 + 16 KB :( Any ideas to workaround this problem? Thanks! AndreaArticle: 115887
Sean Durkin schrieb: [D-FF with async reset] > ... you get a counter that can be reset at any time (even between clock > pulses), i.e. asynchronously. But it will only increment at a rising > clock edge. > > Whereas if you write it like this: ... [D-FF with sync reset] > ... you get a counter that can only be reset at a rising clock edge, > i.e. synchronously. > > Now, in some cases, the two descriptions above can lead to totally > different synthesis results. .. and totally different behavior. ;-) Synchronous resets are signals like any other signal (except that there is a big fanout to this signal but this is handled well by the synthesis tool). Asynchronous resets are special signals where signal skew is a big problem. One should use global signal buffers and global (dedicated) reset wires in FPGAs. Often they can be inferred using a primitive as mentioned in every manual of FPGAs. For performance problems I would suggest to read the timing report _very_ carefully and to try to understand where the critical path is. This includes looking into the netlist and being creative to have an imagination, about what signals the timing report talks. RalfArticle: 115888
mahdi schrieb: > Can you explain ALTPLL. It is a phase-locked loop for frequency multiplication. > Actually I'm using altra fpga(flex10k family). I am not sure, but AFAIK the ALTPLL is not included in this family. If you really need signal processing at the doubled clock rate (think twice about it!) then maybe pseudo dual-edge flipflops are a choice: <http://www.ralf-hildebrandt.de/publication/pdf_dff/pde_dff.pdf>. But I strongly recommend to use a faster oscillator and a clock divider for the other parts. RalfArticle: 115889
HI Every body, I hope well to help me in regards to my problem: I want to program a coding unit of video that is the one of estimation and movement compensation while using the language VHDL, I want well to have an outline defining the entries and gone out in order to facilitate me the comprehension, puique I am very beginning in this domain. thanks very muchArticle: 115890
I've been interested in using SystemVerilog for quite some time now I don't really know if the tool support is there yet. XST doesn't (yet?) support SystemVerilog so I tested Precision instead. Unfortunately it didn't seem to work that well. Some constructs were supported but I couldn't get interfaces to work reliably. Is there any tool available that does support SystemVerilog synthesis for Xilinx FPGAs today? I'm mainly interested in these features (for synthesis that is): 1. Interfaces (This is very high on my wishlist) 2. always_comb/always_ff 3. The logic net type (I really dislike the wire/reg confusion) /AndreasArticle: 115891
Thank you.Article: 115892
You should recalculate your BRAM needs. As some cores and microblaze itself may consume a few of the BRAM for fifos or cache. If you use chipscope, you'll need a bram for onchip debugging. Nonetheless, I wouldn't worry so much about the LUT logic consumed for controllers unless you running out of resources. The approach of combining controllers (32 + 16) in a contiguous memory space is correct. The BMM generated will recognize that memory regions are contiguous thus allowing data2mem to populate code segments that are larger than 32kB. Ofcourse, this requires atleast EDK 8.2 Andrea05 wrote: > Hi Everybody, > > I'm using a xc2vp4 FPGA from Xilinx which has 28 blocks of 18Kb (= 504 > Kb = 63 KB) of BRAM. > > The problem is: > using EDK is only possible to allocate a power of two size (in KB) for > the BRAM !!! > This means that I can only address 32KB of the 63KB available on > FPGA... > > One possible (bad) solution to use all BRAM can be to create more BRAM > controllers each one with a different size (32 + 16 + 8 + 4 + 2 + 1). > The drawbacks of this approach in my opinion are: > 1) Lot of logic used for all the controllers > 2) Each code segment has to fit fine (to exploit the memory) in each > bram. > 3) If I have a code segment greater than 32KB there's no way to > complete the design even if the FPGA has 63KB available... > > Nevertheless, EDK minimum BRAM size is 16KB !!!! So I can, at best, to > use only 32 + 16 KB :( > > Any ideas to workaround this problem? > > Thanks! > > Andrea >Article: 115893
Does anybody know of a good, --small--, development board with an ethernet port? What I'm really looking for is essentially a FPGA, on a very small PCB, with an ethernet port and power port/headers. Some extra pins brought out to headers would be handy, but are not essential. While I'm dreaming, it needs to be something I could communicate to from linux, so proprietary / windows-only ethernet drivers won't cut it. Xilinx is preferred, but I'm open to other platforms if a better solution exists. Cheap is good... how cheap depends on the size of the FPGA that I can get. Thanks for your suggestions... - chrisArticle: 115894
Synplify appears to support 2 and 3. I don't find reference to 1 (interfaces) in the v8.8 reference manual in my quick glance. I've been lackluster in pursuing System Verilog myself because of the synthesis/simulation support mismatch issues I had with Verilog2001; Synplify was up to speed long before Cadence. I've seen the System Verilog check box in SynplifyPro for a while but haven't gone there yet. Since it's been a while since the option first appeared, I would have thought interfaces - one of the more attractive features of System Verilog - would be in there already but the reference manual doesn't mention it. "Andreas Ehliar" <ehliar@isy.liu.se> wrote in message news:ern2na$s3t$1@news.lysator.liu.se... > I've been interested in using SystemVerilog for quite some > time now I don't really know if the tool support is there > yet. > > XST doesn't (yet?) support SystemVerilog so I tested > Precision instead. Unfortunately it didn't seem to work > that well. Some constructs were supported but I couldn't > get interfaces to work reliably. > > Is there any tool available that does support SystemVerilog > synthesis for Xilinx FPGAs today? > > I'm mainly interested in these features (for synthesis that is): > 1. Interfaces (This is very high on my wishlist) > 2. always_comb/always_ff > 3. The logic net type (I really dislike the wire/reg confusion) > > > /AndreasArticle: 115895
On 23 Feb, 18:08, Paulo Dutra <paulo.du...@NOSPAM.com> wrote: Hi Paulo, > You should recalculate your BRAM needs. As some cores and microblaze > itself may consume a few of the BRAM for fifos or cache. If you use > chipscope, you'll need a bram for onchip debugging. What do you exactly mean by that? I have a quite big program which use several 4x4 matrix. I would like to mantain Program and Data in BRAM to speed up the execution. > Nonetheless, I wouldn't worry so much about the LUT logic consumed for > controllers unless you running out of resources. You're right, this is only a minor issue. > The approach of combining controllers (32 + 16) in a contiguous memory > space is correct. Yes correct but (63 - (32 + 16)) KB still remain unsued! > The BMM generated will recognize that memory regions > are contiguous thus allowing data2mem to populate code segments that are > larger than 32kB. Ofcourse, this requires atleast EDK 8.2 Unfortunately I have EDK 7.1 :( Thanks for your hints, AndreaArticle: 115896
Ah! There it is. The Mini-module from Avnet. Spartan-3 3S400 and Virtex-4 FX12 flavors. Go to www.em.avnet.com, Products tab, Design Resource Center (right below the Products tab), look for Mini-module. "Designed as a complete system on a module, the Mini packages all the necessary functions needed for an embedded processor system, onto a tiny footprint slightly bigger than a stick of chewing gum." - John_H "Chris Murphy" <chrismurf@gmail.com> wrote in message news:1172251224.719699.314850@a75g2000cwd.googlegroups.com... > Does anybody know of a good, --small--, development board with an > ethernet port? What I'm really looking for is essentially a FPGA, on > a very small PCB, with an ethernet port and power port/headers. Some > extra pins brought out to headers would be handy, but are not > essential. While I'm dreaming, it needs to be something I could > communicate to from linux, so proprietary / windows-only ethernet > drivers won't cut it. > > Xilinx is preferred, but I'm open to other platforms if a better > solution exists. Cheap is good... how cheap depends on the size of > the FPGA that I can get. > > Thanks for your suggestions... > > - chrisArticle: 115897
> Actually I'm using altra fpga(flex10k family).But I'm also interested > in xilinx. Can't help you there. DCM's are usually hardware specific. And I never heard of Altra although flex10K sounds familiar. Brad Smallridge Ai VisionArticle: 115898
"Andreas Ehliar" <ehliar@isy.liu.se> wrote in message news:ern2na$s3t$1@news.lysator.liu.se... > I've been interested in using SystemVerilog for quite some > time now I don't really know if the tool support is there > yet. > > XST doesn't (yet?) support SystemVerilog so I tested > Precision instead. Unfortunately it didn't seem to work > that well. Some constructs were supported but I couldn't > get interfaces to work reliably. I would check again since SystemVerilog support is quite high on their development list (so I understand) and they are bringing out frequent updates (I just downloaded 2006a.112). Also if something doesn't work let them know, like all EDA vendors they want(need) feedback especially on new features. Personally, I wish they would spend the same amount of effort on VHDL2006.........:-( Hans www.ht-lab.com > > Is there any tool available that does support SystemVerilog > synthesis for Xilinx FPGAs today? > > I'm mainly interested in these features (for synthesis that is): > 1. Interfaces (This is very high on my wishlist) > 2. always_comb/always_ff > 3. The logic net type (I really dislike the wire/reg confusion) > > > /AndreasArticle: 115899
On 2007-02-23, HT-Lab <hans64@ht-lab.com> wrote: > > "Andreas Ehliar" <ehliar@isy.liu.se> wrote in message > news:ern2na$s3t$1@news.lysator.liu.se... >> I've been interested in using SystemVerilog for quite some >> time now I don't really know if the tool support is there >> yet. >> >> XST doesn't (yet?) support SystemVerilog so I tested >> Precision instead. Unfortunately it didn't seem to work >> that well. Some constructs were supported but I couldn't >> get interfaces to work reliably. > > I would check again since SystemVerilog support is quite high on their > development list (so I understand) and they are bringing out frequent > updates (I just downloaded 2006a.112). Also if something doesn't work let > them know, like all EDA vendors they want(need) feedback especially on new > features. > > Personally, I wish they would spend the same amount of effort on > VHDL2006.........:-( 2006a.112 is actually what I'm testing as well. Some interface constructs work and some doesn't but I came up with a workaround (I think): The following doesn't seem to work: myinterface intf0(); foo (.intf_slave(intf0)); bar (.intf_master(intf0)); In this case Precisioin claims that it has found a black-box for myinterface. However, the following seems to work: myinterface intf0(); foo (.intf_slave(intf0)); assign intf0.some_master_signal = something; And the following also seems to work: myinterface intf0(); foo (.intf_slave(intf0)); bar (.intf_master(intf0)); logic workaround_dummy; assign workaround_dummy = intf0.some_master_signal; So I guess I can continue experimenting with SystemVerilog as long as I add some dummy signal from the interface to persuade Precision to take a look at the interface specification even if no signals of the interface is actually used in the file. (This is only my initial analysis, I just got this to work so I can't say if more advanced interface constructs will work or not.) /Andreas
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Compare FPGA features and resources
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