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On Feb 20, 11:46 pm, "Peter Alfke" <a...@sbcglobal.net> wrote: > Vladimir, another approach would be to use a more modern device, like > the Virtex-4 LX25. > This is almost the smallest part in that family, but has twice as many > resources (>20 000 LUTs) than the XC2V1000, which -in its days- was > considered one of the larger devices in its family. Which is all well and pointless if he happens - as is likely to be the case - to be holding a development board with the old chip and not have a budget for a new one. > Evolution is very fast in our industry, and it may be wise to move to > a more modern family (Virtex-4 is about 3 years old) So how about giving away licences to the old full versions of the software for the obsolete parts... yeah, probably be a support headache though the webpacks are there already.Article: 115801
My writes take place at 60 Mhz & reads at 35 Mhz. The maxm memory freq is 120 Mhz. I require it for an ASIC design Thanks On Feb 20, 10:20 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > And I'll repeat the other questions: > > What is your operating frequency versus maximum memory frequency? > If you have a 50 MHz read/write clock and your memory can give you 300 MHz > performance, you can use a faster clock and time multiplex your writes and > reads. > Are you targeting a specific device? > If you don't know the device capabilities but have a specific FPGA or ASIC > in mind, perhaps you could get specific help from those who know your target > well. > > If this is just a homework problem - no specific device, no specific > frequency - be up front about it and you're more likely to get good help. > > - John_H > > "vlsifresher" <baj...@gmail.com> wrote in message > > news:1171986778.256284.152970@q2g2000cwa.googlegroups.com... > > > Hi John, > > > My SPRAM will have only one address.The DPRAM needs to be such that I > > will only write through portA & only read through port B. > > > On Feb 20, 6:28 am, John_H <newsgr...@johnhandwork.com> wrote: > >> vlsi_learner wrote: > >> > Hi, > > >> > Is there any way of implementing DPRAM from single port RAM's?(may be > >> > by connecting two SPRAM's) > > >> > Thanks > > >> Maybe. > > >> Do you have extra clock cycles available to do multiple reads and writes > >> in one memory and make it "look" like a mult-port memory? > > >> Is you SPRAM truly only one address? There are "pseudo" dual-port > >> memories and "true" dual port memories. A true dual port can be made > >> from 2 pseudo dual ports. > > >> So. What is the structure of your SPRAM? What DPRAM structure do you > >> want? What is your operating frequency versus maximum memory frequency? > >> Are you targeting a specific device?Article: 115802
I am developing an FPGA application which works in series with a main processor which is running an RTOS(VxWorks). Since my inputs and outputs are to and from that processor, should i be using any RTOS? Kindly clarify. thanks in advance. Regards Surya.Article: 115803
Hi While delivering an IP is it necessary to have all the outputs registered? what is the advantage from this?Article: 115804
MikeJ wrote: >>There is a motorola booklet describing a stereo graphic equalizer >>built with a 56001. That would probably have all the logic you >>would need to do what you want. > Sounds interesting. I don't suppose you have a link? Google is currently > failing me ... It is older than the web, so it might not be there. (Well, older than when the web started to get popular.) I might be able to find mine and scan it. -- glenArticle: 115805
<cs_posting@hotmail.com> wrote in message news:1172029404.087282.193620@a75g2000cwd.googlegroups.com... > On Feb 20, 8:53 am, "cpope" <cep...@nc.rr.com> wrote: > > > Unfortunately I only have low speed serial links so it woudl take about an > > hour to transfer the flash contents. > > > > So run them faster when downloading the code. > > Or use an additional link for this purpose. > > Remember, jtag is just a synchronous serial interface, with a mode > pin... there's no reason you can't get comparable throughput from a > simple function temporarily downloaded into your FPGA. In fact you > should be able to do better, as you could minimize the overhead. > I should have specified UART. Max I can get is 115 kbaud. So a 64MB flash would take about 6400 seconds. I have USB once the system is up. I guess I could write a stub application with just enough code to get the USB up, but it won't fit in the FPGA block ram which then means: program prom, transfer stub app over RS-232, finish over USB.Article: 115806
"vlsi_learner" <bajajk@gmail.com> wrote in message news:1172051271.621813.243870@a75g2000cwd.googlegroups.com... > Hi > > While delivering an IP is it necessary to have all the outputs > registered? what is the advantage from this? > Only if the requirements of the design demand registered outputs. Kevin JennignsArticle: 115807
Just wondered if anyone could point me to documentation on the timing constraints for the "altsyncram" standard module on Cyclone II. I have chapter 8 of the device handbook, which has a basic diagram, but when I try to duplicate the timing of this diagram, I don't seem to be able to get clock speeds above about 100MHz to work correctly (according to Quartus II's simulation). I understood this module was supposed to function at 200MHz, so I guess I must be doing something wrong, but what it is I'm at a loss to explain. I've tried shifting my clock signal's phase in relation to the control signals, but haven't found anything that helps. In case it's relevant, I'm using it in true dual-port mode, with a single clock for both ports.Article: 115808
On 21 Feb, 08:59, "Surya" <aswingopa...@gmail.com> wrote: > I am developing an FPGA application which works in series with a main > processor which is running an RTOS(VxWorks). Since my inputs and > outputs are to and from that processor, should i be using any RTOS? > > Kindly clarify. thanks in advance. > > Regards > Surya. It really depends on your application. If you're implementing a processor core that will run multiple tasks, then you may want to consider using an RTOS. If your FPGA is only performing a single task, having an RTOS (or in fact, any OS) will just increase your resource requirements. Remember that bare hardware without an OS is also capable of realtime.Article: 115809
On 18 Feb, 23:18, Jaime Andres Aranguren Cardona <j...@nospam- sanjaac.com> wrote: > Hello, > > Talking about video codecs, specifically Theora (www.theora.org) and > M-JPEG2000, how do they compare in terms of compression ratio for a given > quality? Well, I've seen discussions that suggest JPEG2000 can compare favourably with MPEG-4, and also others that suggest there's not a lot to choose between Theora and MPEG-4. The discussions are usually talking about quality for specified ratio, but that typically works out similar. > Being M-JPEG2000 based on still pictures and not taking advantage of > interframe redundancies (from the very few I have read so far), is it > viable for networking and storage applications? Given that MJPEG was clearly viable, I see no reason why not. It's also possible to trivially create a variant that takes some advantage of interframe redundancies by encoding an image that's subtracted from the previous frame (as it appears after running back through the decoder, not the original frame). I did that with JPEG once and the results were reasonably good.Article: 115810
Doesn't the ASIC library have dual-port RAMs? As I said, if you have a target ASIC in mind, perhaps those that have used that ASIC can help. You can probably use a dual-port library element directly. If a single port truly is all you have available, run the memory at a higher frequency and perform the reads and writes as time-muliplexed operations. The asynchronous write/read time domains makes the coordination a pain in the neck but it's doable. If you need a read valid shortly after a write, you may need additional logic to allow that turnaround to occur quickly. It's not pretty but it's doable with just single port SRAMs. First, look for native pseudo dual port memories from the ASIC vendor. Only if that fails, use a fast clock preferably at 3x the read clock where you can have the read transaction occur as if it's real time and use posted writes from that asynchronous time domain. vlsifresher wrote: > My writes take place at 60 Mhz & reads at 35 Mhz. > The maxm memory freq is 120 Mhz. > I require it for an ASIC design > > Thanks > > On Feb 20, 10:20 pm, "John_H" <newsgr...@johnhandwork.com> wrote: >> And I'll repeat the other questions: >> >> What is your operating frequency versus maximum memory frequency? >> If you have a 50 MHz read/write clock and your memory can give you 300 MHz >> performance, you can use a faster clock and time multiplex your writes and >> reads. >> Are you targeting a specific device? >> If you don't know the device capabilities but have a specific FPGA or ASIC >> in mind, perhaps you could get specific help from those who know your target >> well. >> >> If this is just a homework problem - no specific device, no specific >> frequency - be up front about it and you're more likely to get good help. >> >> - John_HArticle: 115811
On 14 Feb, 17:52, pixelsm...@gmail.com wrote: > Hello , > > Several years ago when I designed my first PCI add -in card for a > wintel platform I discovered that back to back CPU reads of the PCI > card's memory address space did not get burst but instead where sent > as two seperate frames. Each frame had only a single read. The result > was that the CPU could only acheive a 6 Mbytes per sec read bandwidth > vs 55 or so if the reads where burst. (32bit PCI bus @ 33 MHZ less > overhead ) Are you sure about this result? The benchmark linked below suggests that a PCI Gigabit Ethernet card is capable of transferring data over the network at speeds similar (i.e. about 44MB/sec) to your suggested theoretical maximum for the bus, so it can't be doing it wrong. http://www.tomshardware.co.uk/2006/08/08/diy_nas_smackdown_uk/index.html Perhaps it was a driver issue?Article: 115812
On Feb 21, 5:34 am, "cpope" <cep...@nc.rr.com> wrote: > > Remember, jtag is just a synchronous serial interface, with a mode > > pin... there's no reason you can't get comparable throughput from a > > simple function temporarily downloaded into your FPGA. In fact you > > should be able to do better, as you could minimize the overhead. > > I should have specified UART. Max I can get is 115 kbaud. So a 64MB flash > would take about 6400 seconds. Then don't use the UART. Make your own synchronous serial connection. You seem to be treating the jtag loader as somehow magic - it isn't, it's still a synchronous serial connection with a download speed deteremined by it's clock rate. The difference is that you can buy it already working, wheras this you would have to build, license, or locate in open-source form.Article: 115813
On Feb 21, 10:19 am, cs_post...@hotmail.com wrote: > Then don't use the UART. Make your own synchronous serial > connection. You seem to be treating the jtag loader as somehow magic > - it isn't, it's still a synchronous serial connection with a download > speed deteremined by it's clock rate. And start by looking here: http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htmArticle: 115814
S, This is not the "rocket science" part of the business. Even with all of the constraints, there should be a way to get our samples to our customers. Breaking packages into smaller packages means that customers must bake their parts before they use them, as moisture may have seeped into the parts when the packages were being re-packaged. Moisture is death to the part, as the device will "popcorn" when solder reflowed to the pcb without a pre-bake. No one wants to open the package (which may contain hundreds of parts), take one out, put it into a new package, and place it on a shelf for a customer. That said, it is done, and done right by people, so it isn't like this is not possible, it is done everyday. I wish it was as easy as you suggest, but to insure that we don't deliver popping corn, we do need to pay attention to the proper handling of the parts in the distribution channel. This is not a job for amateurs. AustinArticle: 115815
On 2007-02-21, Jules <jules@dsf.org.uk> wrote: > On 14 Feb, 17:52, pixelsm...@gmail.com wrote: >> Hello , >> >> Several years ago when I designed my first PCI add -in card for a >> wintel platform I discovered that back to back CPU reads of the PCI >> card's memory address space did not get burst but instead where sent >> as two seperate frames. Each frame had only a single read. The result >> was that the CPU could only acheive a 6 Mbytes per sec read bandwidth >> vs 55 or so if the reads where burst. (32bit PCI bus @ 33 MHZ less >> overhead ) > > Are you sure about this result? The benchmark linked below suggests > that a PCI Gigabit Ethernet card is capable of transferring data over > the network at speeds similar (i.e. about 44MB/sec) to your suggested > theoretical maximum for the bus, so it can't be doing it wrong. > > http://www.tomshardware.co.uk/2006/08/08/diy_nas_smackdown_uk/index.html The original post was talking about reading from the card via memory reads on the CPU. The cards that are tested in the benchmark are transferring data via DMA without involving the CPU. For people interested in latency of PCI, PCI-X or PCI Express cards mmio_test might be something to google for IIRC. /AndreasArticle: 115816
Hello all, What is the difference between a NET and a PAD with regards to constraints management? Also, I noticed that I can constrain my FPGA_CLK but it looks like there's another element called FPGA_CLK_c . Why does Xilinx ISE add this extra element? What is it? Thanks.Article: 115817
I am having this exact same problem, but using schematic entry and automatic VHDL from that. I have spent hours trying to get PACE to look at MY ports. It works if I create a new project with just a schematic containing an inverter and one in and one out pin. PACE lets me assign the two clock pins. But when I add even one part such as a counter, then PACE says that it can not apply my constraints and my pins and their nets no longer show up in PACE's list of nets. Instead the various unused pins of library parts that I have used, are what show up as nets in PACE. One hint perhaps, is that I get warnings about the source of the ports and entities definitions, being changed from the schematic to the generated vhdl file. I think that this is an encapsulation issue. All this, yet the design actually works in hardware. It's an inverter for a crystal clock, that then drives three 8-bit counters to divide down for a blinking LED. Anyone know how to fix this ? - BruceArticle: 115818
how to create an 8 bit up down lfsrArticle: 115819
Where's the rest? I thought this was a how to.... : )Article: 115820
jams, http://www.caip.rutgers.edu/~bushnell/COURSE/lec27.ppt slide 4 Ever used Google before? Try it. "up down lfsr" AustinArticle: 115821
On 15 Feb, 17:39, "Matt B" <mbb...@gmail.com> wrote: > If you just want to include a netlist generated by CoreGen in your XPS > project, you will need to create a BBD (black box definition?) file in > the data/ directory of the pcore you want to use the core in. You will > also need to create a netlist/ directory to put your EDNs and NGCs > in. > > Matt thanks for your help I've got it sorted nowArticle: 115822
Hi I need to convert type : array (0 to 3) of std_logic_vector (31 downto 0) to type : STD_LOGIC_VECTOR2 ( 3 downto 0 , 31 downto 0 ) As an example, I was using signal DATA_TEMP(3) <= x"80030001"; How should I modify the *DATA_TEMP* signal? If someone knows this, please let us know. Thankyou in advance.Article: 115823
I'm talking to an IPIF device on the OPB bus from a linux driver. My problem is that when I try to write to the DIER register to enable device interrupts, linux gives me a bus error. (Enabling, receiving, and processing user logic interrupts through the driver is working with no problems.) I hooked up chipscope, and I see that it takes 15 bus cycles before the DIER write is acknowledged by the IPIF device, and because OPB_toutSup isn't being asserted, I think the transaction is timing out. Since the DIER belongs to the IPIF device, shouldn't the device be responsible for asserting OPB_toutSup if necessary? But if this transaction really did require 15 bus cycles to do its thing, surely the IPIF architects would have been aware of it. So I assume that I'm doing something wrong or just missing something here. The device isn't waiting for something from my user logic, is it?Article: 115824
Hi, I have been doing designs, digital and analog, for over 20 years, without making use of ibis data, but I think that is about to end. I was doing a design with one of the newer Altera BGA's and could not find the ususal "rise time", "fall time" data, so I inquired to Altera. Altera told me that they provide ibis models for more cases than I could count but that the "old style" specifications were no longer applicable. What I am trying to do is match the output of an Altera device to a transmission line. If I don't know the rise time and the output impedance then I have little chance of making a good match. I tried using the freeware tool from Intusoft that can translate ibis models to spice models (I have used spice for a long, long time) but the translator would only translate models up to ibis version 3.0. The ibis models provided by Altera were based upon ibis 3.2 and there were errors in the translation. The whole process of making use of ibis models must be easier than I am making it. I would think that if I had an ibis simulator, then I could use the ibis models provided by manufacturers and then create ibis models of my own to simulate the transmission lines in my design. 1) Is that last assumption correct? 2) Are there freeware ibis simulators? 3) Can someone recommend an inexpensive ibis simulator? 4) What am I missing in all this that makes the process seem more complex than it probably is? Thank You Tom
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Compare FPGA features and resources
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