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cs_posting@hotmail.com wrote: > On Mar 22, 5:34 am, Herbert Kleebauer <k...@unibwm.de> wrote: (snip) >>I don't know if all the supporters of VHDL/Verilog/HandleC here have >>done low level logic development using a graphical representation and >>just don't recognize how important that is to become a good designer >>at VHDL level. > The problem I see is that you are making the assumption that > _graphical representation_ is the only appropriate way to do low level > design. I'd argue it generally isn't. I have to argue somewhere in between. The designer should have some idea about what is going on in the hardware. For FPGA it isn't quite as easy to see, so imagine a standard cell design instead. For standard cell the actual complexity is closer to that seen by the designer. It does help to imagine it in terms of gates, just as a C programmer can imagine his code in terms of machine instructions. Though with modern RISC machines you might be as far from what one can imagine as FPGAs are from gates. One should be able to choose a design based on complexity or speed. (Often speed is more important than size, and that isn't so obvious if you can't imagine the gate level.) > More suitable low level design notations are things like minimum-sum- > of-products equations, and the Karnough maps that one might use to > create those by hand. Sum of products is directly implementable in > hardware - you could indeed have them draw some representative > examples as gates. But it's a much better notation system when you > find it necessary to take the black boxes apart and look at their > functionality. One has to look at the problem at different levels. One is the gate level, another would have been the MSI level in TTL days, adders, counters, multiplexers, decoders. One doesn't need the exact details (though I do still like to see the designs in the TTL data book), but just to know how complex each one is or isn't. (snip) > A key reality that you are refusing to acknowledge is that you will > not receive an actual "map to the city" of anything but a first- > generation FPGA. That kind of detail is proprietary. What you get on > the data sheet is a programming model, with a lot of things already > hidden from you. Using an FPGA to implement something that you've > designed at the gate level is not a bad idea, but you must come to > terms with the fact that your gate level design is only theoretical - > even if you draw it in schematic entry, the tools is going to refactor > it using its knowledge of the proprietary details of the hardware. That is true, but as I said one can imagine it for standard cell. One might even be able to run the synthesis and P&R for a standard cell design to see how big or small things actually are. (snip) >>The same is true for software: if you know how the hardware >>works you maybe can choose a different approach to solve the >>problem which is much more appropriate for the hardware. This is still very true for today's software. Maybe even more, as many of the old rules don't apply anymore. With overlapped execution it isn't easy to predict the timing for even simple software projects. (snip) >>The purpose of Universities is not to teach the students the >>use of tools but to teach them how to recognize, analyze and >>solve problems. The tools you use to solve the problems change >>rapidly but the ability to understand the source of a problem >>and analyze it from all angeles without using blinders is an >>essential requirement for the whole life. > And ever since we stopped designing chips on single pieces of paper, > the number one skill for a solving problems has been developing a > healthy relationship with the _concept of abstraction_. >>Sorry, but it really doesn't matter whether the AND gate is implemented >>as AND gate, by multiplexers or as a look-up table. They have learned >>that this all is equivalent and that the order of complexity is the >>same. But they must learn that there is big difference in the complexity >>for the ALU operation "add" and "div" and they don't see this in >>the VHDL source code. But the order of complexity really isn't the same. A four input exclusive or gate is much more complicated than a four input nand gate made out of transistors, but not made out of LUTs. > They most certainly will see this in the VHDL source code if you have > require them to code up the ALU functionality from sufficiently small > building blocks! (snip) > The moral? Pick your battles. Your course project doesn't have > anything that can't easily be implemented as gates and registers, so > let your students implement in a gates and registers programming > model. But recognize that just because a language will let you > utilize fancy functions like a hardware multiplier does not mean that > you have to choose to do so, or let your students do so. One should pick the appropriate blocks, either as schematic capture or HDL. Most schematic capture systems include a library of logic blocks, probably similar to those available in HDL. Actually, more than the synthesis tools will generate directly! -- glenArticle: 117151
> I'm talking to an IPIF device on the OPB bus from a linux driver. My > problem is that when I try to write to the DIER register to enable > device interrupts, linux gives me a bus error. If anybody cares to know what caused this, I chose not to include the device ISC (interrupt service controller) in my IPIF, so there was simply no circuitry there to handle or acknowledge the DIER write. Didn't put two and two together though until I noticed the tell-tale "constant USER_INCLUDE_DEV_ISC : boolean := false;". Funny how that works. ;)Article: 117152
is it possible to implement a serial in , parellel out shift register from xilinx distributed ram? any guidance is appreciated.Article: 117153
is it possible to implement a serial in , parellel out shift register from xilinx distributed ram? any guidance is appreciated.Article: 117154
Un bel giorno Paul digiṭ: > Anywho... does anyone actually have a legitimate > reason for brand loyalty? Familiarity with the development tools? Better app notes/technical support? -- emboliaschizoide.splinder.comArticle: 117155
On Mar 24, 1:26 am, "CMOS" <manu...@millenniumit.com> wrote: > is it possible to implement a serial in , parellel out shift register > from xilinx distributed ram? any guidance is appreciated. I remember seeing an app note on the Xilinx web site dealing with using the JTAG port to initialize BRAMS that showed how to get two bits per lut plus one more from the FF. I think it was an app note by Ken Chapman showing how to initialize the BRAM in a PicoBlaze. A quick search of the Xilinx web site mentions a program called JTAG_loader that I think uses this technique. I will leave the rest of the searching up to you, unless maybe some one with near perfect recall just happens to remember the app note I am talking about. Regards, John McCaskill www.fastertechnology.comArticle: 117156
On Mar 24, 12:26 am, "CMOS" <manu...@millenniumit.com> wrote: > is it possible to implement a serial in , parellel out shift register > from xilinx distributed ram? any guidance is appreciated. The LUT-based distributed RAM in Xilinx FPGAs can be used as a shift register, called SRL16 or SRL32, with a length (depth) that is dynamically adjustable by the address inputs. But since the LUT has only one output (2 in Virtex-5) you cannot use a LUT as serial-to- parallel converter. Peter Alfke, Xilinx ApplicationsArticle: 117157
CMOS wrote: > is it possible to implement a serial in , parellel out shift register > from xilinx distributed ram? any guidance is appreciated. Think of how a serial-in, parallel-out shift register is put together. There is series of shift elements that shift the data in with a broadside dump of all the shift registers into output holding registers. If you implement an n-bit serial-in, parallel out shift register where the most recently shifted in bit is present on the output, you'll need 2n registers. If you want the top n bits of an m-bit shift register where the most recently shifted bit is m-n bits from the parallel-out data, you can use 2(n-1) independent registers and int((m-n+15)/16) shift registers where the last distributed memory shift register also uses the embedded register for output. While the tools would not synthesize the stages, you could instantiate an SRLC16E element with an output mux address of 0 to accompany the output registers to get an n-bit serial-in, parallel-out shift register in n LUTs with n embedded output registers. But since registers are plentiful in the Xilinx series (heck, Lattice even tossed out 25% of the rigisters in their low-cost family in recognition of this fact) it's probably much better to used the registers (implemented with direct inputs) and leave the LUTs for use for other combinatorial logic. The register-only approach also eliminates the problems with whether to reset or not since the distributed RAM shift registers 1) cannot take a reset themselves and 2) make the use of a reset for the embedded output register almost impossible. - John_HArticle: 117158
On Mar 24, 9:57 am, "Peter Alfke" <a...@sbcglobal.net> wrote: > On Mar 24, 12:26 am, "CMOS" <manu...@millenniumit.com> wrote: > > > is it possible to implement a serial in , parellel out shift register > > from xilinx distributed ram? any guidance is appreciated. > > The LUT-based distributed RAM in Xilinx FPGAs can be used as a shift > register, called SRL16 or SRL32, with a length (depth) that is > dynamically adjustable by the address inputs. But since the LUT has > only one output (2 in Virtex-5) you cannot use a LUT as serial-to- > parallel converter. > Peter Alfke, Xilinx Applications The SLR16s have two outputs that can be used for serial to parallel shifters, the Q15 for cascading, and the selectable output. I finally found the article that describes how to use an SRL plus a FF to build a 6 bit per slice serial to parallel shifter. It is by Kris Chaplin, not Ken Chapman like I had been thinking. The article is a TechXclusives "Reconfiguring Block RAMs" at: http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?iLanguageID=1&category=&sGlobalNavPick=&sSecondaryNavPick=&multPartNum=2&sTechX_ID=krs_blockRAM or: http://tinyurl.com/2fyll8 Regards, John McCaskill www.fastertechnology.comArticle: 117159
Hi , please my problem is how to use real constant for example 0.1913 and multiply it with an std_logic_vector(7 downto 0) and as an exmple to remplace reals b std_logic_vector , i did find that -- Y = 0.299 * R.000 + 0.587 * G.000 + 0.114 * B.000 -- Y = 0x132 * R + 0x259 * G + 0x074 * B -- -- Cr = 0.713(R - Y) -- Cr = 0.500 * R.000 + -0.419 * G.000 - 0.0813 * B.000 -- Cr = (R >> 1) - 0x1AD * G - 0x053 * B -- Cb = 0.565(B - Y) -- Cb = -0.169 * R.000 + -0.332 * G.000 + 0.500 * B.000 -- Cb = (B >> 1) - 0x0AD * R - 0x153 * G please i cant get how the reals are converted like that (hexadecimal), is any one can explain it to me ? please and thank youArticle: 117160
"kha_vhdl" <abaidik@gmail.com> writes: > please my problem is how to use real constant for example 0.1913 and > multiply it with an std_logic_vector(7 downto 0) Represent your real constants as two's complement fixed-point fractions. For instance, if you're going to use the hardware multiplier in a Xilinx FPGA, it is convenient to use 18-bit representation, so you multiply 0.1913 by 2^17, resulting in a fixed-point constant 0x061f2.Article: 117161
On 24 mar, 20:52, Eric Smith <e...@brouhaha.com> wrote: > "kha_vhdl" <abai...@gmail.com> writes: > > please my problem is how to use real constant for example 0.1913 and > > multiply it with an std_logic_vector(7 downto 0) > > Represent your real constants as two's complement fixed-point fractions. > For instance, if you're going to use the hardware multiplier in a Xilinx > FPGA, it is convenient to use 18-bit representation, so you multiply > 0.1913 by 2^17, resulting in a fixed-point constant 0x061f2. REALLY THANK YOU FOR YOUR EXPLAINATION THANK YOU , i did get it now thank youArticle: 117162
On Mar 23, 8:33 pm, Zara <me_z...@dea.spamcon.org> wrote: > On 23 Mar 2007 05:13:46 -0700, "Allen" <lphp...@gmail.com> wrote: > > > > > > >hi all, > > >first, i am sorry for my poor English. > > >i use EDK 7.1i and ISE 7.1i. > > >imported custom peripheral with PLB Master Interface ( not from IFIP ) > >into my .xps project after overcame several problems. > > >In the step " generate netlist " there has no error or warning. > > >but in the step "Generate Bitstream",i got a error message "ERROR!! > >NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": return code 2 > >abort. > > >already search this problem in xilix's answer database and tried > >modify the parameter of C_BaseAddr, but it is still stuck here. > > >does anyone meet this problem before? > > >thanks in advance. > > I always got that messaghe when I had some signal with two outputs > connected to it. That seems your case, in your plb address bus, master > interface. > > Best regards, > > Zara- Hide quoted text - > > - Show quoted text - Thanks for your reply. so it might mean something wrong during import of custom peripheral? but in 64-bit PLB protocol, the address width is 32-bit. i already use (C_PLB_AWIDTH-1) to replace with constant "31" in my port declaration. do anything i could try to solve this problem? thank you :-)Article: 117163
Paul, For the same reasons as you spelled out we wanted to migrate from QII 6.0 to QII 6.1 unfortunately, the signed multiplier did not get inferred correctly in QII 6.1. I can still remember checking with the QII documentation to see if we incorrectly described the logic. But everything was according to the docs on Altera's website. The point is that it is this kind of unpredictable behavior between releases of the tools that give us cold feet when it comes to moving an existing project to a new release of the software. -sanjay > > So if you don't care about Stratix III or Cyclone III devices, don't > want faster & better compilation results, don't need to interface with > a PCB, and aren't hitting any bugs that affect your design, there's no > reason for you to move to QII v7.0. However, the migration experience > is fairly painless, and you may find yourself liking some of the new > features you can by migrating. >Article: 117164
On Mar 23, 5:21 pm, John_H <newsgr...@johnhandwork.com> wrote:
> GaLaKtIkUs=E2=84=A2 wrote:
> > On Mar 23, 8:45 am, "MM" <m...@yahoo.com> wrote:
> >> "GaLaKtIkUsT" <taileb.me...@gmail.com> wrote in message
>
> >>news:1174626985.784318.16210@n76g2000hsh.googlegroups.com...
>
> >>> This board INVERTS LVDS PAIRS ie: if I
> >>> have an output {XP,XN} I get the input {XN,XP}. ({A,B}=3DA on P pin a=
nd
> >>> B on N pin).
> >> 1. I doubt anyone can understand your description above. Are you tryin=
g to
> >> say that the wires are crossed on the board?
> >> 2. Use a scope.
>
> >> /Mikhail
>
> > They are not crossed like X. the problem is the following if we try
> > (using the loop back board) to get P pin on P pin and N pin on N pin
> > we will be obliged to cross the wires (make an X on the board). To
> > avoid this the guy ho made that loopback board decided to send the P
> > to N and N to P and says that the only problem will the inversion of
> > the logic levels.
> > I reformulate my question in more simple terms:
> > I LVDS pins are crossed what would be the result? only inversion of
> > logic levels or more?
> > Mehdi
>
> 1) Are you using 8B10B or some similar coding?
> 2) use a scope
8B10B is not used.
using a scope is not possible!!
I rewrote my HDL code from the beggining and it worked. The problem
was in wrong use of OSERDES.
Now I'm transmitting at 16x1Gb/s.
Thank you for having taken time to answer
Mehdi
Article: 117165On Mar 25, 12:32 am, "Allen" <lphp...@gmail.com> wrote: > On Mar 23, 8:33 pm, Zara <me_z...@dea.spamcon.org> wrote: > > > > > On 23 Mar 2007 05:13:46 -0700, "Allen" <lphp...@gmail.com> wrote: > > > >hi all, > > > >first, i am sorry for my poor English. > > > >i use EDK 7.1i and ISE 7.1i. > > > >imported custom peripheral with PLB Master Interface ( not from IFIP ) > > >into my .xps project after overcame several problems. > > > >In the step " generate netlist " there has no error or warning. > > > >but in the step "Generate Bitstream",i got a error message "ERROR!! > > >NgdBuild:455 plb_M_ABUS<62> has multiple driver(s)": return code 2 > > >abort. > > > >already search this problem in xilix's answer database and tried > > >modify the parameter of C_BaseAddr, but it is still stuck here. > > > >does anyone meet this problem before? > > > >thanks in advance. > > > I always got that messaghe when I had some signal with two outputs > > connected to it. That seems your case, in your plb address bus, master > > interface. > > > Best regards, > > > Zara- Hide quoted text - > > > - Show quoted text - > > Thanks for your reply. > > so it might mean something wrong during import of custom peripheral? > > but in 64-bit PLB protocol, the address width is 32-bit. > > i already use (C_PLB_AWIDTH-1) to replace with constant "31" in my > port declaration. > > do anything i could try to solve this problem? > > thank you :-) The PLB address width is 32 bits. However, the way that all the bus signals are connected to the PLB IP is that they are concatenated together. So if you look at the MPD file for the PLB you will see that it defines the bus width to be 32 bits times the number of masters: PORT M_ABus = M_ABus, DIR = I, VEC = [0: (C_PLB_NUM_MASTERS*C_PLB_AWIDTH)-1] So the signal plb_M_ABUS<62> is bit 30 of the second master. Look to see if your core has been assigned the second master slot on the PLB bus. Assuming that is the case, find what two sources are driving bit 30 of the address. Assuming that you left the name of your EDK project as system.xmp, when you tell EDK to generate a netlist it will create a top level hdl file named either system.vhd or system.v depending on your tool settings. You can look at this file to see how EDK has connected the cores to the PLB. It has been a while since I had to find a multi source signal, but I think that XST will produce a warning about it in its report and tell you what the multiple soures are. Look in the synthesis report file for the appropriate core and see if it tells you what the source of the problem is. Since you are creating your own interface design instead of using the IPIF, are you using the bus functional models in your simulations? I use these, and they make the job much easier. I think it was not until EDK 8.1 that they were integrated into EDK itself, but I was able to use the CoreConnect tool kit directly from IBM in some of our early stuff. The bus monitors will tell you as soon as your core has done something wrong, so you do not have to track the source of the problem back from when the symptoms show up. Regards, John McCaskill www.fastertechnology.comArticle: 117166
Hi,
I would like to load a on-chip ROM in a Altera Stratix device with the
data produced by the linker script shown below. Since the text segment
is not located at address 0x00000000, ModelSim, or altera_mf.v rather,
produces the following error:
# ERROR: rom.hex, line 1, Unknown record type.
# ERROR: rom.hex, line 1, Invalid checksum.
Any suggestions? I'm basically looking for a way to relocate the base
address to 0 without actually affecting the data produced by the
linker, as I need to keep everything statically linked.
Thanks,
Edmond
--- rom.ld (linker script) ---
MEMORY
{
rom : ORIGIN = 0x08000000, LENGTH = 4k
}
SECTIONS
{
.text :
{
. = ALIGN(4);
*(.text)
_text_end = . ;
} > rom
}
--- rom.hex ---
:020000040800F2
:100000003C040A0024080005AC8800002408000A0B
:100010000E000041000000000000000D0000000084
:1000200000000000000000000000000000000000D0
:1000300000000000000000000000000000000000C0
:1000400000000000000000000000000000000000B0
:1000500000000000000000000000000000000000A0
:100060000000000000000000000000000000000090
:100070000000000000000000000000000000000080
:100080000000000000000000000000000000000070
:100090000000000000000000000000000000000060
:1000A0000000000000000000000000000000000050
:1000B0000000000000000000000000000000000040
:1000C0000000000000000000000000000000000030
:1000D0000000000000000000000000000000000020
:1000E0000000000000000000000000000000000010
:1000F0000000000000000000000000000000000000
:100100000000000D1500FFFF2108000103E00008BA
:1001100000000000000000000000000000000000DF
:1001200000000000000000000000000000000000CF
:1001300000000000000000000000000000000000BF
:1001400000000000000000000000000000000000AF
:10015000000000000000000000000000000000009F
:10016000000000000000000000000000000000008F
:10017000000000000000000000000000000000007F
:10018000000000000000000000000000000000006F
:10019000000000000000000000000000000000005F
:1001A000000000000000000000000000000000004F
:1001B000000000000000000000000000000000003F
:1001C000000000000000000000000000000000002F
:1001D000000000000000000000000000000000001F
:1001E000000000000000000000000000000000000F
:1001F00000000000000000000000000000000000FF
:0400000508000000EF
:00000001FF
Article: 117167Hi All, I'm looking for a tool, or a method to convert the ISE project into a makefile, which I could run remotely without X connection. The only thing I've foond is: http://www.xess.com/appnotes/makefile.html However I don't now if it works with ISE 9.1. Could anybody share some experiences? -- TIA & Regards, Wojtek Zabolotny wzab@ise.pw.edu.plArticle: 117168
On 2007-03-25, Wojciech Zabolotny <wzab@mail.cern.ch> wrote: > Hi All, > > I'm looking for a tool, or a method to convert the ISE project into a > makefile, which I could run remotely without X connection. > The only thing I've foond is: http://www.xess.com/appnotes/makefile.html > However I don't now if it works with ISE 9.1. > Could anybody share some experiences? I don't think there is such a tool available, (especially not since they changed their project file to binary...) but writing your own Makefile is not that hard if you don't worry too much about dependencies. There was a thread about this some time ago on this newsgroup and some scripts were posted. The scripts I posted are available on my homepage at http://www.da.isy.liu.se/~ehliar/stuff/ I would recommend starting with xil_synt_test.sh if you are not that interested in dependencies since it is quite straightforward. Just edit it to set what part you are using and then run it with xil_synt_test.sh yourtoplevel.v yourucffile.ucf the.v rest.v of.v\ your.v design.v files.v This script works with ISE 7.1, 8.1, 8.2 and 9.1 as far as I know. /AndreasArticle: 117169
On Mar 23, 4:16 am, "Luzerne" <luzerne.gan...@gmail.com> wrote: > On 23 mar, 07:25, carlos.as...@gmail.com wrote: > > > I'm very new to linux but I undestand that you propose an alternative > > to windrvr that seems to work well. > > [...] > > I've spent many hours trying to get the windrvr and your driver to > > work without success. > > [...] > > I would really appreciate some help. I'm new to Linux and I use > > Kubuntu 6.10. > > Here is my "step by step newbie" installation howto for Ubuntu Dapper > 6.06 :) > > Open a terminal (Application menu : Accessory > Terminal), where you > can enter the given commands (line starting with the $ prompt symbol). > > We suppose we are in your prefered directory. For you it is probably > something like "/home/carlos". For this tutorial il will be replaced > by a generic "/path" : > > $ pwd > /path > > First, you donwload the program's archive in your prefered "/path/ > Download" directory. > > $ mkdir Download > $ wget "http://cvs.zerfleddert.de/cgi-bin/viewcvs.cgi/usb- > driver.tar.gz?view=3Dtar" -O Download/usb-driver.tar.gz > > Now you go in your prefered work directory (for me it is called > "Travail" :) and you decompress the archive. > > $ cd /path/Travail > $ tar zxvf /path/Download/usb-driver.tar.gz > $ cd usb-driver > > First thing to do is to check if README or INSTALL files exist, and > _READ_ them. > > $ ls -l > $ more README > > Now you know what to do. First you check the required module are > loaded. > > $ lsmod | grep parport > parport_pc 38340 1 > parport 39560 3 ppdev,lp,parport_pc > > If you get something like that, it's ok. You can compile. > > $ make > > You may get this kind of error : > > gcc -fPIC -Wall usb-driver.c -o libusb-driver.so -ldl -lusb -lpthread - > shared > usb-driver.c:36:17: erreur: usb.h : Aucun fichier ou r=E9pertoire de ce > type > > It's because you have not installed one of the required libusb and > libusb-dev library. > You can install libusb-dev this way : > > $ sudo apt-get install libusb-dev > > Now you can retry the compilation. > > $ make > gcc -fPIC -Wall usb-driver.c -o libusb-driver.so -ldl -lusb -lpthread - > shared > gcc -fPIC -DDEBUG -Wall usb-driver.c -o libusb-driver-DEBUG.so -ldl - > lusb -lpthread -shared > > This time, if everything goes right, you can try impact :) As > explained in the README, set the preload environnement variable (this > will be set only for the current terminal) : > > $ export LD_PRELOAD=3D/path/Travail/usb-driver/libusb-driver.so > > Now, you can run impact. But you may get an error : > > Can't open /dev/parport0: Permission denied > LPT port is already in use. rc =3D 0h > Cable connection failed. > Reusing 79063641 key. > Reusing FD063641 key. > > It means you have not the required right on the /dev/parport0 device. > You can check this this way : > > $ ls -l /dev/parport0 > crw-rw 1 root lp 99, 0 2007-03-16 07:48 /dev/parport0 > > A fast work arround solution is to change the owner of this device : > > $ whoami > luzerne > $ sudo chown luzerne /dev/parport0 > > Before retrying to program a device with impact, it may be necessary > to disbale the eventual impact cable locking. This can be done this > way : > > $ impact -batch > > > setMode -bscan > > cleancablelock > > quit > > Now, you can retry to program a device with impact. This was my "step > by step" personnal log. > > http://www.chezmoicamarche.org/ YMMV / HTH > > Luzerne GANHIR Thank you very much Luzerne for taking the time of explaining it step by step really clearly and slowly. I really really appreciate it. What I was doing wrong was doing "export LD_PRELOAD=3D/path/Travail/usb- driver/libusb-driver.so" in another terminal session since I thought this was a kind of global setting. Again thanks a lot for everything you have done. CarlosArticle: 117170
Dear Sir I am using Quartus by ALtera, i have made my design using VHDL and have ran it on model sim, the basic design use a state machine that depends on a clock. each state execute some vhdl code. by when i try synathise it i get warnings such as Warning: Can't achieve minimum setup and hold requirement CLK_H along 1922 path(s). See Report window for details. -17.200 ns brain:I0|WRITE:I0|counter[4] rammomb:I1| alt3pram:alt3pram_component|altdpram:altdpram_component2|q[10]~reg_wa4 CLK_H CLK_H 0.000 ns 19.000 ns 1.800 ns please guide me on what i need to do, the design has a counter 5-bit which is basically the inputted to the RAM address input. Regards Dharmesh JoshiArticle: 117171
Many engineers today have Linux on Desktop as main-OS. Many engineers today use Open Source products because of their quality, stability, and configurability. Today I see no alternative to use Xilinx or Alteras Web Packs. Both are in a very sad state. As Linux or PowerPC user you cannot develop your FPGA design with this tools. On x86 or on Windows they are very buggy, slow, and unproductive as well. So, any idea, how can we change this situation? Will we meet the time of Open Source development tools for programmable logic devices?Article: 117172
"John McCaskill" <junkmail@fastertechnology.com> wrote in message news:1174756909.000771.39330@e1g2000hsg.googlegroups.com... > The SLR16s have two outputs that can be used for serial to parallel > shifters, the Q15 for cascading, and the selectable output. I finally > found the article that describes how to use an SRL plus a FF to build > a 6 bit per slice serial to parallel shifter. It is by Kris Chaplin, > not Ken Chapman like I had been thinking. Slightly in another direction...is there a trick to setting up the cascades on the SRL16s to maintain a consistent delay? We strung 8 in a row to get an adjustable 1-bit delay line. It works, but there's a bunch of extra muxes, etc. to get the delay consistent (3 clocks plus whatever tap I pull as output). I'm actually the systems guy and not the VHDL coder (and communication of requirements is always tricky when you're doing something new), but I'm always interested in the mechanics to see if it can be done better (smaller) while still meeting requirements. Especially since I'd really like a 1024 tap delay but I ran out of space (I need tens of these, plus other DSP goodies). Suggestions on other mechanisms to use are also welcome. Dr. Marty Ryba martin (dot) ryba (at) verizon (dot) net (man, I hate sp*m)Article: 117173
psihodelia@googlemail.com wrote: > Many engineers today have Linux on Desktop as main-OS. Many engineers > today use Open Source products because of their quality, stability, > and configurability. Hmm, yes, but your many is still a tiny %. Other are more pragmatic: as long as windows does not get in the way, they tolerate it. > > Today I see no alternative to use Xilinx or Alteras Web Packs. Both > are in a very sad state. As Linux or PowerPC user you cannot develop > your FPGA design with this tools. On x86 or on Windows they are very > buggy, slow, and unproductive as well. > > So, any idea, how can we change this situation? Will we meet the time > of Open Source development tools for programmable logic devices? Full end to end flow tools, probably never. Xilinx and Altera's engineers are not inept nor incompetent (tho yes, sometimes users can wonder..) - a large part of their problem is the continually moving target of their silicon. Now, if large teams of SW designers, working with in-house correlation between the Silicon designers, and the SW crew, struggle to achieve quality, how are OpenSource teams, without that link, going to achieve - well, much at all ?. That said, there is plenty of scope for opensouce+FPGA. opencores / Lattice Mico8 / Mico32 are all examples. Others are working on various HDL/Sim alternatives, but back end tools like Map/P&R ? - rather less likely, until the pace of change slows down. Plus, the vendors give free tools, so there is not the price, or sponsored, incentive other open-source targets have. There probably is scope for users to co-operate more with the vendors, in raising Sw quality. As an aside, this made interesting reading http://www.eetimes.com/showArticle.jhtml;jsessionid=XE4AJV2TYRLWGQSNDLRCKH0CJUNN2JVN?articleID=198500084 -jg -jgArticle: 117174
Quartus defaults to the most stringent hold requirement, 0ns. A hold violation is typically due to clock skew, gated clocks, or the sourse and destination register clocked by two different clocks. Your state machine probably transistions from one state to another by CLK_H; and certain states within your state machine are probably creating strobes that are clocking registers. My guess is that the source and destination register are being clocked by two different signals thus giving you this error. If you really don't need a 0ns hold requirment on this path, you can utilize the Multicycle Hold assignment to get you by this timing warning. Search on "hold relationship" and "Multicycle Hold timing assignment" in the help section of Quartus. These two section should help you. <djoshi@btinternet.com> wrote in message news:1174854319.423923.143580@l75g2000hse.googlegroups.com... > Dear Sir > > I am using Quartus by ALtera, i have made my design using VHDL and > have ran it on model sim, the basic design use a state machine that > depends on a clock. each state execute some vhdl code. by when i try > synathise it i get warnings such as > > Warning: Can't achieve minimum setup and hold requirement CLK_H along > 1922 path(s). See Report window for details. > > -17.200 ns brain:I0|WRITE:I0|counter[4] rammomb:I1| > alt3pram:alt3pram_component|altdpram:altdpram_component2|q[10]~reg_wa4 > CLK_H CLK_H 0.000 ns 19.000 ns 1.800 ns > > > > please guide me on what i need to do, the design has a counter 5-bit > which is basically the inputted to the RAM address input. > > Regards > > Dharmesh Joshi >
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