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Ray Andraka wrote: (snip) > OK, fine, but even at $129-139, that is far cheaper than what it will > cost to get your own board made. You'll probably spend more than half > of that just on the components, then you've got to do the artwork, have > a board fabricated, stuff it, and debug it (which in itself is going to > be non-trivial if you havent worked with CPLDs before) before you ever > get to play with your simple design. Even if your time is worth > nothing, you'll come out ahead buying the eval board AND paying to have > it shipped to you. Except that he won't get any practice in board design, fabrication, stuffing, and debugging. -- glenArticle: 115101
On 2007-01-31, Dennis Yurichev <Dennis.Yurichev@gmail.com> wrote: > Hi. > Just interesting, does anybody used FPGA to produce real-time graphics > effects, in the spirit of demoscene? > http://en.wikipedia.org/w/index.php?title=Demo_%28computer_programming%29 I haven't heard of anything really impressive but I had some fun a couple of years ago by making a design that could show a julia fractal on a VGA screen by generating it on the fly. Something which could be impressive would be a simple physics engine that only handles spheres (but lots of them). /AndreasArticle: 115102
Hi. Just interesting, does anybody used FPGA to produce real-time graphics effects, in the spirit of demoscene? http://en.wikipedia.org/w/index.php?title=Demo_%28computer_programming%29Article: 115103
"dan" <daniel.blake2@baesystems.com> writes: > Thanks Martin. > > I am using a virtex 4 sx35. > > There are some specific details i am unsure of maybe you can help > with. > > The development board i am using has a CPLD which connects to a flash > memory and the FPGA, when i have new code i connect to the CPLD and > upload it to the flash. With every boot of the developement board the > CPLD then programs the FPGA with the code i have previously uploaded. > I also have another flash memory(completely seperate from this > programming interface) and a DDR. > > I can load my project with the bootloader application onto the board, > run it and i get various error messages(throuhgh the RS232) because i > have not loaded the main program. Now here comes the problem. The > bootloader is trying to copy data from the 4MB flash to the DDR then > run it, > What is this bootloader application? Is that on the PC or the FPGA? > 1) how do i get the real program into the 4MB flash? It seems that i > should be able to set this up as part of the hardware within the > project but i can't find a way of "initialising" the memories. Flash is a bit different in the way it has to be written to - you have to erase a whole block and then write it all at once. > 2) tutorials i've been reading tell me to use the "program flash > memory" option in the EDK, but this causes me a problem. From what i > can make out, loading data to the flash in this way requires the > hardware part of the project to be loaded on the FPGA already, does > this mean when loading data to the flash i am interacting directly to > the FPGA with the hardware part of the project? When i program my FPGA > as i mentioned earlier i don't interact with it at all but instead > interact with it via a CPLD. Can you see my problem? more > importantly....can you see my answer? You have to have the processor and all it's peripherals already running in the FPGA. When you do a "program flash" it loads a small program into the processor and that then programs the flash. You must have a supported flash configuration for htis to work, otherwise you're on your own :-( It's not that hard though! You just have to read the flash datasheets carefully. If you open the EDK helpfile and search for "flash" and then click "programming flash memory", there's a detailed guide, which also leads onto a reference to Embeddeed System Tools Reference Manual which has a chapter on flash programming... > I hope you have time to answer. > While I wait for another PAR run to complete :-) Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt - Consultancy in Engineering, Knowledge and Technology http://www.conekt.net/electronics.htmlArticle: 115104
I did a realtime fractal, but it is only a simple screen not a full demo. The fractal is calculated in realtime with the electron ray of the monitor (60Hz thus correspond to 60fps). www-user.rhrk.uni-kl.de/~alles/fpga I think doing a full featured 3D-Engine (with texturing, z-buffering, backface-culling, clipping) in an FPGA would be really nice but also a LOT of work. Some years ago I coded one on a DSP56001 that is used in the Atari Falcon030 and even that was quite a lot of work (I think about 3000 lines of assembler code - gives only a 9KB binary!) Matthias Dennis Yurichev schrieb: > Hi. > Just interesting, does anybody used FPGA to produce real-time graphics > effects, in the spirit of demoscene? > http://en.wikipedia.org/w/index.php?title=Demo_%28computer_programming%29 >Article: 115105
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message news:epo8vh$j20$1@lnx107.hrz.tu-darmstadt.de... > Thomas Reinemann <tom.reinemann@gmx.net> wrote: >> Hello, > >> we want to use a Spartan-3A to collect signals of about 100 >> differential lines. This type offers the possibility for on-chip LVDS >> termination. Is there a limit how many pairs per bank can be >> terminated via the on-chip resistor? Where may I find further >> information? > > Often LVDS on-chip Termination is a power hog on Xilinx chips. > Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It > eases layout and spares you a lot of pins. > Hi Uwe, Are you saying that LVDS uses more power than LVDS_DT from the Xilinx supplies? That surprises me. Could you point me in the direction of some documentation for this? Or maybe you're refering to the DCI modes? Thanks, Syms.Article: 115106
Symon <symon_brewer@hotmail.com> wrote: > "Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message > news:epo8vh$j20$1@lnx107.hrz.tu-darmstadt.de... > > Thomas Reinemann <tom.reinemann@gmx.net> wrote: > >> Hello, > > > >> we want to use a Spartan-3A to collect signals of about 100 > >> differential lines. This type offers the possibility for on-chip LVDS > >> termination. Is there a limit how many pairs per bank can be > >> terminated via the on-chip resistor? Where may I find further > >> information? > > > > Often LVDS on-chip Termination is a power hog on Xilinx chips. > > Consider using a multi channel LVDS transceiver. like the SN65LVDM1677. It > > eases layout and spares you a lot of pins. > > > Hi Uwe, > Are you saying that LVDS uses more power than LVDS_DT from the Xilinx > supplies? That surprises me. Could you point me in the direction of some > documentation for this? Or maybe you're refering to the DCI modes? > Thanks, Syms. I meant the problem with excessive power for LVDS with on-chip DCI termination. -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115107
>You will note all these standards use simple ON/OFF electrical keying, >with no complex signal modulation. Transmit symbol pre-shaping, and >receive signal equalization is used to maintain the eye opening in most >devices running higher than 3 Gb/s. Run length codes are used to >prevent long strings of zeroes or ones from being a challenge to IC >designers (8b10b, 64b66b). What's the thumb rule limit of electrical "on-off" signaling with current fpgas? (length, FR4/Cat.5, speed etc..) I did some calculations on ordinary S-ATA, should be able to run through 5 meters of cat.5 just barely (maybe I missed something ;). >Just one more reason why you tend to find a Xilinx FPGA inside just >about every box nowadays. Doesn't the competition have anything substantial to come with?Article: 115108
"Joel Kolstad" <JKolstad71HatesSpam@yahoo.com> wrote in message news:12rv0de39jkcp74@corp.supernews.com... > "Geronimo Stempovski" <geronimo.stempovski@arcor.de> wrote in message > news:45bf1bb4$0$27613$9b4e6d93@newsspool2.arcor-online.net... > > I'm not interested so much in those higher modulation methods (nor in > > optical transmission) but in the baseband communication where bitrate = > > clockrate, i.e. the line rate. What can be efficiently transmitted today > > electrically (over wire or PCB)? > > It's around 1Gbps that you really need to start paying attention to your board > materials, transmission lines, etc.: With inexpensive boards (e.g., FR-4), > you're at the point where you're starting to get significant loss, dispersion, > and distance limitations. If you can get the physical size of the circuit well below one wavelength then things becomes "simply" DC again (Well worth doing if you, say, happen to be building a RADAR front-end).Article: 115109
Replying (very late) in case this helps anyone else: My problem was ultimately solved by replacing the top level schematic with VHDL. Xilinx support recommended this. There was some discussion of upper case/lower case mismatches in the ED kmodule name (ppc_ddr in my case), but changing that did not help. Problem went away in an all- VHDL situation. Thanks for the suggestions in the other replies...Article: 115110
I want to order a xilinx xc9536 cpld. In one catalog I found the following 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 15ns, 100MHz XC9536-15PC44C. 384-8980 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 10ns, 100MHz, 3.3V (IND TEMP) XC9536XL-10PC44C 384-9016 What are the 15ns and 10ns respectively refer to ?Article: 115111
On Jan 30, 11:48 am, "idp2" <ian.pei...@gmail.com> wrote: > Yea, I figured that was the case. However, I have no always > statements that are not of the form: > > always @(posedge clk) > begin > foo <= bar > end > > all of my always statements are driven off of clock. I do have if > statements within the always statements that depend on rst. will this > cause it to be seen as a clock? > If the always block is not a clocked block, i.e. always @* it is possible to create latches. In the FPGA fabric the gate input of a latch uses the clock routing. Did you check if there were any transparent latches created in synthesis?Article: 115112
On Jan 30, 1:52 am, Daniel O'Connor <dar...@dons.net.au> wrote: > billu wrote: > > Any ideas/pointers on how i can get started on a setup like this. So, > > the USB 2.0 on the XUPV2P might not be able to support 480Mbps. What > > USB chipset can I use to get the maximum transfer rate, and how would > > I interface the chipset w/ the PC/FPGA? > > Try looking up the USRP. > > That uses a Cypress chip connected to a Cyclone II and appears to work > reasonably well, although there are plenty of caveats with USB :( Yes, based on their reported success I'm being very tempted to order some of the Digilent NEXYS boards which pair the cypress chip with an XC3S1000 FPGA. There are some other boards around like the Xylo at FPGA4FUN, but this is the best deal I've seen so far from a vendor that won't require trying to talk the purchasing department into playing with paypal. Anyone used the NEXYS board? As for the OP's needed SMA connector - it's a connector for crying out loud. Worry about the board functionality, you can patch any connector you want on there. I think digilent even sells a BCD connector you can plug into one of the expansion ports, and get a BCD to SMA adapater somewhere.Article: 115113
What are the requirements of the application at a high level? You need to move data from a PC (hard drive, memory, algorithmically generated...) to some device (?) using _______ protocol / physical layer interface..? Minimum data bandwidth from the PC to the device is ________? The device will (not?) communicate/handshake back to the PC using said protocol? etc. -RB On Jan 30, 11:49 am, "billu" <bkama...@gmail.com> wrote: > Thx for everyones input. > > It looks like the PC is going to be the real bottleneck in the whole > setup. So assuming a maximum data rate of around 240 Mbits/sec, whats > the best way to interface the PC data stream with the SMA interface. > This is what came to my mind. Cypress FX2 board takes in a data stream > from the PC, and the slave fifo interface sends the data to the FPGA. > The FPGA takes in the data and sends it out through the SMA MGTs. Is > this reasonable? Any pointers on working with FX2-FPGA board setups. > Can a Xilinx ML321 board be used? > > As far as requirements: > * Throughout: Maximum possible data rate > * Latency: Would like it to be small, but not critical > * Ease of use: Somewhat important, but not the driving factor > * Ubiquity: Again somewhat important, b/c we would like to > communicate between PC-PC or PC-Smartphone using a USB port. > > Really appreciate everyones response.Article: 115114
carshie wrote: > I want to order a xilinx xc9536 cpld. In one catalog I found the following > 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 15ns, 100MHz > XC9536-15PC44C. 384-8980 > 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 10ns, 100MHz, 3.3V (IND > TEMP) XC9536XL-10PC44C 384-9016 > What are the 15ns and 10ns respectively refer to ? Did you take a look at the datasheets? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115115
"> Doesn't the competition have anything substantial to come with?" Competition is always there. Just visit the each vendor's websites to see their offerings. Not every implementation is the same: some use more power, some less. Some have more built in hardware function, some less. Xilinx may have been the first to place the gigabit transceivers on a FPGA, but that was years ago now, and offerings of FPGA with transceivers is common today. I would like to think that PCIe+MGT+65nm+lowest power (Virtex 5 LX, LXT shipping NOW) is a substantial offering, and the soonest any serious competition is expected (from their hasty press releases) is late this year (end of 2007). So the simple answer for 65nm? No, Xilinx is now one full year ahead of its competition. There is absolutely no competition for a 65nm FPGA socket. We are shipping, and no one else is, nor will they be for a very long time. If you mean does anyone have gigabit transceivers, then the answer is yes, and there is plenty of competition. AustinArticle: 115116
Good question. It's the pin-to-pin logic delay of the device.
XC95xx come in several sizes (macrocells) each size is tested and given a
speed rating, -10, -7, -15 etc. This figure is the tpd in nanoseconds: you
can expect to pay more for the faster devices, but with the benefit that you
can run them at a higher frequency. The way to distinguish them is in the
part number
XC95288-10HQ208C
^^^^^^^^ = 288 macrocell xc9500
^^^ = 10ns tpd
^^^^^^^= 208 PQ package with heat sink
^ = commercial temperature grade
One vital thing to note is that this is NOT the same as FPGA markings, FPGA
have a speed grade, which does not directly correspond to any tpd, and
higher numbers are FASTER, the opposite of CPLD markings (from my
experience)
Just my 2p
Ben
The silicon is qualified in terms of gate delay,
"Uwe Bonnes" <bon@hertz.ikp.physik.tu-darmstadt.de> wrote in message
news:epqdaj$ngp$1@lnx107.hrz.tu-darmstadt.de...
> carshie wrote:
>> I want to order a xilinx xc9536 cpld. In one catalog I found the
>> following
>
>> 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 15ns, 100MHz
>> XC9536-15PC44C. 384-8980
>
>> 9536 XLX 44 PLCC In-system Programmable FLASH CPLD, 10ns, 100MHz, 3.3V
>> (IND
>> TEMP) XC9536XL-10PC44C 384-9016
>
>> What are the 15ns and 10ns respectively refer to ?
>
> Did you take a look at the datasheets?
>
> --
> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de
>
> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
Article: 115117I'm planning an FPGA design that will be using SDRAM (DDR Winbond W9425G6DH5) and NAND Flash (ST NAND018W3B2AN6E). I'm not particularly experienced in DDR memory design and there are other issues that need my attention other then just DDR RAM design. I keep hearing horror stories about engineers getting into trouble with DDR RAM designs. Do you have any experience integrating DDR to FPGAs and how do you recommend I kkep out of trouble. ThanksArticle: 115118
Hello, Since any datapath design is essentially a control statemachine, I was wondering about the following: Say I have a certain DSP function to implement. If I'm to specify literally every single statement to be carried out in a certain state and carry on to fill the whole datapath control statemachine, do you think that the synthesizer (and subconsequently the implementer) will do a good job in extracting and minimizing the design as a whole. I tried it out on fairly simple designs (FIR filter), and apparently there isn't much difference in terms of logic occupancy nor in terms of timing compared to an equivalent design based on Xilinx core generator (ISE 8.1). I know that an FIR filter case is far from being a faithful benchmark and this is basically why I'm seeking counselling on this issue from the gurus in here. If this turned out to be promising, I intend to write a tool to basically fill in a template statemachine with desired tasks (accounting for everything including pipelining) and let the CAD tools worry about the rest. Would be great to hear opinions on this. Many thanks, Cheers, -MannyArticle: 115119
> Did you take a look at the datasheets? Having looked in the datasheet (belatently) there is another question, in the top of the datasheet the pin to pin delay is quoted as 5ns, then down below we see also 6ns 7ns 10ns 15ns. So do they mean to say that 5ns is the fastest one, but slower one are also available? Another question, I have here a xc9536 which has the following marking xc9536 tm pc44amm0521 f3002413a 7c What speed would it be? I can't find the ordering number on the part, or should have I made a note of it when I bought it (so how would I to know if my supplier did not send me a different spec?) > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 115120
I can't find any help files about schematic entry, please advise?Article: 115121
oopps, found it!!Article: 115122
Carshie, See Answer Record 1067. It will be able answer all your questions regarding to part markings: http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=1067 -David <carshie> wrote in message news:45c0c8d3_3@mk-nntp-2.news.uk.tiscali.com... >> Did you take a look at the datasheets? > > Having looked in the datasheet (belatently) there is another question, > in the top of the datasheet the pin to pin delay is quoted as 5ns, then > down below we see also 6ns 7ns 10ns 15ns. So do they mean to > say that 5ns is the fastest one, but slower one are also available? > > Another question, I have here a xc9536 which has the following marking > > xc9536 tm > pc44amm0521 > f3002413a > > 7c > > What speed would it be? I can't find the ordering number on the part, > or should have I made a note of it when I bought it (so how would I > to know if my supplier did not send me a different spec?) > > >> >> -- >> Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de >> >> Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt >> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ---------- > >Article: 115123
Mounard Le Fougueux <blinkingCursor@NonEventHorizon.com> wrote: >I'm planning an FPGA design that will be using SDRAM (DDR Winbond >W9425G6DH5) and NAND Flash (ST NAND018W3B2AN6E). I'm not particularly >experienced in DDR memory design and there are other issues that need my >attention other then just DDR RAM design. > >I keep hearing horror stories about engineers getting into trouble with >DDR RAM designs. Do you have any experience integrating DDR to FPGAs and >how do you recommend I kkep out of trouble. Be realistic and don't let yourself fooled by succes stories. If you stay within the timing limits of the FPGA, you'll be just fine. And remember: there are no free DDR implementations available. So either roll your own or buy one. Clocking the data from the memory is an issue if you use fpga's. Timing may vary a bit from device to device. The more layers of logic you add to the data input path, the bigger the variation in timing, the worse things get (this is why the MIG tool from Xilinx makes such a kludge of a DDR implementation). Use the flipflops in the IO cell to clock the data into the fpga. If you take all the timing variations and jitter into account, you can determine a window (with respect to the DDR clock) in which the data will be stable. The only thing you need is a (shifted) clock with an edge inside that window. If you can't get the window big enough, lower the frequency or use a faster fpga. -- Reply to nico@nctdevpuntnl (punt=.) Bedrijven en winkels vindt U op www.adresboekje.nlArticle: 115124
The final 7c stands for "speed-grade 7, commercial temperature grade, 0 to 70 degrees centigrade) Peter Alfke On Jan 31, 8:50 am, <carshie> wrote: > > Did you take a look at the datasheets? > > Having looked in the datasheet (belatently) there is another question, > in the top of the datasheet the pin to pin delay is quoted as 5ns, then > down below we see also 6ns 7ns 10ns 15ns. So do they mean to > say that 5ns is the fastest one, but slower one are also available? > > Another question, I have here a xc9536 which has the following marking > > xc9536 tm > pc44amm0521 > f3002413a > > 7c > > What speed would it be? I can't find the ordering number on the part, > or should have I made a note of it when I bought it (so how would I > to know if my supplier did not send me a different spec?) > > > > > -- > > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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Compare FPGA features and resources
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