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On Feb 1, 9:52 am, "Quesito" <francesco_poder...@yahoo.com> wrote: > I've tryed ISE9.1 SP1.. and it crash!!! > Then I come back with ISE8.2... and I can't open my old projects!!! Your projects should be in some sort of source-code control system, which will easily allow you to go back to any arbitrary version. -aArticle: 115176
On Feb 1, 5:03 pm, LT1...@yahoo.com wrote: > On Feb 1, 4:20 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > > > On the Spartan-3E, LVPECL is input only! > > Right, the supported output is "LVDS_25". I suspect that the outputs > "want" to be symmetrical around VCCO/2, which is the 1.25V VCM of > LVDS_25. LVPECL has a different common mode voltage. > > > This may contribute to why you find no 3.3V compliant standards in the data > > sheet. > > Agreed. What I'm not clear on is what changes are made to the output > structure to shift things around. Presumably, a stronger pull-up > device and weaker pull-down would give the needed behavior, but I > wonder if this couldn't just be done with a resistor network, assuming > the swings are sufficient? > > > The 3.3V LVPECL standard's last foot in the Spartan series was the > > Spartan-IIE. The Spartan-3 tried an LVPECL_25 version that wasn't continued > > into later parts. Odds don't look good in your favor. > > We're trying to replace a Spartan-IIE. In that device, the > differential outputs seemed to swing rail-to-rail (I think), and you > just controlled the output swings and common-mode with output > resistors if needed. I'm wondering if I can do this here? > > Or does the Spartan 3E really control the swings internally? > > One last thought... > > Can I simply program the two pins of a differential pair as single- > ended LVCMOS_33, and just drive one with an inverted signal? The full- > voltage output swing does not bother me at all - five resistors (two > up, two down, one across) will get me to LVPECL_33 levels. Only issue > is whether I'm taking my chances with skew between the outputs. Using external resistors is the usual approach to differential outputs where the chip doesn't support your standard directly. Lattice parts use this for LVDS as well as LVPECL on some outputs. The issue of output skew is more important, however. If your outputs are clocked in the IOB flip-flops, the skew between two outputs in an IOB pair is negligible. If the outputs go to the pad from a fabric register, possibly via logic (inverter?) you'll most likely run into too much skew. I don't know if you can use the direct differential path between the IOB's in a pair unless you use one of the differential standards. HTH, GaborArticle: 115177
On Feb 1, 5:28 pm, "Gabor" <g...@alacron.com> wrote:
> On Feb 1, 5:12 pm, "idp2" <ian.pei...@gmail.com> wrote:
>
>
>
> > I am constantly getting the following warnings when compiling in
> > Xilinx:
> > FF/Latch <thresh_0> (without init value) has a constant value of 0 in
> > block <calibrate>
>
> > I do not understand why this happens since I set thresh to 0 on rst
> > signal.
> > Here's my code:
>
> > //determine the threshold value
> > reg[7:0] thresh;
> > always @(posedge clk)
> > begin
> > if(~done & stepCnt==2 & cal_cnt==3 & sampCtr==511)
> > thresh <= mean8*ALPHA;
> > else if(rst)
> > thresh[7:0] <= 8'h00;
> > end
>
> > Thanks,
> > Ian
>
> What you describe does not have an asynchronous reset term, which
> may cause the "without init value", but the real point of the warning
> is that
> bit 0 of thresh doesn't ever become nonzero, not that there is no init
> value. I'm guessing that either mean8 or ALPHA is always even?
Yes ALPHA is always even. Thanks. However, Due to other FF/Latch
trimming, FF/Latch <thresh_1> (without init value) has a constant
value of 0 in block <calibrate> has also come up as a warning which I
do not understand. And finally, FFs/Latches <PCI_DMAoutaddr<31:1>>
(without init value) have a constant value of 0 in block <pci_pnp>
also comes up which corresponds to the following code:
always @(posedge PCI_CLK)
begin
if(~PCI_RSTn)
begin
PCI_DMAaddr <= 0;
DMAwordsWritten <=0;
unrelated foos <= 0;
end
end
wire outaddr = PCI_DMAaddr + {17'b00000000000000000,
DMAwordsWritten[12:0], 2'b00};
always @(posedge PCI_CLK)
begin
if(~PCI_RSTn)
PCI_DMAoutaddr <= 0; //this might work??
else
PCI_DMAoutaddr <= outaddr;
end
Why is PCI_DMAoutaddr coming up without init value??
Thanks.
Ian
From invalid@dont.spam Thu Feb 01 15:03:11 2007
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From: Phil Hays <invalid@dont.spam>
Subject: Re: Webpack 9.1 problems with Impact on parallel cable
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Newsgroups: comp.arch.fpga
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Andy Peters wrote:
> On Feb 1, 9:52 am, "Quesito" <francesco_poder...@yahoo.com> wrote:
>> I've tryed ISE9.1 SP1.. and it crash!!! Then I come back with ISE8.2...
>> and I can't open my old projects!!!
>
> Your projects should be in some sort of source-code control system, which
> will easily allow you to go back to any arbitrary version.
Not everyone knows what a source control system is. As an example, I use
this one:
http://subversion.tigris.org/
As Francesco seems to be on windows, I'd also suggest this:
http://tortoisesvn.tigris.org/
If Francesco was using subversion, then he would recover after:
svn revert projectname.ise
Or a couple of mouse clicks using tortoisesvn.
Would have been much easier and faster than posting to comp.arch.fpga.
Hope that helps.
--
Phil Hays (Xilinx, but posting for myself)
Article: 115178Hello, I am working with an unusual board that has two Xilinx Virtex 4 FX60's on it in a top/bottom mirrored configuration. (The BGA's are mounted above/below each other, with via's running between select pins to form mirrored pairs) The problem I am running into is that both FPGA's must run identical firmware loads, and in some cases, this results in contention due to the mirrored pins. I do have a strap bit that can tell the design whether it is loaded in the top or bottom fpga, which I use to remap the inputs. (ie, in the top part, pin AG30 is used as the input, and in the bottom part, AG5 is used instead) These input muxes work fine using a similar concept. The idea is that the fpga ID pin can be used to forcibly tri-state certain outputs in either the top or bottom design to prevent the contention. Since the fpga ID pin is an external input, the designs should be able to remain the same. So, I created an EDK ip core in VHDL that instantiates an OBUFT, and connected it between the user logic and the external net. The VHDL is simply a wrapper. (I did implement a for/generate block to handle vectors) The problem is that ISE is turning it into a LUT based AND gate instead, so I still get the contention. When I look at the pad in FPGA Editor, the T input is not mapped. I'm using ISE/EDK 8.2.03i for this project. Any ideas? Thanks!Article: 115179
spartan3wiz wrote: > Another very interesing subject would be FPGA-MAME! > Or maybe a FPGA-MESS would be even more interesing! Well what do > think? I think that's a stupid idea! ;) <http://members.iinet.net.au/~msmcdoug/pace/platforms/platforms.html#Downloads> Note: no downloads there yet... Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 115180
Along with Gabor's comments, the BLVDS_25 differential output maintains the Spartan-IIE style of full-swing output requiring the familiar resistor network to get the appropriate drive levels. You can have the rail-to-rail 2.5V outputs but with a lower bandwith than the native limited-swing differential standards. <LT1Z07@yahoo.com> wrote in message news:1170367386.830858.125810@a75g2000cwd.googlegroups.com... > On Feb 1, 4:20 pm, "John_H" <newsgr...@johnhandwork.com> wrote: >> On the Spartan-3E, LVPECL is input only! > > Right, the supported output is "LVDS_25". I suspect that the outputs > "want" to be symmetrical around VCCO/2, which is the 1.25V VCM of > LVDS_25. LVPECL has a different common mode voltage. > >> This may contribute to why you find no 3.3V compliant standards in the >> data >> sheet. > > Agreed. What I'm not clear on is what changes are made to the output > structure to shift things around. Presumably, a stronger pull-up > device and weaker pull-down would give the needed behavior, but I > wonder if this couldn't just be done with a resistor network, assuming > the swings are sufficient? > >> The 3.3V LVPECL standard's last foot in the Spartan series was the >> Spartan-IIE. The Spartan-3 tried an LVPECL_25 version that wasn't >> continued >> into later parts. Odds don't look good in your favor. > > We're trying to replace a Spartan-IIE. In that device, the > differential outputs seemed to swing rail-to-rail (I think), and you > just controlled the output swings and common-mode with output > resistors if needed. I'm wondering if I can do this here? > > Or does the Spartan 3E really control the swings internally? > > One last thought... > > Can I simply program the two pins of a differential pair as single- > ended LVCMOS_33, and just drive one with an inverted signal? The full- > voltage output swing does not bother me at all - five resistors (two > up, two down, one across) will get me to LVPECL_33 levels. Only issue > is whether I'm taking my chances with skew between the outputs. >Article: 115181
"Fred" <fred@n0spam.com> wrote in message news:1170332691.17553.0@iris.uk.clara.net... >I know there is a PCI-Express newsgroup but there are very few posts of any >relevance to PCI Express itself. > > Is there another newsgroup more dedicated to the workings of PCI Express? > > I have the following question: What happens when a mal formed packet is > received? The transmitter CC will be incremented but the CL (which is the > CA received from the receiver) will not be incremented such that the > apparent size of the available space in the receive buffer will decrease > with no mechanism to correct itself. Am I correct? > > > What does CC, CL and CA stand for? I'm familiar with PCI Express but not these acronyms.Article: 115182
I think what Nico was trying to say is you get what you pay for. In my experience, the free DDR designs are generally not worth much. Either they only support basic operation, or they won't work at full speed, or they are so littered with bugs that you are better off starting from scratch. Yes, there are "free" cores out there, but you'll likely put as much effort into getting them to work in your design as you would starting with a clean sheet.Article: 115183
Can anybody tell me how to read the contents of the FPGA? I am working on xupv2p development board and after I download data to the fpga I want to read back its contents. Thank youArticle: 115184
I want to use a DDR SDRAM on my virtex 2 pro platform; however the vhdl controller available is for a 256Mb micron SDRAM; mine is a kingston kvr266x64c25/512 with 512MBytes ( actually 64Mx64). Can anyone help me? is it possible to adapt the opencore controller for my SDRAM? how??Article: 115185
I'm about to use an APA1000 with Actels implementation of dual port RAMs. These require the use of the PLL to create a X2 clock. My input clock is 33MHz, but this goes to another FPGA as well, and the skew between the two chips must be kept to a minimum. So, will the PLL output of 66MHz have its rising edges coincident with the edges of the 33MHz clock? Anyone had experience of using these PLLs, good or bad. Regards, Niv.Article: 115186
I don't think is so simple Phil... I did backed up my project before use 9.1! Yes ISE 9.1 for default open your old project but also ask you "This project was made with an older version of ISE do you want to open?" (or a similar message) And I pressed "NO"... Maybe ISE 9.1 said Did you pressed NO? I don't care I'll open anyway.. I'm not the only person in my company having this sort of problem and we are very sceptic on 9.1.. and waiting now for the SP2! I belieave that you guy at Xilinx are excelent engineer... but this sort of negative feedback must be taken seriously from you. It is actually the first time in 6 years that I'm starting to think to swtitch to Altera! FrancescoArticle: 115187
On Feb 2, 1:09 am, Mark McDougall <m...@vl.com.au> wrote: > spartan3wiz wrote: > > Another very interesing subject would be FPGA-MAME! > > Or maybe a FPGA-MESS would be even more interesing! Well what do > > think? > > I think that's a stupid idea! ;) > > <http://members.iinet.net.au/~msmcdoug/pace/platforms/platforms.html#D...> > > Note: no downloads there yet... > > Regards, > > -- > Mark McDougall, Engineer > Virtual Logic Pty Ltd, <http://www.vl.com.au> > 21-25 King St, Rockdale, 2216 > Ph: +612-9599-3255 Fax: +612-9599-3266 Of all sites I've been to I've actually missed that one... :-) Of course, someone has already thought of it. Sorry to see that the site hasn't got more attention. A prime start of such a mission is to base the main branch work on a cheap and capable board and offer (sell) upgrades so that anyone can get their hands on working key- hardware cheaply and simple. After that, I think there might be a possiblity to build a small Community of Gamers/Testers/Enthusiasts that could attract even more implementers to add man hours in implementing new "circuits". And yes I'm just looking into a suitable add-on board for my FPGA-card.. I still like my thoughts of using Partial Reconfiguration... maybe it's not a "better" solution but more interesting. But of course maybe it would be good enough to be able to do RAM/ROM- insertion-changes into already pre-compiled bitstreams to be able to play all games on a particular Arcade platform. That would demand that ALL different Arcade platforms had pre-compiled bitstreams. A cooler solution would be to have a main FPGA-MAME framework as a static partial reconfguration block, that care for both instanciating the blocks neeeded for a particular platform and also injects tha ROM/ RAM needed for that platform. The end result would be a generic hardware-platform, that would have big similarities with the current software-based MAME. For some logical circuits included in the MAME- community maybe the most gate-economical way of implementing it would be to spawn a small microcontroller and just use the c sourcecode from MAME compiling it for that particular microcontroller ... :-) Sorry to mumble about MAME and MESS in a thread that asked for a demo- scene.. back to the original question. YES there could really be a demoscene in the FPGA-world! It would be GREAT! /MArticle: 115188
I was a TA for an introductory VHDL lab yesterday and
I encountered a very weird problem. In the source code
included below I get the following interesting messages
from XST when I try to synthesize the file:
INFO:Xst:1799 - State start is never reached in FSM <stage>.
INFO:Xst:1799 - State stop is never reached in FSM <stage>.
INFO:Xst:1799 - State data_1 is never reached in FSM <stage>.
INFO:Xst:1799 - State data_2 is never reached in FSM <stage>.
INFO:Xst:1799 - State data_3 is never reached in FSM <stage>.
INFO:Xst:1799 - State data_4 is never reached in FSM <stage>.
and
WARNING:Xst:1710 - FF/Latch <timer_3> (without init value) has a constant value of 0 in block <transmitter>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <timer_2> (without init value) has a constant value of 0 in block <transmitter>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <timer_1> (without init value) has a constant value of 0 in block <transmitter>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <timer_0> (without init value) has a constant value of 0 in block <transmitter>.
Personally I cannot see any reason why stage shouldn't leave
the waiting state. On the other hand I might just have missed
something blindingly obvious. If I simulate the design in
ModelSim it does leave the waiting state immediately. I don't
get any such messages if I try to synthesize to for example a
Virtex 4.
The sad thing is that this is the first time the students were
exposed to Xilinx tools and VHDL and I fear that the first
impression wasn't very good :(
In ISE 7.1, 8.1, and 9.1 for Linux xst gives the same warnings.
ISE 6.3 for Solaris does not emit any warning however.
8.1 for Windows also gives the warnings about the timer but I
haven't double checked that they give the same INFOs for the
stage signal.
Do we have to go back to ISE 6.3 to have functioning XC9536
support?
I guess this posting is mainly a way to vent some irritation,
but I do hope that someone at Xilinx sees this because the
last time I tried to report a possible bug to Xilinx my
request for a webcase account was denied. (At that time they
referred me to the University program forums and I never
got any useful reply to my message.)
/Andreas
------------------------------------------------------
-- The following code has been modified somewhat
-- by removing as much stuff as possible while still
-- retaining the problematic code.
------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity transmitter is
port( clk: in std_logic;
reset: in std_logic;
debug:out std_logic_vector(1 downto 0));
end transmitter;
architecture arch of transmitter is
type state is (waiting, start, data_1, data_2, data_3, data_4, stop);
signal stage: state;
signal timer: std_logic_vector(3 downto 0);
begin
process(clk)
begin
if rising_edge(clk) then
timer <= timer+1;
if ((stage=waiting)) then
timer<="0000";
stage<=start;
elsif timer="1111" then
if stage=stop then stage <= waiting;
elsif stage=start then stage <= data_1;
elsif stage=data_1 then stage <= data_2;
elsif stage=data_2 then stage <= data_3;
elsif stage=data_3 then stage <= data_4;
elsif stage=data_4 then stage <= stop;
end if;
end if;
if reset='1' then
timer<="0000";
stage<=waiting;
end if;
end if;
end process;
debug(1) <= '0' when stage=waiting else '1';
debug(0) <= timer(3);
end arch;
Article: 115189"nana" <nmichou@utk.edu> wrote in message news:1170388556.873878.192840@v33g2000cwv.googlegroups.com... > Can anybody tell me how to read the contents of the FPGA? > I am working on xupv2p development board and after I download data to > the fpga I want to read back its contents. > Thank you > Google readback fpga site:xilinx.comArticle: 115190
"John_H" <newsgroup@johnhandwork.com> wrote in message news:12s4mc8mffujk8b@corp.supernews.com... > On the Spartan-3E, LVPECL is input only! > > The issue of running 2.5V standards at 3.3V reliably really should be > taken up directly with your FAE rather than with this newsgroup. If it > were a "sure, yeah, anyone can do it" issue, wouldn't the parts already be > characterized that way? > Hi John, Maybe, maybe not. Xilinx are only going to charactarise things to a proper spec. LVDS outputs are symtetrical about 1.2V ish, so they'll charactarise for LVDS with Vcco = 2.5V. I bet the outputs work fine with 3.3V Vcco, but then the outputs aren't meeting any published standard for Xilinx to charactarise against. However, this might well be good enough for someone's application, especially now modern LVDS receiver parts generally have a very wide common mode range. It could help out the OP who is understandably peeved about the bank requirements. Of course, you're quite correct, the FAE needs to confirm all this. Cheers, Symon.Article: 115191
On Jan 31, 2:49 am, "Shant" <shantchandra...@gmail.com> wrote: > Hi All, > > I am a Newbie and I am trying to load my C program on an FPGA using > through EDK 8.1i without using BSB (since it does not support multiple > processors). I am using Xilinx's ML310 development board for the same > and. I am using Jtag cable for connection. After downloading my > program on the FPGA and launching XMD I am getting the following > messages: > > Xilinx Microprocessor Debug (XMD) Engine > Xilinx EDK 8.1.02 Build EDK_I.20.4 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > > XMD% > Loading XMP File.. > Processor(s) in System :: > > Microblaze(1) : microblaze_0 > Address Map for Processor microblaze_0 > (0x00000000-0x00001fff) lmb_bram_if_cntlr_1 lmb_v10_0 > (0x00000000-0x00001fff) lmb_bram_if_cntlr_0 lmb_v10_1 > (0x80000000-0x800000ff) opb_uartlite_0 opb_v20_0 > (0x80000100-0x800001ff) opb_mdm_0 opb_v20_0 > > Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > Driver windrvr6.sys version = 7.0.0.0. LPT base address = 0378h. > ECP base address = 0778h. > ECP hardware is detected. > Cable connection established. > Connecting to cable (Parallel Port - LPT1) in ECP mode. > Checking cable driver. > Driver xpc4drvr.sys version = 1.0.4.0. LPT base address = 0378h. > Cable Type = 1, Revision = 3. > Setting cable speed to 5 MHz. > Cable connection established. > > JTAG chain configuration > -------------------------------------------------- > Device ID Code IR Length Part Name > 1 0a001093 8 System_ACE > 2 0127e093 14 XC2VP30 > Assuming, Device No: 2 contains the MicroBlaze system > Connected to the JTAG MicroProcessor Debug Module (MDM) > No of processors = 1 > > UNKNOWN Processor Version (0) > Verify if FPGA Bitstream was downloaded and DONE pin went High > > During download process, LEDs for OPB ERR and PLB ERR becomes Red for > a while and then becomes green again. Once the Download process > finishes, the INIT LED goes Low and DONE LED goes Green. > For Verifying the download, I also tried downloading my program > through iMPACT and doing the verification afterwards, but then also I > am getting the same message again. > > Apart from this, the tutorial also asks for invoking the HyperTerminal > before starting the download process, I also did the same using COM1 > (after connecting the serial port cable ) with > Baud rate of 9600, > Data 8 bits, > Parity None, > Stop 1 and > Flow Control None > > And it mentions about the print statements getting displayed on the > HyperTerminal. But I could not see anything on the HyperTerminal. > > I am not in a position to understand why it is happening. So please > suggest your expert comments on this problem of mine. > > Thanks, > Shant Chandrakar Hi, It might be that PPC is not coming out of RESET check your reset block. Most of the time its reset problem. You can also check if your DCM's are locking correctly and they are correctly configured. Check this and regenerate bit file and try again. Enjoy.. AshishArticle: 115192
I think you really found a bug in XST. Switch FSM Extraction to "none" and it seems to work. Best regards Klaus FalserArticle: 115193
"TC" <noone@nowhere.com> wrote in message news:11wwh.19701$w91.12306@newsread1.news.pas.earthlink.net... > > "Fred" <fred@n0spam.com> wrote in message > news:1170332691.17553.0@iris.uk.clara.net... >>I know there is a PCI-Express newsgroup but there are very few posts of >>any relevance to PCI Express itself. >> >> Is there another newsgroup more dedicated to the workings of PCI Express? >> >> I have the following question: What happens when a mal formed packet is >> received? The transmitter CC will be incremented but the CL (which is >> the CA received from the receiver) will not be incremented such that the >> apparent size of the available space in the receive buffer will decrease >> with no mechanism to correct itself. Am I correct? >> >> >> > > What does CC, CL and CA stand for? > > I'm familiar with PCI Express but not these acronyms. > > Some literature use the following CC = Credits Consumed CL = Credit Limit CA = Credits Allocated Hope this helps.Article: 115194
On Feb 1, 7:40 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > Along with Gabor's comments, the BLVDS_25 differential output maintains the > Spartan-IIE style of full-swing output requiring the familiar resistor > network to get the appropriate drive levels. You can have the rail-to-rail > 2.5V outputs but with a lower bandwith than the native limited-swing > differential standards. We're not trying to break any speed records here, just need the speed and noise suppression of a differential signal to outside logic. The Spartan-IIE design we're replacing worked just fine. Is there published info that confirms BLVDS_25 uses full-swing outputs? I couldn't find any mention of this in the Spartan3E datasheet, just "figure 72" showing a resistor network for testing. I actually prefer full-swing outputs so I can tune my swings and common mode with resistors - one of the outputs is not going to logic, but to a differential current-steering transistor pair. I could tell you why, but then I'd have to kill you all... Thanks for all the replies - guess I'll try to get in touch with an FAE on this to get the "definitive word".Article: 115195
<LT1Z07@yahoo.com> wrote in message news:1170425926.998103.189140@k78g2000cwa.googlegroups.com... > We're not trying to break any speed records here, just need the speed > and noise suppression of a differential signal to outside logic. The > Spartan-IIE design we're replacing worked just fine. Is there > published info that confirms BLVDS_25 uses full-swing outputs? I > couldn't find any mention of this in the Spartan3E datasheet, just > "figure 72" showing a resistor network for testing. Is there any published info that confirms the pre-Spartan-3 LVDS outputs (which need the resistor networks) are full swing? You can probably find the full-swing information only in the IBIS files where the information isn't spelled out too clearly for the casual reader. The info should be there, though, hard to interpret as it may be. For doing any cute resistor tricks to get anything except LVDS levels out of there, it might be handy to use IBIS simulations making that model a valuable resource.Article: 115196
Hi, I'm just wondering how many people here are using ISE 9.1. Could you post your experience here? Antii what do you think? Is really 6 time faster? I tryed unsuccesfully to use ISE 9.1 SP1...unfortunately in my case the tool crashed with the message error: "Runtime error" I tryed a few time unsuccesfully.... Now I'm back on ISE 8.2 Thanks eveybody, Francesco PS: please post here even if you are using Webpack 9.1Article: 115197
Hi, Does anyone know how to implemtent circle generation algorithm in verilog? i want to implement it in spartan 3 kit,for VGA pattern generator. i don't want to use ROM and RAM. please, reply as soon as possible From invalid@dont.spam Fri Feb 02 06:59:30 2007 Path: newsdbm05.news.prodigy.net!newsdst01.news.prodigy.net!prodigy.com!newscon04.news.prodigy.net!prodigy.net!newsfeed.telusplanet.net!newsfeed2.telusplanet.net!newsfeed.telus.net!cycny01.gnilink.net!spamkiller2.gnilink.net!gnilink.net!trndny07.POSTED!933f7776!not-for-mail From: Phil Hays <invalid@dont.spam> Subject: Re: Webpack 9.1 problems with Impact on parallel cable User-Agent: Pan/0.14.2.91 (As She Crawled Across the Table) Message-Id: <pan.2007.02.02.15.03.18.548036@dont.spam> Newsgroups: comp.arch.fpga References: <1170348508.967318.22380@j27g2000cwj.googlegroups.com> <1170348761.233534.224400@m58g2000cwm.googlegroups.com> <1170369047.105495.235160@l53g2000cwa.googlegroups.com> <pan.2007.02.01.23.06.57.132464@dont.spam> <1170410413.209375.236100@k78g2000cwa.googlegroups.com> MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 8bit Lines: 43 Date: Fri, 02 Feb 2007 14:59:30 GMT NNTP-Posting-Host: 71.112.133.239 X-Complaints-To: abuse@verizon.net X-Trace: trndny07 1170428370 71.112.133.239 (Fri, 02 Feb 2007 09:59:30 EST) NNTP-Posting-Date: Fri, 02 Feb 2007 09:59:30 EST Xref: prodigy.net comp.arch.fpga:126601 Francesco wrote: > I don't think is so simple Phil... > I did backed up my project before use 9.1! Yes ISE 9.1 for default open > your old project but also ask you "This project was made with an older > version of ISE do you want to open?" (or a similar message) And I > pressed "NO"... > Maybe ISE 9.1 said Did you pressed NO? I don't care I'll open anyway.. > I'm not the only person in my company having this sort of problem and > we are very sceptic on 9.1.. > and waiting now for the SP2! > > I belieave that you guy at Xilinx are excelent engineer... but this sort > of negative feedback must be taken seriously from you. It is actually > the first time in 6 years that I'm starting to think to swtitch to > Altera! Francesco, I'm a little person at Xilinx. I've designed using Xilinx FPGAs for about 15 years, and have worked for Xilinx for less than a year. I have much more experience giving feedback than getting feedback. As a long time user of Xilinx's software and FPGAs, I have given feedback to Xilinx in many ways and on many topics. Xilinx, as a whole, has listened well and has taken this feedback seriously. I don't think that I was listening well to your feedback. Thinking as a long time user of FPGAs, I replied to Andy Peters comment to suggest a specific source control program. Bad things happen. Not only can software behave badly, and not only Xilinx's software, but also I make mistakes and need to recover from them. A source control program allows for quick and graceful recovery from many of these problems. I have been suggesting use of source control programs (cvs, svn and many others) for years. I used your problem as an example of why using a source control program would be a good habit. This was rude of me, I'll try to listen better in the future, please forgive me. -- Phil Hays (Xilinx, as usual, writing for myself)Article: 115198
On Feb 1, 5:40 pm, "idp2" <ian.pei...@gmail.com> wrote:
> On Feb 1, 5:28 pm, "Gabor" <g...@alacron.com> wrote:
>
>
>
> > On Feb 1, 5:12 pm, "idp2" <ian.pei...@gmail.com> wrote:
>
> > > I am constantly getting the following warnings when compiling in
> > > Xilinx:
> > > FF/Latch <thresh_0> (without init value) has a constant value of 0 in
> > > block <calibrate>
>
> > > I do not understand why this happens since I set thresh to 0 on rst
> > > signal.
> > > Here's my code:
>
> > > //determine the threshold value
> > > reg[7:0] thresh;
> > > always @(posedge clk)
> > > begin
> > > if(~done & stepCnt==2 & cal_cnt==3 & sampCtr==511)
> > > thresh <= mean8*ALPHA;
> > > else if(rst)
> > > thresh[7:0] <= 8'h00;
> > > end
>
> > > Thanks,
> > > Ian
>
> > What you describe does not have an asynchronous reset term, which
> > may cause the "without init value", but the real point of the warning
> > is that
> > bit 0 of thresh doesn't ever become nonzero, not that there is no init
> > value. I'm guessing that either mean8 or ALPHA is always even?
>
> Yes ALPHA is always even. Thanks. However, Due to other FF/Latch
> trimming, FF/Latch <thresh_1> (without init value) has a constant
> value of 0 in block <calibrate> has also come up as a warning which I
> do not understand. And finally, FFs/Latches <PCI_DMAoutaddr<31:1>>
> (without init value) have a constant value of 0 in block <pci_pnp>
> also comes up which corresponds to the following code:
> always @(posedge PCI_CLK)
> begin
> if(~PCI_RSTn)
> begin
> PCI_DMAaddr <= 0;
> DMAwordsWritten <=0;
> unrelated foos <= 0;
> end
> end
>
> wire outaddr = PCI_DMAaddr + {17'b00000000000000000,
> DMAwordsWritten[12:0], 2'b00};
> always @(posedge PCI_CLK)
> begin
> if(~PCI_RSTn)
> PCI_DMAoutaddr <= 0; //this might work??
> else
> PCI_DMAoutaddr <= outaddr;
> end
>
> Why is PCI_DMAoutaddr coming up without init value??
>
> Thanks.
> Ian
Again I don't think that "without init value" is the point of the
message. I imagine
if you had defined PCI_DMAoutaddr something like:
reg [31:0] PCI_DMAoutaddr = 32'b0;
you wouldn't see that part of the message, but it wouldn't change
the fact that it never takes a value other than zero. This can be
traced
back to DMAwordsWritten also staying zero, unless you have left
out some code in the first always block?
I've looked at some of my synthesis reports and found the
same parenthetical "without init value" on signals that had
asynchronous reset terms, so I'm concluding that Xilinx's
idea of "init value" is a specified INIT constraint as applied
to a flip-flop, which can be different from the asynchronous
or synchronous reset term. This is true for FPGA's because
the flip-flops take there initial value from the bitstream, which
does not have to be the same value as the flip-flop reset
term. In any case I'm sure they write this in parentheses
because it is not the important part of the warning. It is
relevant, because if you had specified an init value other
than zero, it could not remove the flip-flop from the design
because the value would no longer be constant.
HTH,
Gabor
Article: 115199I've had no problems so far, 9.1.01i. My design isn't huge - less than half an XC3S1600E - so my compile times aren't what are focused on with the speed improvements. Things did appear a little faster but that may also be because of my tuning the timing numbers recently to make things cleaner in my design. One thing I did notice that looked different (maybe is was, maybe it wasn't) is when the timing was met (Timing Score 0) another quick step was also executed (Timing Score 0) perhaps as a visit to a "cleanup pass" that used to be a good part of the Place & Route. It's only an extra 15 seconds in my 8 minutes or so of Place & Route time. If it's a cleanup, it's much appreciated. I don't use XST so I don't have any indication there. My flow comes in from SynplifyPro Edif and goes out with a promgen-generated .bin file. I had more of a hiccup (small as it was) with SynplifyPro 8.8 than with ISE 9.1.01i. - John_H "Francesco" <francesco_poderico@yahoo.com> wrote in message news:1170427827.806443.94060@q2g2000cwa.googlegroups.com... > Hi, I'm just wondering how many people here are using ISE 9.1. > Could you post your experience here? > Antii what do you think? > Is really 6 time faster? > > I tryed unsuccesfully to use ISE 9.1 SP1...unfortunately in my case > the tool crashed with the message error: "Runtime error" > I tryed a few time unsuccesfully.... Now I'm back on ISE 8.2 > > > Thanks eveybody, > Francesco > > PS: please post here even if you are using Webpack 9.1 >
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