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I am looking for a VHDL/Verilog sample program of Kalman filters. Anybody can help?Article: 97476
Hello All, Does anyone know what the real max DCM CLKIN speed of Spartan-3E stepping 0 is. In the datasheets it says 90 Mhz but in the errata is says 120 MHz. We have one design (with clock feedback from an external pin) where it fails at 100 MHz... Does the same speed limit apply to the CLKFB pin as well.. Thanks, FinnArticle: 97477
Hi there, i`m trying to get a SoC runinng, which is based on a OR1200 soft-processor in an Spartan 3 device. At the moment the system is working (25 MHz, with UART, external SRAM and an SMSC 9118 connected-done with ISE 7.1.04 and 8.1.02). If i`m trying to re-synthesize the whole system with little changes or removed peripherals, the processor seems to get very instable and the execution of the formerly proper working code fails. I`ve also tried to enable the caches for instructions and data, but the result is the same. I guess, the whole system and the processor is very sensitive for timing problems caused by disadvantageous place and route. My questions: Does anyone have experience with implementing OR1200 on spartan 3 ? Is there any reference-desing available, which works with the new debug-interface (i doesnt get it to work) and /or enabled caches ? Any hints for getting better implementation-results (settings of ISE, maybe manually place and route)? any hint would be helpful .. thanks Th. OehmeArticle: 97478
ada wrote: > Thanks to all! > > I simulated my design indeed using Micron memory models (I use > mt8vddt1664a memory model for simulation - it's not exactly my model but > seems to be closed enough for me) and as I wrote before it worked just > fine. But I did not use the FPGA netlist in my simulation. So as > ALuPin@web.de said I'd simulated the VHDL description but not the > synthesis result. I am going to simulate the synthesis results (I'll do it > tomorrow because first I have to find out how to do it. I've never done it > before). Does somebody have a good link about it? So I'm googling around. > I'll write about results tomorrow. > > I am open to any other ideas. > > Best, > Ada One thing I did not mention that *has* given me a great deal of grief on DDR is Vref. DDR requires this to be V(mem) / 2 and the clock crossings have to be within a tight range of this, to say nothing of the other signals. if Vref is produced by a resistive divider with a cap, you might have an issue with just *some* memory sticks - they pull more from Vref than the divider can stand (it's not stiff enough) and you'll get all sorts of flaky (particularly read) behaviour. The standard behaviour of devices is such that the current drawn from Vref is temperature dependent, too, which you are seeing. Stick a scope probe on Vref somewhere with a 'bad' stick and see if it remains at the proper level (or if it even gets to the proper level). Cheers PeteSArticle: 97479
>I did something ugly with a 3.3v cmos 7406 varient and a feedback >resistor, which works well enough to get an accurate reading on one >version of the device under test, but not on the other (both have been >verified with real test equipment) It also tends to self-oscillate >with no input... 7406 is open collector. Did you mean 7404? What size feedback resistor? What sort of oscillations? I've had reasonable luck with that sort of hacking. Not great. What's the output of your gate look like? Is it cleanly switching or struggling to switch at that speed? You might want to skip the external gate and use an inverter in the FPGA out to a feedback pin. That gets the feedback covering the input pin that you are really interested in. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 97480
Frist a little bit of information before my question. I don't know where the best place is for this question. I'm building a 64bit ALU using standard TTL devices. I made a 4bit adder with fast carry, combined 4 of those with 16 AND gates (ends up as a 4x4=8bit multiplier), and then combined 64 groups to provide 15 partial products to a wallace tree (which I also had to make a model for). A final summing adder takes the two partial products from the wallace tree and adds them together. This final summing adder is built using 181 and 182 TTL devices, so I can also subtract and preform basic logic operations if necessary. I basically followed the datasheet from Texas Instruments from 1975. ;) I had to make models of the 74274 and 74275 because they weren't included as standard Altera macros I guess (which is very understandable... ;) ) Anyway, my schematic program produces an EDIF netlist which I'm able to import into Altera's software and compile and simulate my schematic for their FPGA devices. I've been simulating my project with great success. So we are on topic with the whole FPGA thing. :) Now on to my question. Is there a simple combinatorial design for division? So far the whole schematic is made using "Combinatorial logic"? I'm not sure that's the right word. The ALU can perform any function without clock inputs, its also faster than a lot of the other methods I've found. For example, calculating one partial product at a time for multiplication. For more info on the multiplication circuit I've described you can look at the datasheet below. On page 7-398 through 7-400 is a schematic for a 16x16 bit multiplier. Mine is pretty much the same, except mine is 4x larger. This is the first time I've used D size schematic layout. :) For more informatio http://www.tech-systems-labs.com/booksdata/TI-DATA-1976.pdf Any hints for what I should be looking for or links would be great. Searching for combinatorial division I found what looked like to be some good hits, but the website was in the CGI error mood. :(Article: 97481
but you missed the most important information - how fast? sample rate of Hz? kHz? MHz? how many operations for your calculation? (anything other than add/mult involved?) if it fits into a microcontroller then stick to it - its easier bye, MichaelArticle: 97482
pavan wrote: > hi, > am Pavan working on a project in India. I am stuck with a problem. i > > hope one of u can clear it. before continuing ill tell u my project in > brief. I am basically a fresh graduate. i love working on > microcontrollers. but i would like to know which one would be better > for my application. my application goes this way. > i need to collect analog inputs convert into a digital format > using a A/D convertor and use the digital data to do some calculations > and based on the value send a signal to the output which changes state > from one to the other. also i need to interface display and some > keypad. so i thought a microcontroller with internal A/D convertor and > memory is sufficient. But now i ve heard about this FPGA concepts and i > > would like to know which would be better. And also please mention some > of the advantages of using FPGA over the microcontroller. > hoping to get an answer soon. > Thanking you > > yours truly > Pavan. > How fast do you need things to happen? You mention a digital output: all the others are human-interface, hence not "fast". At human speeds (& a lot more!), a small microcontroller (eg AVR) has an in-built multi-channel ADC, & all the processing you need, for about $3. Can't get near that in a FPGA. FPGA's are the ting if you want awesome speed: you will need a separate ADC, & the high-speed ones come expensive. Looks like you don't need them.Article: 97483
cs_posting@hotmail.com wrote: > The other day I found myself needing a short gate time ~200 mhz > frequency counter for an automated test, and since I had an FPGA board > on hand I whipped one up quickly. Getting it reading and reporting to > my computer was the easy part. > > Ah, the input stage.... > > I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p > or a little more if it's high-Z. The output of the device under test > has a transformer and then a series cap to create an unbalanced output. >[snip] Beside that no frequency is mentioned, I'd have a look at line receivers. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.net *** Free account sponsored by SecureIX.com *** *** Encrypt your Internet usage with a free VPN account from http://www.SecureIX.com ***Article: 97484
Thomas, Thomas Oehme wrote: > Hi there, > i`m trying to get a SoC runinng, which is based on a OR1200 > soft-processor in an Spartan 3 device. > At the moment the system is working (25 MHz, with UART, external SRAM > and an SMSC 9118 connected-done with ISE 7.1.04 and 8.1.02). > If i`m trying to re-synthesize the whole system with little changes or > removed peripherals, the processor seems to get very instable and the > execution of the formerly proper working code fails. > I`ve also tried to enable the caches for instructions and data, but the > result is the same. > I guess, the whole system and the processor is very sensitive for timing > problems caused by disadvantageous place and route. instead of guessing take look to the timing report, do you have any timing constraints? does it fail on timing? by looking into the timing report you can identify the critical path, and you'll be able to judge yourself if is a design isssue (to many levels of logic) or an implementation issue (poor placement) Have fun, Aurash > > My questions: > Does anyone have experience with implementing OR1200 on spartan 3 ? > Is there any reference-desing available, which works with the new > debug-interface (i doesnt get it to work) and /or enabled caches ? > Any hints for getting better implementation-results (settings of ISE, > maybe manually place and route)? > > any hint would be helpful > > .. thanks > > Th. Oehme >Article: 97485
Hi again, another possibility (that I have implemented sometime ago) is to use a BRAM memory in the coprocessor. The MB write/read data from this memory through the FSL interface, being accessible for the coprocessor too. An schematic: MB <--- FSL interface ---> BRAM <--- custom interface ---> Coprocessor I hope that it is useful for you. Ivan fpga wrote: > I want my coprocessor can access the BRAM diretly because there is a > lot data transfer between them. It will be very unefficient to send > these data back to MB through FSL and then put them into OPB RAM or > vise verso. > I don't want to put connected my coprocessor to the sceond port of the > BRAM either because the BRAM(64K) is shared between the MB and my > coprocessor and I want the OPB arbitrator to solve the contension > problem for me. Then I needn't program my own. > For the second choice, write my own FSL2OPB bridge, or as said by ivan: > "develop a FSL coprocessor with OPB Master interface" will be quite > time consuming because I need to take care of my customized circuit to > the OPB bus signals? But it seems the only choice I have. > Did I understand this correct? > > Thank you very much for all the replies. >Article: 97486
Then, I share your stance/viewpoint about that ;) Ivan Antti wrote: > Yes/No > > I was using custom board for the PPC design mentioned, not anything > even remotly similar to any supported Xilinx boards, so I created a > full custom system, and that worked. But agree, I only used uart lite > for simple hello greeting. At next step adding a DCM I had to use 2 > synthese attempts to get it working again (the DCM runs from 12MHz > external clock so its little difficult to setup properly). > > And with LEON3 I wasnt using supported board either (with supported > board it most likely would have worked from first config attempt) - and > all of that getting working on first attempt (or within hours) is only > possible with lots of experience ;) > > Antti >Article: 97487
cs_posting@hotmail.com wrote: > The other day I found myself needing a short gate time ~200 mhz > frequency counter for an automated test, and since I had an FPGA board > on hand I whipped one up quickly. Getting it reading and reporting to > my computer was the easy part. > > Ah, the input stage.... > > I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p > or a little more if it's high-Z. The output of the device under test > has a transformer and then a series cap to create an unbalanced output. > > > I did something ugly with a 3.3v cmos 7406 varient and a feedback > resistor, which works well enough to get an accurate reading on one > version of the device under test, but not on the other (both have been > verified with real test equipment) It also tends to self-oscillate > with no input... > > What would be the right way to do this using on hand parts, such as > abused logic, little 1:1 or 2:1 RF transformers, etc? One idea is to > use another gate with a feedback resistor and cap to ground in the hope > of establishing the threshold level, and then using a transformer to > swing another input above and below this. Most parts on hand are SMD - > which means dead bug construction in SOIC scale under the maginifier - > discourages extensive experimentation. > > Why do most abuse-of-logic RF applications seem to use NAND gates > rather than inverters? From a digital perspective NAND gates are a > universal element, but once you tie their inputs together, is there > something to be gained from having two inputs in parallel? the only gain is some PWB layout simplifications and less wasted part sections. > > Is there a way to use a differential input configuration on an FPGA to > input a balanced RF signal directly? Theoretically this should be an > FPGA clock input... The device in use currently is an Altera Stratix > II, but a Xilinx S3 kit is available. > > If ordering things, what would be a good default low supply voltage > HF/VHF gain component to have on hand? I seem to recall lots of > last-millenium ham designs using the MC1350P video IF amp, but what > would make sense today? > I am thinking on the order of a single transistor amplifier to go to logic levels, then characterize it for delay issues. -- JosephKK Gegen dummheit kampfen Die Gotter Selbst, vergebens. --ShillerArticle: 97488
Hi can anyone tell how much Virtex 4 costs, given that I only want to buy 2 chips :). e.Article: 97489
>... but what > would make sense today? > http://www.onsemi.com/PowerSolutions/product.do?id=MC100EPT21DR2Article: 97490
around 100 USD maybe a little aboveArticle: 97491
"metal" <nospam@spaam.edu> wrote in message news:7bnqv15u98kpc9cnll2suuubkmf9a4sm0o@4ax.com... > > Nevertheless; your mention of a mega-chip did cause me to sit back and > wonder if there is the "optimum" approach might be size-related?? > I.e., those who are repeatedly doing desgins of a few hundred > registers (like myself) may benefit more from a graphical approach > than the designer who is tackling the million-gate monster. > > I have to say though, that when it comes time to troubleshoot the > -product- that your monster-chip is embedded in, I will -still- want a > block-diagram of your chip! LOL > Hi there, Yeah, fair point on the block diagram! And 'monster-chip' is an apt description of some of the stuff I seem to be involved with. :-) I think you're right on the optimum approach depends on size. For a small design or, as you point out, a small part of a 'monster' design, a schematic could be a good way to do things. OTOH, for a large DSP design drawing 18 bit multipliers gets old very soon. Writing a <= b * c; is nice and quick! I guess a mixture of design entry methods would be nice, but then you have to cope with bugs in the HDL tools, bugs in the schematic tools and, worst of all, bugs in the tools that merge the parts together. I'm not sure my keyboard/mouse could stand being thrown that many times! Finally, I think your point about using hierarchy intelligently is the key to any design, overriding by far whatever design entry approach the designer uses. Thanks and all the best, Syms.Article: 97492
Aurelian, thanks for your reply. Of corse i did a look to the timing report. I have no timing constraints specified, but i am using a system clock (25 MHz), which is clearly lower than the maximum clock period from the report(36,2 MHz). Aurelian Lazarut schrieb: > > instead of guessing take look to the timing report, do you have any > timing constraints? does it fail on timing? > by looking into the timing report you can identify the critical path, > and you'll be able to judge yourself if is a design isssue (to many > levels of logic) or an implementation issue (poor placement) > > Have fun, > Aurash >Article: 97493
> I think > what is suprising to some, is that low level software design is long > gone, ????? No-one ever programs in assembly language any more then? > and low level hardware design is soon to be long gone for all the > same reasons of labor cost vs. hardware cost. Where price, performance and power consumption don't matter a higher level language might become more prevalent. I think we'll always need to be able to get down to a lower level hardware description to get the best out of the latest devices, stretch the performance of devices or squeeze what needs to be done into a smaller device. I also wonder if price/performance/power consumption will become much less important in the future, as it has with software. These days you can assume application software will be run on a 'standard' sufficiently powerful PC. It won't be the case that at the start of every hardware project that you can assume you have a multi million gate FPGA (or whatever) at your disposal. Nial.Article: 97494
You need to ask Xilinx if checkpointing/restore is supported for the PowerPC model since you need to hardcode it in. Have a look at the FLI (used for swift) documentation to get an idea what is required. Hans www.ht-lab.com "Nju Njoroge" <njoroge@stanford.edu> wrote in message news:1140654602.292568.161850@g43g2000cwa.googlegroups.com... > Hello, > > I have set-up checkpointing in ModelSim 6.0b (also using EDK 7.1 SP2). > ModelSim complains that "two foreign architectures are missing save and > restore callbacks" when I checkpoint. These "foreign architectures" > happen to be the PPC swift models. When I restore the checkpoints, the > waveforms are fully restored. However, I cannot continue the simulation > because it makes the following complaint: > > # ** Fatal (SmartModel): > # SWIFT protocol: > # The first call to lsm_Model_DCEvaluate must occur at time 0. > # Time: 424875000 ps > Instance:/system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst > # ** Fatal: Foreign module requested halt. > # Time: 424875 ns Iteration: 0 Foreign Process: > /system/ppc405_0/ppc405_0/ppc405_i/ippc405_swift/ppc405_swift_inst/SmartModel > File: Foreign > # Fatal error at an unknown location > # > > Anyone encountered this issue? > > Thanks, > > NN >Article: 97495
hello all, I am currently working on a DDR2 memory implementaion with Xilinx Virtex4 SX35. I have to use two independant SoDIMM 200 Modules. The main problem I think is to find the correct physical PCB layout. Which constraints do I need to fulfill? (trace length, impedance, ...) I currently dont have the schematics of a reference design. can anyone help? I like to use the MIG from Xilinx and ISE8.1 - Xilinx told me I have to wait till MIG1.5 is relesed. pitArticle: 97496
you can obtain the ml461 sch from xilinx I think hmm.. MIG 1.5 and EDK ?? EDK 8.1 SP1 has non-MIG based DDR2 support, I have not heard that EDK will include support for MIG generated memory cores? AnttiArticle: 97497
swimmer_@gmx.de wrote: > hello all, > I am currently working on a DDR2 memory implementaion with Xilinx > Virtex4 SX35. > I have to use two independant SoDIMM 200 Modules. > The main problem I think is to find the correct physical PCB layout. > Which constraints do I need to fulfill? (trace length, impedance, ...) > I currently dont have the schematics of a reference design. > can anyone help? > > I like to use the MIG from Xilinx and ISE8.1 - Xilinx told me I have to > wait till MIG1.5 is relesed. > > pit Which DDR devices are you going to use? Whatever they are, get the data sheets and start a timing budget analysis. For most impedance controlled tracks on FR4 (or something close), signal transit time is about 160picosec / inch. For the timing budget, you need to know the timing *at the pins* (which can differ significantly from the signal at the IO buffer). For each standard via, add 50 picoseconds (minimum) of deterministic jitter at edge rates. The schematics are simply not sufficient for setting layout rules - you need a precision data sheet with all the relevant timing parameters listed. Cheers PeteSArticle: 97498
On a sunny day (22 Feb 2006 19:01:44 -0800) it happened cs_posting@hotmail.com
wrote in <1140663703.875988.162830@g14g2000cwa.googlegroups.com>:
>The other day I found myself needing a short gate time ~200 mhz
>frequency counter for an automated test, and since I had an FPGA board
>on hand I whipped one up quickly. Getting it reading and reporting to
>my computer was the easy part.
>
Just a partial reply... I think 7400 series should stop way below 200mHz,
perhaps 50MHz?
I would make a small diff amplifier, did something 40 years ago (yes 40!)
with I think it was BFY90 transistors, then invert with 2 more and drive
the LVDS input.
-------------------------------- +5 or + 12
| | |
[ ] [ ] [ ] R4
| |------------ __|__
|-----|-------- | | |
|/ \| | | |/>e < \|
---| NPN |---- | |----| |---
in |\> e </ |bias2 | |\ PNP /| |
|___| | | | |
| ---------|-----|----
| / | |
---| |---- |----------- LVDS +
bias | \> | |----------- LVDS -
| | |
[ ] [ ] [ ]
| | R5 | R6
---------------------------------------------- GND
R4 could be a current source too, set it so it is guaranteed that
the voltage across R5 and R6 (max i in one leg) cannot exceed FPGA
max in.
Gives you some input protection
The 'bias voltages can be generated with diode drop.
No time now to enter it in spice to get response.....
You can use simple junction FETS for the first stage too.
There are also nice chips, but transistors I have always in the box.
Article: 97499hello PeteS, I like to use all kind of DDR2 Ram modules fitting in the DDR2 SoDIMM Socket (200pin). I looked at the micron page and found the data sheet for MT8HTF6464HD. Actually there are no timing information. When I use instead the information from the micron chips on the module itself, I need to add something for the traces on the module. I think the absolute trace length doesnt matter - the Xilinx MIG core compensates for that. Maybe I need to buy the ML461 Reference Board from Xilinx. Are there any layout rules? Are the schematics included? does anybody have the layout rules and schematics? thanks pit
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