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Uwe Bonnes wrote: > rickman <spamgoeshere4@yahoo.com> wrote: > > Xilinx XC3S1000-4FG456I > > Altera EP2C20F484I8 > > Lattice ECP2-12E-5F484I > > > I find that the differences between the parts are not so great that I > > want to exclude any of them. I would like to get an idea of how the > > pricing compares. I am looking for other than the list prices which > > tell me more about the distributor's markup than it does the price I > > can otherwise get. I figure asking here might be quicker than waiting > > for a price quote. > > To get a feeling for Xilinx price, try the Xilinx webshop, nuhorizons and > digikey. They all have on-line prices. > > Are there any online prices for the Altera/Lattice parts? Yes, but all of these sources have typically poor pricing, especially the manufacturer's store. FPGA pricing will vary signficantly with volume and that will never show on the web pages at Digikey or Arrow.Article: 97251
John Adair wrote: > Very much what Simon said is that the distributors are working from a price > book unless you get supported pricing for your project. Here in EEC I > believe by law they can't enforce centrally fixed prices and the disti can > vary prices out of their margin. Margins are tight nowadays and here in the > UK we don't even have a choice of distributor for Xilinx to get a > competative quote. The other vendors are not much better in having choice of > whom to buy from. So pressure to give competative pricing isn't high unless > you fall into the area of interest for the FPGA vendors. > > If your project is reasonable volume, or FPGA value, then talk to your > distributor and get supported pricing whoever's silicon you choose to use. > If you don't have either of these attributes in your project you may be > better to a third company like ourselves to manufacture . It may be cheaper > than even doing it yourself because of the better FPGA pricing that can be > obtained by volume users of FPGA silicon. I understand how pricing works. I would just like to avoid the disti because it typically takes them a week to close the loop with the product manager and the vendor and they always want to play 20 questions with me. Where I work they take every little part very seriously and I am not looking at this for a current project, I am planning a future one. The vendors are very, very supportive, too much so. For once I want to find out what prices others are getting without going through the disti mill. Anyone using the specific parts listed above?Article: 97252
God "Philip Freidin" <philip@fliptronics.com> wrote in message news:n1vhv1tc1nelcm31ei1ka4v6epgi1kadhm@4ax.com... > On Sun, 19 Feb 2006 11:21:50 -0800, Phil Hays <Spampostmaster@comcast.net> > wrote: >>"Hub van de Bergh" <hub_antispam@hetnet.nl> wrote: >> >>>Does a VHDL programmed FPGA concern software or hardware? >> >>Both. > > Neither > Philip Freidin > FliptronicsArticle: 97253
Hi All,
I am trying to infer a adder with a carry in and carry out in Xilinx
ISE 7.1. For the unsigned adder case it is inferred properly, i.e carry
in is fed to the slice adding the LS bits and Carry out taken from the
COUT line of the slice adding the MS bits.
However when I generate a signed adder (by sign extension) the above
does not happen. The carry in is properly created, but the carry out is
not taken as the output of the COUT signal of the slice where the MS
bits are added. Instead another LUT is used to add the MS bits (again)
and the cout from prev stage and then this is used as the carry out.
Why the difference? Below is the VHDL I am using to generate the adder
---------------------------------------------
-- Generic Adder with Carry In and Carry Out
---------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity GenAdder is
generic(
gDATA_I_WIDTH: natural := 16; -- data input width
gSIGNED: boolean := true -- signed adder?
);
port(
A: in std_logic_vector(gDATA_I_WIDTH-1 downto 0);
B: in std_logic_vector(gDATA_I_WIDTH-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(gDATA_I_WIDTH-1 downto 0);
Cout: out std_logic
);
end entity GenAdder;
architecture rtl of GenAdder is
signal sum: std_logic_vector(gDATA_I_WIDTH downto 0);
signal A_ex,B_ex: std_logic_vector(gDATA_I_WIDTH downto 0);
begin
----------------
-- signed adder
----------------
gensigned: if gSIGNED generate
A_ex <= A(gDATA_I_WIDTH-1) & A;
B_ex <= B(gDATA_I_WIDTH-1) & B;
sum <=
conv_std_logic_vector(signed(A_ex)+signed(B_ex)+Cin,sum'length);
S <= sum(gDATA_I_WIDTH-1 downto 0);
Cout <= sum(gDATA_I_WIDTH);
end generate;
-----------------
-- unsigned adder
-----------------
notgensigned: if not gSIGNED generate
A_ex <= '0' & A;
B_ex <= '0' & B;
sum <=
conv_std_logic_vector(unsigned(A_ex)+unsigned(B_ex)+Cin,sum'length);
S <= sum(gDATA_I_WIDTH-1 downto 0);
Cout <= sum(gDATA_I_WIDTH);
end generate;
end architecture rtl;
Thanks in advance
Sudhir
Article: 97254
JJ wrote:
[ ... ]
> Besides, badly asked obvious homework/essay questions are considered
> sport. On the comp arch parent NG, the sport is far more brutal.
> Professors should I hope monitor the relevant NGs to see who the class
> slackers are. I actually had some buffoon google me & ask to do his
> homework, only had to haggle the price.
Once upon a time (in a different NG) a bozo asked obvious homework
questions for about a month straight. I (semi-jokingly) asked him to
send me his prof's email, so I could save him the trouble of even
having to email the answers in -- and being (apparently) a bit stupid
along with lazy, he sent not only his prof's email, but also his own
full identification (class number, student ID number and the whole
bit). For some strange reason, after I emailed his prof, the guy just
seems to have dropped out of sight.
I also know of at least one guy in Russia who makes a pretty decent
living, almost entirely from doing homework for people in the US. I
guess in this day and age, it's good training for managers though --
they'll have practical knowledge of outsourcing before they graduate...
--
Later,
Jerry.
The universe is a figment of its own imagination.
Article: 97255
Hello:
I am trying to write some code for a comparator. Is it possible to
write the code as so
module comparator(A_lt_B, A_gt_B, A_eq_zero, B_eq_zero, A, B);
parameter D_Width = 32;
output A_lt_B, A_gt_B, A_eq_zero, B_eq_zero;
reg A_lt_B, A_gt_B, A_eq_zero, B_eq_zero;
input [D_Width-1:0] A;
input [D_Width-1:0] B;
always@(A or B)
begin
if(A>B) A_gt_B = 1;
else if (A<B) A_lt_B = 1;
else if (A==0) A_eq_zero = 1;
else if (B==0) B_eq_zero = 1;
end
endmodule
Thank You
Article: 97256prasunp@gmail.com wrote: > Hello: > > I am trying to write some code for a comparator. Is it possible to > write the code as so > > module comparator(A_lt_B, A_gt_B, A_eq_zero, B_eq_zero, A, B); > > parameter D_Width = 32; > output A_lt_B, A_gt_B, A_eq_zero, B_eq_zero; > reg A_lt_B, A_gt_B, A_eq_zero, B_eq_zero; > input [D_Width-1:0] A; > input [D_Width-1:0] B; > > always@(A or B) > begin > if(A>B) A_gt_B = 1; > else if (A<B) A_lt_B = 1; > else if (A==0) A_eq_zero = 1; > else if (B==0) B_eq_zero = 1; > end > > endmodule > > Thank You 1) you don't have statements for results of false. 2) you can have A<B and A==0 but your code will only provide A_lt_B. Rather than if/elseif/elseif/elseif which will produce latches (if A==B and A!=0) consider assigning the result variables directly as opposed to the conditional statements, e.g. A_gt_B = (A>B);Article: 97257
Mich wrote:
> Hi all,
>
> I'm designing a IP core for a Virtex 2 pro board. This IP need to store
> data in BRAM. I have been searching how I can adress the BRAM with my
> IP but I haven't found it.
> Can anyone tell me how you can do this?
>
> Thanks
> Mich
>
Short coding example (from the real life):
--snip
type memory_type is array (natural range <>) of std_logic_vector(0 to 31);
signal memory : memory_type(511 downto 0);
--snap
--snip
bram_inst : process(clk) is
begin
if rising_edge(clk) then
if rst = '1' then
data_out <= (others => '0');
else
if fifo_write = '1' then
memory(to_integer(write_addr)) <= data_in;
else
data_out <= memory(to_integer(read_addr));
end if;
end if;
end if;
end process;
--snap
This process infers a BRAM (at least if synthesized by ISE). data_out
and data_in are obviously global ports. write_addr is a counter keeping
track of where to write (this BRAM was used in a FIFO) and read_addr is
equally a counter keeping track of where to read. to_integer() is a
function converting a std_logic_vector to an integer.
Apart from this you may implement logic for full- and empty flags etc.
--
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer
Swedish Defense Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems
www.foi.se
Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------
Article: 97258
Hi
I am writing synthesizable Verilog code for a DPRAM. It has two ports,
Port A and Port B.
For each port theres is a separate clock and separate clock_enable.
This is the code I wrote
reg [ 4: 0] read_addr_a;
reg [ 4: 0] read_addr_b;
always @ (posedge clock0)
if (clocken0)
begin
read_addr_a <= address_a;
read_addr_b <= address_b;
end
always @ (posedge clock1)
if (~clocken0 & clocken1)
begin
read_addr_a <= address_a;
read_addr_b <= address_b;
end
Can't resolve multiple constant drivers for net "read_addr_a[4] in the
begiing of the first posedge block.
Even though read_addr_a and read_addr_b are having multiple drivers
but they are in different clock domains and different clock enables are
being used.
How can I resolve this. I am using Leonardo Spectrum and Precision RTL.
TIA
Sunny
Article: 97259workaround: you divide into 2 macros and create the 16 possible macros for LUT1 and same for LUT2. Then you instanciate a component that will "if ... generate" the right macros... sure that's not smart but can be useful if part of an automated flow. Antti Lukats wrote: > "Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag > news:43f72f54$0$27124$ba620e4c@news.skynet.be... > >>Antti Lukats wrote: >> >>>"Sylvain Munaut" <com.246tNt@tnt> schrieb im Newsbeitrag >>>news:43f72795$0$18969$ba620e4c@news.skynet.be... >>> >>> >>>>Hi, >>>> >>>> >>>>I have a hardmacro that's quite small (2 slices) and that have 2 LUTs in >>>>them and I'd like to be able to choose the INIT string of theses two >>>>luts when I instanciate them. Is this somehow possible ? >>>> >>>>I have to instanciate quite a few of them with different parameters and >>>>I'd _hate_ to have to make as many hardmacro as I need different LUT4 >>>>config ... >>>> >>>> >>>>Sylvain >>> >>> >>>convert .NMC to XDL and back, maybe it works that way >>> >>>(NMC is same format as NCD) >> >>How is that gonna help me ? >> >>What I'd like to do is when I instanciate in my VHDL code, be able to >>use generic to pass the INIT string of my two LUT4 like >> >>inst_I: my_hard_macro >>generic map ( >>INIT_LUT4_1 => x"0123", >>INIT_LUT4_2 => x"1234" >>) >>port map ( >>-- my ports, ... >>); >> >> >> >>Sylvain > > > you cant do that ASFAIK, > so XDL may be the only possibility to change an existing hardmacro, sure it > involves some scripting to be done, etc, > > Antti > > >Article: 97260
HI, Hub van de Bergh schrieb: > Does a VHDL programmed FPGA concern software or hardware? This question is hard to answer. Depends on the criteria you use. My opinion is use the one of Hard, Soft & Firm that fits your needs best :). A good answer should include, that it is very design dependend. A programmed fuse based FPGA is hardware, a bitfile using reconfiguring during runtime is software. Maybe you could allways consider the device as HW and the bitfile as SW. Of course this is a very easy point of view. > As usual also this issue can be approached from different viewpoints. > One viewpoint can be the realization process, Why? > Another viewpoint can be blackbox testing of the programmed FPGA device, > whether or not 100 % coverage can be achieved. And what do you call SW without 100% BB-Testing? (Beside "commercial ready") > Should software > engineering methodologies be applied or is it more likely application of > switching theory and logical design or ..... > And what about design verification & validation? Software engineering methods are more often applied for developing HW than for developing SW. bye ThomasArticle: 97261
This guy is not a student, he has an Ir degree (at least according to his website) which is like a 3 year MSc! The best answer to his question is both, ignore one out and you will fail :-) Hans www.ht-lab.com "Rich Webb" <bbew.ar@mapson.nozirev.ten> wrote in message news:v09hv1ledk0kltuau21v40u57jifb8c805@4ax.com... > On Sun, 19 Feb 2006 15:58:45 +0100, "Hub van de Bergh" > <hub_antispam@hetnet.nl> wrote: > >>Does a VHDL programmed FPGA concern software or hardware? >> >>As usual also this issue can be approached from different viewpoints. >>One viewpoint can be the realization process, >>Another viewpoint can be blackbox testing of the programmed FPGA device, >>whether or not 100 % coverage can be achieved. >>You will certainly be able to add your own viewpoints and your personal >>opinion to this question. >>Does a VHDL programmed FPGA concern software or hardware? Should software >>engineering methodologies be applied or is it more likely application of >>switching theory and logical design or ..... >>And what about design verification & validation? >>What do you think? > > Essay question for homework? > > -- > Rich Webb Norfolk, VAArticle: 97262
send a mail to ur company address and the mail address provided in the groups profile. Any way i found no virtex 4 based board on your site. I want a virtex 4 based board. And there should be provision for connecting 400 pin processor directly to the FPGA. Also there should be an SD RAM or provision to add one. I am ready to implement a sd ram controller in the virtex 4. Please consider this as an urgent thinh. Thank you very much for your response. regards Sumesh v SArticle: 97263
> All signals seem to > drive as they should during writing. During reading I see all zeros or > just rubbish on data bus. > I tried to change timing parameters but they don't affect. you are convinced that your write operations are fine just by looking at the signals with chipscope? writing has no "success" feedback from the ram so if you mix up your enable signals or provide a faulty clock that would still look good on chipscope! take a logic analyzer or an oscilloscope and check your setup/hold times and your clock at the ram ... bye, MichaelArticle: 97264
Hi,
Reading the
http://www.xilinx.com/publications/books/serialio/serialio-ch3.pdf
you can see in fig 3-5 pg .24 and in the text pg. 25 an example of
multiphase data extraction circuit.
I tried to implement it with a variant:
- the 4 first flip-flops clocked with 0, 90, 180 and 270 phase
shift,
feeds directly other 4 flip-flops clocked with 0 phase shift.
simulating it, the circuit seems to work...
Someone know if doing that (my variant), instead of feeding some other
flip-flop clocked by the next lowest phase until it is clocked
off the zero-phase clock, can have some glitch issue or some
other problem ?
i--|
| ---- ----
----------| |--------------| |------
| 0 ---| | 0 ---| |
| ---- ----
|
| ---- ----
----------| |--------------| |------
| 90 ---| | 0 ---| |
| ---- ----
|
| ---- ----
----------| |--------------| |------
| 180 ---| | 0 ---| |
| ---- ----
|
| ---- ----
----------| |--------------| |------
270 ---| | 0 ---| |
---- ----
thanks in advance
Sandro
Article: 97265On Sat, 18 Feb 2006 06:23:28 -0600, "maxascent" <maxascent@yahoo.co.uk> wrote: >The system I am designing is a pc scope. I guess I will know the trigger >point. What I dont really understand is how you can generate precise >offsets from the trigger if you want to sample in the GHz region as you >are talking about picosecond values. I guess I dont fully understand the >procedure > I think that last item is the one to focus on. What you're attempting to make is a "Sampling Scope", and it was done long before digital electronics even existed (i.e. vacuum-tube days, 1950's and earlier). In fact, the "equivalent-time sampling technique" itself stretches all the way back to before ANY electronics existed....to around 1900. It was invented in that era as a mechanical device; used for drawing a real-time "pressure-volume-time" diagram of an operating engine. While the explanations given so far are good 'snippets', if you really want to understand the basics, you should forget all about "digital" for a minute, and get hold of the Sampling Oscilloscopes book of the Tektronix Primer series. It will give you an -excellent- grounding in the basic theory and techniques of sampling; and -then- you'll be armed with the knowledge to help you best implement as much of the system as possible digitally. Note that there are -two- methods of sampling....the 'linear' or 'incremental' method, as covered here by the various posters; but also a 2nd method known as "random" sampling. Random sampling has some significant advantages. With proper design, your system can be selectable to do either. I also highly recommend that you get a set of service-manuals (probably $20-50) for the Tektronix 7T11 and 7S11 sampling plugins. These are 1980 era plugins which have pretty modern analog electronics and also TTL-era digital stuff; so it'll be fairly close in relevance to your goal of "all digital". The 7T11 does random-sampling, and these manuals contain excellent "theory of operation" sections; as well as a full set of what I consider the nicest schematics ever produced. (i.e. Tek schematics of the 50's through 80's in general) One of the biggest advantages of the "random sampling" method is that it eliminates that need for a delay-line between the trigger ckt and the sampling ckt. That may sound minor, and someone mentioned that you just needed some coax to do it; but neither is really true in your case. You were talking about several Ghz BW. To get any kind of high quality (i.e. 'scope' quality) acquisition of pulses, you are looking at special low-dispersion coax that costs 10 bucks a foot or more. Note also that your -front end- must have flat BW all the way up to the highest frequency to be measured; -regardless- of how slow the AD is going to be. For example, a vintage Tektronix 3S1 sampling-scope plugin (1950's-60's) has excellent pulse-fidelity past a full Ghz, yet it "digitizes" only in the Khz range. I'm saying that this isn't RF stuff where you can live with 1-3db of variances all through the spectrum. In needs to be FLAT...and issues like dispersion and group-delay are very important in this application. If you take a look at a commercial-quality 1+ Ghz scope front-end, you'll quickly realize that building such a front-end with any quality at all is a non-trivial exercise... <g> Switchable attenuators alone will be an engineering challenge; not to mention buffering, input protection, etc.. And in your case (digital), the quality of your clocks, and the digitizer itself (jitter). Also, trigger-circuitry is a distinct field of art all by itself. Test-equipment quality multi-Ghz triggers are not a simple matter, by any means. It's a fascinating field, and extremely satisfying when you succeed in capturing events which lasted only a few picoseconds. There's just something awesome about that...to me anyway. I've never had occasion to use it in a product, but have dabbled in it solely for the love of it for 25+ years now... If you google for "kahrs sampling" (don't use the quotes), you might find some other interesting material on it. He's another "sampling nut" who has written some journal papers on sampling and network-analyzers (same principles) and had some useful papers and links on his website the last time I looked. good luck! ----== Posted via Newsfeeds.Com - Unlimited-Unrestricted-Secure Usenet News==---- http://www.newsfeeds.com The #1 Newsgroup Service in the World! >100,000 Newsgroups ---= East/West-Coast Server Farms - Total Privacy via Encryption =---Article: 97266
Isaac Bosompem schrieb: >>>>Does a VHDL programmed FPGA concern software or hardware? >>> >>>Both. >> >>Neither >>Philip Freidin >>Fliptronics > > > How are you guys coming up with answers? > I didn't understand the question ??? So we should consult Deep Thought about the question . . . ;-) Regards Falk 42Article: 97267
On 20 Feb 2006 01:44:29 -0800, "Sandro" <sdroamt@netscape.net> wrote: >Hi, > >Reading the >http://www.xilinx.com/publications/books/serialio/serialio-ch3.pdf >you can see in fig 3-5 pg .24 and in the text pg. 25 an example of >multiphase data extraction circuit. > >I tried to implement it with a variant: > - the 4 first flip-flops clocked with 0, 90, 180 and 270 phase > shift, feeds directly other 4 flip-flops clocked with 0 phase > shift. > >simulating it, the circuit seems to work... Because you are simulating without timing. >Someone know if doing that (my variant), instead of feeding some other >flip-flop clocked by the next lowest phase until it is clocked >off the zero-phase clock, can have some glitch issue or some >other problem ? The problem will be meeting the the setup time to the flipflop clocked by phase 0, sourced by the flip flop clocked by phase 270. You will only have .25 of a cycle, and depending on the clock frequency and the routing delays, the setup time will not be met. In your circuit, the first path has 1 cycle available, the second path has .75 of a cycle, the third path has .5 of a cycle, and the fourth path has .25 of a cycle. In Xilinx's circuit, no path has less than .75 of a cycle. >i--| > | ---- ---- > ----------| |--------------| |------ > | 0 ---| | 0 ---| | > | ---- ---- > | > | ---- ---- > ----------| |--------------| |------ > | 90 ---| | 0 ---| | > | ---- ---- > | > | ---- ---- > ----------| |--------------| |------ > | 180 ---| | 0 ---| | > | ---- ---- > | > | ---- ---- > ----------| |--------------| |------ > 270 ---| | 0 ---| | > ---- ---- > >thanks in advance >Sandro Cheers, Philip Freidin Philip Freidin FliptronicsArticle: 97268
Try www.opencores.org Still there ... WBR, Vladimir S. MirgorodskyArticle: 97269
On 02/20/2006 11:22 AM, Philip Freidin wrote: >... > > The problem will be meeting the the setup time to the flipflop clocked > by phase 0, sourced by the flip flop clocked by phase 270. You will > only have .25 of a cycle, and depending on the clock frequency and > the routing delays, the setup time will not be met. > > In your circuit, the first path has 1 cycle available, the second > path has .75 of a cycle, the third path has .5 of a cycle, and the > fourth path has .25 of a cycle. In Xilinx's circuit, no path has > less than .75 of a cycle. >... Philip, Then if i use strongs timing constraints and the constraints are satisfied implementing my circuit, it should works ? I have well understood ? thanks a lot SandroArticle: 97270
"Philip Freidin" <philip@fliptronics.com> wrote in message news:np5jv11opddfqnhfdqet8feg45e6po0ouq@4ax.com... > On 20 Feb 2006 01:44:29 -0800, "Sandro" <sdroamt@netscape.net> wrote: >> >>I tried to implement it with a variant: >> - the 4 first flip-flops clocked with 0, 90, 180 and 270 phase >> shift, feeds directly other 4 flip-flops clocked with 0 phase >> shift. >> >>simulating it, the circuit seems to work... > > > Because you are simulating without timing. > > The problem will be meeting the the setup time to the flipflop clocked > by phase 0, sourced by the flip flop clocked by phase 270. You will > only have .25 of a cycle, and depending on the clock frequency and > the routing delays, the setup time will not be met. > Yep, I agree with Philip. Just to add, if the OP can meet the timing because (say) the clock frequency is low enough, they'd probably be able to have a better design by dumping the DCM phase shift idea, using the DCM to multiply the clock by four and then using that clock to sample the data instead. Cheers, Syms.Article: 97271
> Yep, I agree with Philip. Just to add, if the OP can meet the timing because > (say) the clock frequency is low enough, they'd probably be able to have a > better design by dumping the DCM phase shift idea, using the DCM to multiply > the clock by four and then using that clock to sample the data instead. Symon, I agree with you... maybe if the frequency is low enough (so that my circuit will works...) probably I don't need the multiphase data extraction... thanks SandroArticle: 97272
On Mon, 19 Feb 2006, JJ wrote: "[..] Professors should I hope monitor the relevant NGs to see who the class slackers are. [..] [..]" When I was an undergraduate in what was then called the School of Computer Applications and which is now called the School of Computing in Dublin City University ( WWW.computing.DCU.Ie ), students had their own (non-Usenet-)newsgroups which almost no lecturers bothered with. A fair amount of acceptable discussion trying to help each other out with homework problems used to (and possibly continues to) occur on one of those newsgroups, as with gross unacceptable plagarism. Shockingly, one of the postgraduate students actually provided answers to simple second year programming exercises (which were actually of late first year caliber). Though mass scale (approximately one hundred cheaters in a class of approximately two hundred) plagarism was detected and warned against and possibly punished (without expulsions) in the previous academic year in a different case, I had complained to the lecturer for the previous paragraph about a smaller case of copying and I never received a response.Article: 97273
Colin Paul Gloster schrieb: > "[..] > Professors should I hope monitor the relevant NGs to see who the class > slackers are. [..] > > [..]" I think the problem is much more fundamental. This problem of (easy) copy & paste came around with the internet. Schoolers in almost all ages use the internet to gather informations. And sure you will find a lot of ready to use stuff, up to complete essays etc. This IS very tempting. And finally, the goal is to get much information in an easy way. NOBODY is trying to make it harder than necessary, right? Years ago you had to go to the library, search the avialable books. Some were not available because other people rented them. Also, most librarys dont have all relevant books, so you have to check other library, contact people etc. Nowadays this process has changed a lot. The internet can be searched electronically, means you enter a term and google spits out thousands of hits. Sure, the art of searching still involves to know the right keywords and to filter out all the non-relevant crap, but still the process has improved A LOT but hey, this is what is called progess and we all want it, right? So it's a little bit difficult to tell schoolers to ignore all the complete information that are just a few mouse clicks away. But new technologies bring usually new problems. The internet provides tons of informations, but also tons of false/incomplete informations. So maybe a solution to the copy & paste dilema is to focus on validation of information instead of simply collecting informations. Just my two cents. Regards FalkArticle: 97274
Hello all, I am thinking of building a device which will convert DVI output from my graphics card to LVDS to drive my LCD panel. I was originally thinking of using ICs but I wondered if it was possible to do using an fpga? I have a few general questions regarding using LVDS to drive an lcd panel... >From studying TMDS (DVI signal) and LVDS I have found they are quite similar. Is it possible to simple translate the 10bits TMDS stream to its 8bit RGB value and then send that out at a slower clock speed over the LVDS interface? If I have this correct, my understanding is DVI works at a much higher frequency than my LCD needs (40MHz). Can i simply 'sample' the DVI signal every 4 clock cycles (if I use the clock/4 from the DVI input), for example? Also the datasheet for my LCD panel indicates it does not specfically have pins for timing information. I have seen chips from National Semiconductors which output LVDS but require vsync and hsync parameters - I am unsure how this fits into my project - can I not simply send the data to the LCD panel every clock cycle? Lastly. I am thinking of using a Spartan3 based board (possibly the Raggedstone - http://www.enterpoint.co.uk/moelbryn/raggedstone1.html) to do the conversion. Is this board suitable? Any advice will be greatly appreciated. Regards, Kevin
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