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Hello all I am trying to estimate the size of a project which will include an ARCnet interface. I don't have access to the ARCnet spec (not freely available) at the moment so I can not give any number. If anyone has good pointers or a quick rule of thumb... Thanks in advance Nicolas PS don't tell me I will need the spec, I already know :o)Article: 97501
swimmer_@gmx.de wrote: > hello PeteS, > I like to use all kind of DDR2 Ram modules fitting in the DDR2 SoDIMM > Socket (200pin). I looked at the micron page and found the data sheet > for MT8HTF6464HD. Actually there are no timing information. When I use > instead the information from the micron chips on the module itself, I > need to add something for the traces on the module. > I think the absolute trace length doesnt matter - the Xilinx MIG core > compensates for that. > Maybe I need to buy the ML461 Reference Board from Xilinx. > Are there any layout rules? > Are the schematics included? > does anybody have the layout rules and schematics? > > thanks > pit Try this datasheet: http://download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf It's a typical DDR2 device from Micron and has *tons* of timing specs. Absolute length to the device does matter for a number of reasons (deterministic jitter being one of them, turnaround time being another) although if the core can take care of the turnaround timing it will help. For the timing budget, there are two budgets that are inter-related 1. CK/#CK to address / command 2. CK/#CK to data. 1. is unidirectional and fairly simple. 2. is bidirectional and not simple at all. To give you an idea of what is involved: Read: The various Dn lines will have some skew across them (and relative to DQS as an output) that must be subtracted from the timing budget. All clock to data uncertainties must be subtracted. All timing uncertainties in the core relative to read data must be subtracted. Write: All timing uncertainties in the core relative to write must be subtracted. All timing uncertainties in the DDR2 relative to latching data must be subtracted. After all that, you get to figure out how much mismatch you are permitted in the board on the D[group] as a group, D[group] vs. CK, CK - #CK, CK to address/command and so forth. The last time I set up a timing error budget it took me a couple of days just to set the budget. Cheers PeteSArticle: 97502
PeteS wrote: > One thing I did not mention that *has* given me a great deal of grief > on DDR is Vref. DDR requires this to be V(mem) / 2 and the clock > crossings have to be within a tight range of this, to say nothing of > the other signals. > > if Vref is produced by a resistive divider with a cap, you might have > an issue with just *some* memory sticks - they pull more from Vref than > the divider can stand (it's not stiff enough) and you'll get all sorts > of flaky (particularly read) behaviour. The standard behaviour of > devices is such that the current drawn from Vref is temperature > dependent, too, which you are seeing. > > Stick a scope probe on Vref somewhere with a 'bad' stick and see if it > remains at the proper level (or if it even gets to the proper level). > > Cheers > > PeteS Another point on using Virtex II and Vref. The tools will automatically determine whether Vref is required for a particular bank based on the inputs to that bank. I have had a problem in the past where I did not realize that my SSTL signals on one bank were all outputs (Address and Control lines). For this bank, I had the Vref pins tied to a source with a relatively high impedance. The Vref pins were not required for Vref on that bank and so the tools automatically defaulted them to weak pullups. The half dozen "weak" pullups were enough to bring the Vref up to almost 2 volts. This is worth checking if you are not using all of the connections on the board, for example leaving out a feedback input. If you inadvertently free up the Vref pins on a bank they could get you in trouble. In my design I fixed the problem by setting the BitGen defaults to "Float" for unused IOB pins. Regards, GaborArticle: 97503
PeteS wrote: > swimmer_@gmx.de wrote: > > hello PeteS, > > I like to use all kind of DDR2 Ram modules fitting in the DDR2 SoDIMM > > Socket (200pin). I looked at the micron page and found the data sheet > > for MT8HTF6464HD. Actually there are no timing information. When I use > > instead the information from the micron chips on the module itself, I > > need to add something for the traces on the module. > > I think the absolute trace length doesnt matter - the Xilinx MIG core > > compensates for that. > > Maybe I need to buy the ML461 Reference Board from Xilinx. > > Are there any layout rules? > > Are the schematics included? > > does anybody have the layout rules and schematics? > > > > thanks > > pit > > Try this datasheet: > http://download.micron.com/pdf/datasheets/dram/ddr2/512MbDDR2.pdf > > It's a typical DDR2 device from Micron and has *tons* of timing specs. > > Absolute length to the device does matter for a number of reasons > (deterministic jitter being one of them, turnaround time being another) > although if the core can take care of the turnaround timing it will > help. > > For the timing budget, there are two budgets that are inter-related > > 1. CK/#CK to address / command > 2. CK/#CK to data. > > 1. is unidirectional and fairly simple. > 2. is bidirectional and not simple at all. > > To give you an idea of what is involved: > Read: > The various Dn lines will have some skew across them (and relative to > DQS as an output) that must be subtracted from the timing budget. All > clock to data uncertainties must be subtracted. All timing > uncertainties in the core relative to read data must be subtracted. > Write: > All timing uncertainties in the core relative to write must be > subtracted. All timing uncertainties in the DDR2 relative to latching > data must be subtracted. > > > After all that, you get to figure out how much mismatch you are > permitted in the board on the D[group] as a group, D[group] vs. CK, CK > - #CK, CK to address/command and so forth. > > The last time I set up a timing error budget it took me a couple of > days just to set the budget. > > Cheers > > PeteS For impedances, see the IBIS models. I usually use 60 ohm tracks and terminate into 50 ohms to Vref for address, series terminate in the middle for short traces on data (although you can get away with no termination on point to point **if** you can set the drivers at each end to be about 60 ohm impedance (which is possible on the DDR device through the extended mode register) and by setting the output drive on the FPGA core (or setting Rtt bits if available). Note if you do this, your Vref driver needs to be able to source *and* sink current. CK//#CK should be differentially terminated as close to the DDR device pins as possible, normally into about 100 ohms, but this depends on the driver. It's possible a SODIMM will already have the terminators onboard, but you need to check. There should be some guidance on the effective impedance of the system. Cheers PeteSArticle: 97504
Hallo, I would realize a microcontroller based on powerpc. It will be connected to bus plb at 100MHZ. If I use plb2opb_bridge, may I connect a opb_bus at 50 MHz? Many Thanks MarcoArticle: 97505
Could also be USD 2000+ if it is a big fast one like the ones we are buying. Depends on what you want. John Adair Enterpoint Ltd. - Home of Broaddown4. The Ultimate Virtex-4 Development Board. http://www.enterpoint.co.uk "Antti" <Antti.Lukats@xilant.com> wrote in message news:1140693327.038485.61210@g47g2000cwa.googlegroups.com... > around 100 USD maybe a little above >Article: 97506
hello, I have max 7128s with blocked ISP. The ISP port is set off. How to erase eeprom without using special Altera APU programmer? How to construct simple programmer only for erase? Is it possilbe to reprogram this device via JTAG after any modification? Thanks DarJan Poznan University of TechnologyArticle: 97507
Hi tanks for the help I have looked up the appnote for using BRAM and the PLB-bus. They speak of "IP2IP_Addr but what those that means? I think I don't have addresses in my IP or do I have them and I don't know about it. How can you have addresses in your IP? Can anyone tell me more about this? Greets MichArticle: 97508
Jan Panteltje wrote: > Just a partial reply... I think 7400 series should stop way below 200mHz, > perhaps 50MHz? It's either a 74AC04 or possibly a 74HC04 (it's upside down so I can't tell) and it's self oscillating at 294 mhz - (it's stable enough for the counter to read... a fast scope shows it approximately as a sinewave. It seems to be oscillating at about 1/tpd... can't even really pull it much with finger capacitance - only about 10 mhz. Interestingly, if I short a the floating input-output pair of an unused inverter with the scope probe, that runs a bit slower around 260 mhz... wheras the gate in use has about 20k of resistance in the feedback path. > I would make a small diff amplifier, did something 40 years ago (yes 40!) > with I think it was BFY90 transistors, then invert with 2 more and drive > the LVDS input. I may give your transistor circuit a try, either with components or simulation, thanks.Article: 97509
Hi, We're trying to move our development and testing of VHDL code towards an automatic testing and validation system. Here's the idea: if I change something in the code, I would run something that would compile and test the whole thing and give an alarm if something else broke. I'm curious as to what you guys in the industry use. An obvious approach would be to build a very thorough test vector file and run it every time and look for mismatches between expected data and actual results. Is this the best approach? How about running it automatically? Do you have any ideas/experience on this matter that you could share? Thanks in advance, EmanuelArticle: 97510
you need to read the IPIF documentation, this is an middle IP layer that is used to connect things to OPB and PLB anttiArticle: 97511
"metal" <nospam@spaam.edu> wrote in message
news:7bnqv15u98kpc9cnll2suuubkmf9a4sm0o@4ax.com...
> What a schem/block gives one is the -connectivity-, and
> at a -glance-. I think that's what I was trying to get at....the ease
> of seeing -interrelationsips- in a graphical format.
I don't think many people would dispute that a well-drawn block diagram
makes it much easier to visualize a system than the equivalent pile of VHDL
port map statements. But as soon as the number of components, their sizes,
and their interconnection patterns have to change according to the
configuration of the system or subsystem -- i.e. as soon as you have a
generic, re-usable design -- then schematics become virtually unusable.
Try drawing schematics for an arbitrarily-sized tree of binary adders.
Wouldn't that be a useful thing to have in your library of re-usable IP for
future projects? With VHDL this is a breeze. Good luck with the
pictures-only version. And as soon as you have to contemplate writing
scripts (text!) to generate or alter schematics, you've given up the fight.
One of the powerful things about a block diagram is that I can draw:
+-----+ +---------+
| | WIBL | |+
| A |========| B ||+
| | | |||
+-----+ +---------+||
+--------+|
+-------+
...and it says "there's widget A connected to several widget Bs via the
Widget Interconnect Bus Lines". In my HDL source code I can see the various
bus signals and the exact number of Widget Bs and all the other details of
the design that shouldn't be visible at this high level. As soon as they
make these types of diagram compilable, maybe I'll be a graphical design
entry convert! But such powerpoint-to-gates technology is not available
today...
Cheers,
-Ben-
Article: 97512But I have attached my IP and the BRAM on the PLB why the connection between OPB and PLB MichArticle: 97513
I had the same problems. Lately there was published a solution in Xilinx knowledge base. The solution: EDK, then SP1!!!! and then SP2 It works now for me. Cheers >Hi > >does anyone have had full success using the xilinx platform USB Cable and >XMD in EKD 7.1? >I was trying to check out the 'star wars' movie demo supplied by avnet with >their uClinux Virtex4 reference design, but unfortunatly my new PC has no >printer port so I am bound to use the latest and best ?? USB JTAG cable from >Xilinx. > >and unfortunatly XMD 7.1 doesnt seem to like the cable :( at first I assumed >this being a problem related to Virtex 4, but now checking with Virtex2Pro, >same problem... XMD just doesnt seem to handle usb cable. > >is there some trick or fix? and yes I have all the latest service packs >installed! > >Antti > >http://www.sipsik.net > > >Article: 97514
hi i am doing a project on altera fpga. i need to implement byteblaster in microcontroller so that i can configure fpga using microcontroller.but i am not able to get the source code of byteblaster.if anyone help me in getting the source code please email me immediately i need it urgently ( i am also ready to pay for it)Article: 97515
Hi, I am working on a 10 Gigabit Ethernet Projet. I have to choose a High-Speed Development Board. I don't know yet which kind of FPGA I am going to use. (Altera or Xilinx). I saw on Altera's Web Site the "Stratix GX High-Speed Development Board" http://www.altera.com/literature/ug/ug_stx_gx_hs_dev_kit.pdf I saw on Altera's Web Site a second High Speed Development: "Stratix II High-Speed Development" http://www.altera.com/literature/ds/ds_stratix.II_hs_dev.board.pdf I found the equivalent on Xilinx's Web Site. But I found nothing. Can you confirm me that nothing equivalent of these 2 High Speed Development Board of Altera is realised by Xilinx?Article: 97516
On 23 Feb 2006 06:49:32 -0800, the renowned cs_posting@hotmail.com wrote: >Jan Panteltje wrote: > >> Just a partial reply... I think 7400 series should stop way below 200mHz, >> perhaps 50MHz? > >It's either a 74AC04 or possibly a 74HC04 (it's upside down so I can't >tell) and it's self oscillating at 294 mhz - (it's stable enough for >the counter to read... a fast scope shows it approximately as a >sinewave. > >It seems to be oscillating at about 1/tpd... can't even really pull it >much with finger capacitance - only about 10 mhz. > >Interestingly, if I short a the floating input-output pair of an unused >inverter with the scope probe, that runs a bit slower around 260 mhz... >wheras the gate in use has about 20k of resistance in the feedback >path. > >> I would make a small diff amplifier, did something 40 years ago (yes 40!) >> with I think it was BFY90 transistors, then invert with 2 more and drive >> the LVDS input. > >I may give your transistor circuit a try, either with components or >simulation, thanks. What about using a stand-alone LVDS receiver? Eg. Pericom PI90LV179W.Article: 97517
Hi, I'm making a board with a Spartan3 XC3S200, half of its pins available as I/O are yet occupied and I'd like to bring all the others so far unused to a common connector in order to have them ready for future use. I'm now working with xapp623 (PDS) to select the decoupling capacitors. My question is, as far as I don't know if I'll use the free I/O as input or output, could I place one decoupling capacitor for each Vcco-GND pair? I mean, placing more decoupling that what you really need is only a waste of space or is a completely wrong approach? I suppose that more capacitors is better than less, i.e. I do not have to place less decoupling that what suggested in xapp623, but I can decide to do more than that. Thanks, MarcoArticle: 97518
cs_posting@hotmail.com wrote: > The other day I found myself needing a short gate time ~200 mhz > frequency counter for an automated test, and since I had an FPGA board > on hand I whipped one up quickly. Getting it reading and reporting to > my computer was the easy part. > > Ah, the input stage.... > > I've got about 4dBm of RF into 50 ohms to play with - about a volt p-p > or a little more if it's high-Z. The output of the device under test > has a transformer and then a series cap to create an unbalanced output. > > > I did something ugly with a 3.3v cmos 7406 varient and a feedback > resistor, which works well enough to get an accurate reading on one > version of the device under test, but not on the other (both have been > verified with real test equipment) It also tends to self-oscillate > with no input... I'm surprised any CMOS 7406 variant really goes to 200MHz! I think you got lucky with the one that did work. > What would be the right way to do this using on hand parts, such as > abused logic, little 1:1 or 2:1 RF transformers, etc? I like high-speed comparators (often called "differential receivers" or "LVDS receivers" on the spec sheet) for this. > One idea is to > use another gate with a feedback resistor and cap to ground in the hope > of establishing the threshold level, and then using a transformer to > swing another input above and below this. Most parts on hand are SMD - > which means dead bug construction in SOIC scale under the maginifier - > discourages extensive experimentation. The nice thing about differential receivers are: 1. Easy to set the comparison level. 2. Lowish input impedance but not too low, such that you set the impedance by putting a 50 or 100 or whatever ohm resistor there. 3. At least for the non-LVDS parts, there's only one or two receivers per package so even when it's not SMD it's easy to do dead-bug prototyping. 4. They already have some semblance of defined open-circuit response (usually called "fail-safe" for some bizarre reason in the spec sheets) to prevent oscillating. > Why do most abuse-of-logic RF applications seem to use NAND gates > rather than inverters? From a digital perspective NAND gates are a > universal element, but once you tie their inputs together, is there > something to be gained from having two inputs in parallel? Usually the hex inverter packages cost a little bit more than the 4xNAND gate packages. It's nice to have the extra input to act as an enable etc. And once you start running these parts into the linear region you probably do not really trust using the other sections for other functions. > Is there a way to use a differential input configuration on an FPGA to > input a balanced RF signal directly? Theoretically this should be an > FPGA clock input... The device in use currently is an Altera Stratix > II, but a Xilinx S3 kit is available. You can even feed in non-balanced RF subject to some limitations. > If ordering things, what would be a good default low supply voltage > HF/VHF gain component to have on hand? I seem to recall lots of > last-millenium ham designs using the MC1350P video IF amp, but what > would make sense today? VHF? MMIC's, at least as long as you have only need for AC coupling. Tim.Article: 97519
Finn, The stepping 0 program should be very conservative. I doubt what you are seeing is related to the 120 MHz limitation on the step 0 parts. Have you checked the incoming duty cycle? And yes, both CLKIN and CLKFB share the same specifications. So you also need to check the duty cycle of the CLKFB as well. We spec from 45% to 55% for all operation. Austin Finn S. Nielsen wrote: > Hello All, > > Does anyone know what the real max DCM CLKIN speed of Spartan-3E stepping 0 > is. In the datasheets it says 90 Mhz but in the errata is says 120 MHz. > We have one design (with clock feedback from an external pin) where it fails > at 100 MHz... > Does the same speed limit apply to the CLKFB pin as well.. > > Thanks, > > Finn > >Article: 97520
Hello, Ivan: In your case, how do you deal with the contension when MB and the Coprocessor to the BRAM? And I don't understand why do you use FSL interface to connect the BRAM but not OPB? Thank you very much for your help. I want to build a system as the following. So the OPB arbitrator can deal with the contension when both MB and Coprocessor access the same address in BRAM at same time. MB(M1)<--->FSL Interface<--->Coprocessor(M2) | | | | |---OPB(with arbitrator)-----------|----------------->BRAMArticle: 97521
Anybody here with experiences with syntetising some 8051 core with JTAG debugger in FPGA ? What core can you recommend ?Article: 97522
Just to update your story, regarding the LatticeSC. The SC25 is shipping now as we have a few samples for a board to be built early next month.Article: 97523
Emanuel Machado wrote:
> if I change something in the code, I would run something that would compile
> I would run something that would compile and test the whole thing
Step one is to start using source control: CVS, subversion etc.
Step two is to write a script that checks out everything
into an empty directory and generates a Makefile for sim and/or synth,
does a make, and runs some vsim command on the top entity.
Step three is to run the script continuously and
make the log files available to anyone interested.
-- Mike Treseler
Article: 97524On 21 Feb 2006 02:45:18 -0800, "SaHiD" <sahi.cse@gmail.com> wrote: >Please Give me outline of doing a project of dsp processor design. 1) Pick an application that needs DSP. i.e. Radar with beam forming 2) Write a project specification. i.e. 500 page MS-Word document 3) Extract the DSP part of the project. i.e. Do beam forming 4) Select a DSP chip. i.e. TMS320CV5416 from Texas Instruments 5) Download the free eval version of their software 6) Do the project 7) Learn to write newsgroup posts with sufficient explanation of what you want and what work you have done on it yourself so that there is a reasonable chance that someone could give you a useful answer.
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