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Messages from 97375

Article: 97375
Subject: Re: WebPACK license (and Quartus Web Edition too).
From: Steve Lass <lass@xilinx.com>
Date: Tue, 21 Feb 2006 11:40:51 -0700
Links: << >>  << T >>  << A >>
zlyh wrote:
> I'm Xilinx user, but interestingly to hear Altera users too.
> 
> Everybody knows what WebPACK is free. How long does it free? I see
> followng in the license when I install W.P.:
> "4.Term... this License is effective for one (1) year ... If you wish
> to extend this License, you must contact XILINX ... to determine the
> additional fees, terms and conditions ..."
> 
> What I need to do after one year?
You download the new version of WebPACK (which is free) and agree to
that licence agreement.
  Ask Xilinx to extend free license?
No.  Nobody has ever asked to extend a free license.

Steve

> Does anybody ask Xilinx to extend WebPACK free license? Is there
> anybody who can't extend license?
> 


Article: 97376
Subject: Re: ISE Simulator Price
From: Steve Lass <lass@xilinx.com>
Date: Tue, 21 Feb 2006 11:49:29 -0700
Links: << >>  << T >>  << A >>
Hendra,

ISE Simulator Lite is included free with WebPACK and Foundation.  It has 
limit
of around 10,000 lines of code.

ISE Simulator is only available to Foundation customers and costs $995.  It
has no line limit.

Steve

Hendra wrote:

> What is the price for ISE Simulator? There is no mention of it in
> Xilinx Online Store. How does it compare to ModelSim Xilinx Edition
> III?
> 
> Hendra
> 


Article: 97377
Subject: Re: Is FPGA code called gateware?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 21 Feb 2006 10:52:42 -0800
Links: << >>  << T >>  << A >>
Brannon wrote:
> I've heard it referred to as gateware for a long time where I work. I
> think that's a fine name.

I fifth the motion.
All in favor of gateware say aye.

      -- Mike Treseler

Article: 97378
Subject: Re: Is FPGA code called gateware?
From: Bob Perlman <bobsrefusebin@hotmail.com>
Date: Tue, 21 Feb 2006 10:58:29 -0800
Links: << >>  << T >>  << A >>
On Tue, 21 Feb 2006 10:52:42 -0800, Mike Treseler
<mike_treseler@comcast.net> wrote:

>Brannon wrote:
>> I've heard it referred to as gateware for a long time where I work. I
>> think that's a fine name.
>
>I fifth the motion.
>All in favor of gateware say aye.
>
>      -- Mike Treseler

Sounds good to me.  Anything that disabuses people of the notion that
FPGA design is the same as or similar to software design meets with my
approval.

Bob Perlman
Cambrian Design Works
http://www.cambriandesign.com

Article: 97379
Subject: Re: Is FPGA code called gateware?
From: Tim Wescott <tim@seemywebsite.com>
Date: Tue, 21 Feb 2006 11:09:17 -0800
Links: << >>  << T >>  << A >>
Bob Perlman wrote:
> On Tue, 21 Feb 2006 10:52:42 -0800, Mike Treseler
> <mike_treseler@comcast.net> wrote:
> 
> 
>>Brannon wrote:
>>
>>>I've heard it referred to as gateware for a long time where I work. I
>>>think that's a fine name.
>>
>>I fifth the motion.
>>All in favor of gateware say aye.
>>
>>     -- Mike Treseler
> 
> 
> Sounds good to me.  Anything that disabuses people of the notion that
> FPGA design is the same as or similar to software design meets with my
> approval.
> 
> Bob Perlman
> Cambrian Design Works
> http://www.cambriandesign.com

Yea verily.  I do a lot of embedded software development, and a bit of 
FPGA design.  While Verilog may bear a passing resemblance to C the 
thought processes that go into FPGA design vs. software design are 
considerably different.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

Article: 97380
Subject: Re: Is FPGA code called firmware?
From: Tim Wescott <tim@seemywebsite.com>
Date: Tue, 21 Feb 2006 11:09:57 -0800
Links: << >>  << T >>  << A >>
Brannon wrote:

> I've heard it referred to as gateware for a long time where I work. I
> think that's a fine name.
> 
I think I'll start using that -- at least where I think it has a chance 
to stick.

-- 

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Posting from Google?  See http://cfaj.freeshell.org/google/

Article: 97381
Subject: Virtex2: can I really just leave M1,M2,M3 pins floating?
From: "ML" <geewhiz1@optonline.net>
Date: Tue, 21 Feb 2006 14:37:36 -0500
Links: << >>  << T >>  << A >>
Hi all, for a Virtex II part, for slave serial mode, can I REALLY leave M1, 
M2, M3 pins floating or is it safer to tie them to VCCaux ?

ML 



Article: 97382
Subject: Re: Is FPGA code called gateware?
From: "Isaac Bosompem" <x86asm@gmail.com>
Date: 21 Feb 2006 11:58:24 -0800
Links: << >>  << T >>  << A >>

Mike Treseler wrote:
> Brannon wrote:
> > I've heard it referred to as gateware for a long time where I work. I
> > think that's a fine name.
>
> I fifth the motion.
> All in favor of gateware say aye.
>
>       -- Mike Treseler

aye,

For me the biggest hurlde of learning to utilize VHDL was programming
my brain to not think of it as a programming language. Then everything
began to fall into place.

-Isaac


Article: 97383
Subject: Re: Is FPGA code called firmware?
From: "JJ" <johnjakson@gmail.com>
Date: 21 Feb 2006 12:36:11 -0800
Links: << >>  << T >>  << A >>
Except there really aren't any useable gates in the FPGA, LUTs only
model them and other functions that might be built of gates in an ASIC.
We hardly think in terms of gates do we, usually equations, registers
and memory blocks otherwise we would still be using schematics.

I'd would offer bitware since we also use bitfiles, maybe boolware,
lutware, flexware, mixware, dunnoware, undewear:-).

Some other thoughts

Now to those who rail that xxxxware isn't software just because Verilog
also uses some C style syntax. What happens if say SystemVerilog is
used to describe a system with both hardware & software components,
half (mostly the parallel part) being synthesized and the rest being
executed by a cpu in the FPGA. Suppose that cpu is in control of
dynamic reconfiguration and allows hardware blocks to be loaded at
will. Right now we have no language to support this (do we?). What
about the far future when the onboard processor(s) might even run the
synthesis locally on demand. Maybe too much coolaid.

One should also note the industry shift by Intel, AMD, IBM to 2, 4 and
n way cores and multithreaded cpus. Eventually the software industry
will look over our shoulders and see that hardware guys have had
parallel figured out for 50+ years and don't fall over themselves with
it. They might even notice that SystemVerilog includes a good chunk of
C and that Verilog seems to describe concurrency pretty well too. For
the most part software guys even OS and language experts (not embedded)
have zero clue about our side of the language fence v the 1000s of
languages they reinvent all the time.

A lite version of Verilog combined with a subset of C++ that describes
processes as objects as well as Verilog describes modules using C
syntax all the way might be an attractive alternative to the rather
biggish SystemVerilog. It might allow all execution as code with a
provided runtime event wheel or might be synthesized to hardware or any
mix of the two, at least its one language. Not sure when that might
arrive but it would be alot better than most of these parallel C
dialects that haven't been thought out to well like Jave, C# which
completeley ignored CSP theory.



John Jakson
transputer guy


Article: 97384
Subject: Re: Is FPGA code called firmware?
From: ghelbig@lycos.com
Date: 21 Feb 2006 13:03:33 -0800
Links: << >>  << T >>  << A >>
Here, we usually call it "broken".  On rare occasions we will call it
"the bitstream" or "the configuration file".

$0.02


Article: 97385
Subject: Re: FPGA - software or hardware -2-
From: Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com>
Date: Wed, 22 Feb 2006 10:04:32 +1300
Links: << >>  << T >>  << A >>
Hal Murray wrote:
>>The problem is that the regs require similar levels of documented
>>development processes for life support as they do for any supporting
>>medical electronics, such as imaging products.
> 
> 
> How many people know the story of the Therac-25?
> 
> Is that life support gear?  Imaging?

Is that the famous one about the X-ray machine that irradiated people 
with 100X dose?

That case you could call imaging, but the consequences of the particular 
failure (lethal radiation doses) are a little different from, for 
instance, the failure of a blood pressure machine.

2c
Jeremy

Article: 97386
Subject: Relative placement constraints in Xilinx ISE w/ Verilog
From: "nestorj@lafayette.edu" <nestorj@lafayette.edu>
Date: 21 Feb 2006 13:07:21 -0800
Links: << >>  << T >>  << A >>
I am building a design which consists of a two-dimensional array of
smalll processing elements, each of which contains about 60 LUTs.  The
two dimensional array is constructed in Verilog by creating a "column"
module which contains instances all of the PEs in a column  An "array"
module then puts together the columns.

I would like to create placement constraints to make the placer follow
the array structure.  So I dug around in the documentation and found
"RLOC", which sounds like it specifies what I want.  So I added
constraints to each column array that look something like this:

module PE_column(blah blah)

    PE_instance C0(blah blah blah);
    // synthesis attribute RLOC of C0 is "x0y0"

    PE_instance C1(blah blah blah);
    // synthesis attribute RLOC of C1 is "x0y1"

   etc.

endmodule

I tried something similar with to place the columns at X0y0, x1y0, etc.
at the next level up in the hierarchy.

When I run XST, it dutifully reports the constraints, but the placer
apparently ignores them.

If someone could point out what I'm missing, I'd really appreciate it.
Is it necessary to make the lower-level instances RPMs?  If so, what is
the (currently) easiest way to do this?

BTW I am using XST in ISE 7.1.03I compiling to a Xc2v6000.

Thanks!

  John Nestor
  Lafayette College


Article: 97387
Subject: Communication between FPGA and PC with ethernet card
From: "aayush" <aayush_v2@rediffmail.com>
Date: 21 Feb 2006 13:20:50 -0800
Links: << >>  << T >>  << A >>
hello
i am doing a project called "10 BASE T ETHERNET INTERFACE USING FPGA"
i am using a xilinx's spartan2   XC2S50 chip and using VHDL.now i
wanted to ask if any of u have any information on the codes of VHDL
that i'll be needing and related stuff.
if u happen to have any thing at all kindly send them to me. another
question.
  ethernet traffic is digital. now a logic "zero" must be a
band of voltage and similarly a logic "one". now i wanted to ask if i
am
using a 10/100 Mbps ethernet card or lan card as they are called what
will be my voltages level. ie the RJ 45 female of my lan card will send

a logic "0" at which voltage/voltage band  and on what voltage/voltage
band will be logic"1". its important to find these as i am connecting
FPGA to lan card and hoping that signals fm lan card does not blow up
the damn chip.
  your early positive reply will save me lots of time.hope u will be
able to able to spare some time.
thanku all


Article: 97388
Subject: Re: FPGA - software or hardware -2-
From: fpga_toys@yahoo.com
Date: 21 Feb 2006 13:33:55 -0800
Links: << >>  << T >>  << A >>

Jeremy Stringer wrote:
> That case you could call imaging, but the consequences of the particular
> failure (lethal radiation doses) are a little different from, for
> instance, the failure of a blood pressure machine.

Or a throttle control system or ABS system that fails causing you and
your car/truck/suv to be in harms way resulting in injury. Or a fire
alarm system that fails in a a major high rise. Or a train crossing
system for gating pedestrian and vehicles at a major crossing where
fast trains frequent a blind track access. There are lots of systems
that can cause harm with failure.


Article: 97389
Subject: Re: Is FPGA code called gateware?
From: fpga_toys@yahoo.com
Date: 21 Feb 2006 13:47:37 -0800
Links: << >>  << T >>  << A >>

Isaac Bosompem wrote:
> For me the biggest hurlde of learning to utilize VHDL was programming
> my brain to not think of it as a programming language. Then everything
> began to fall into place.

Interesting discussion. In a prior discussion regarding "programming"
or "designing" with C syntax HLL or HDLs, it was interesting how many
people took up arms that they could do everything in VHDL or Verilog
that could be done with a C based fpga design language such as
Celoxica's Handel-C, Impulse-C, FpgaC or similar tools. That arguement
was that VHDL/Verilog really isn't any different that C based HLL/HDL's
for FPGA design, and frequently with the assertion that VHDL/Verilog
was better.

Now, we have the looks like a duck, walks like a duck, quacks like a
duck, must be a duck argument that if in fact VHDL/Verilog is some
equivalent to C based HDL/HLL's, then it's probably has some
significant aspects of software development, rather than gate level
schematic based hardware design.

So is an fpga design in VHDL/Verilog hardware, and the same realized
equiv gates written in in Celoxica's Handel-C software just because of
the choice of language?  Or is a VHDL/Verilog design that is the same
as a Handel-C design software?


Article: 97390
Subject: Re: Is FPGA code called gateware?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 21 Feb 2006 13:57:42 -0800
Links: << >>  << T >>  << A >>
Isaac Bosompem wrote:

> aye,
> 
> For me the biggest hurdle of learning to utilize VHDL was programming
> my brain to not think of it as a programming language.

Yes. The trickery is that synthesis code describes
a testable simulation model, not hardware.

Hardware which matches this model is inferred
based on the device, Fmax and other constraints.

The "software" aspect to rtl code
just answers the question:

"Oh, another clock, what should we output this time?"

      -- Mike Treseler

Article: 97391
Subject: Re: Is FPGA code called gateware?
From: "Gabor" <gabor@alacron.com>
Date: 21 Feb 2006 14:07:12 -0800
Links: << >>  << T >>  << A >>
Just to throw in my 2 cents on the semantics of FPGA configuration
code/bitstream/whatever...

In the software realm, software vs. firmware is generally the
difference
between something easily changed (i.e. stored on your hard
disk) vs. something not as easily changed (i.e. stored in a ROM).

There is a bit of grey area here, like the BIOS in your PC which is
in a flash memory in most modern systems and can be upgraded
by running a program you download from the Internet.  I would still
call it firmware, though.

At our company we call FPGA configuration code "software" if it
is stored on the hard drive and uploaded at run time by a user
application.  When it is stored in a serial PROM or flash memory
on the board we call it firmware.

I don't think the terms "firmware" or "software" have as much to do
with the programming paradigm as with the delivery of the bits to
make the actual hardware run.

Interesting thread...
Gabor

fpga_toys@yahoo.com wrote:
> Isaac Bosompem wrote:
> > For me the biggest hurlde of learning to utilize VHDL was programming
> > my brain to not think of it as a programming language. Then everything
> > began to fall into place.
>
> Interesting discussion. In a prior discussion regarding "programming"
> or "designing" with C syntax HLL or HDLs, it was interesting how many
> people took up arms that they could do everything in VHDL or Verilog
> that could be done with a C based fpga design language such as
> Celoxica's Handel-C, Impulse-C, FpgaC or similar tools. That arguement
> was that VHDL/Verilog really isn't any different that C based HLL/HDL's
> for FPGA design, and frequently with the assertion that VHDL/Verilog
> was better.
>
> Now, we have the looks like a duck, walks like a duck, quacks like a
> duck, must be a duck argument that if in fact VHDL/Verilog is some
> equivalent to C based HDL/HLL's, then it's probably has some
> significant aspects of software development, rather than gate level
> schematic based hardware design.
>
> So is an fpga design in VHDL/Verilog hardware, and the same realized
> equiv gates written in in Celoxica's Handel-C software just because of
> the choice of language?  Or is a VHDL/Verilog design that is the same
> as a Handel-C design software?


Article: 97392
Subject: Re: Is FPGA code called gateware?
From: Mike Treseler <mike_treseler@comcast.net>
Date: Tue, 21 Feb 2006 14:09:15 -0800
Links: << >>  << T >>  << A >>
fpga_toys@yahoo.com wrote:

> Interesting discussion. In a prior discussion regarding "programming"
> or "designing" with C syntax HLL or HDLs, it was interesting how many
> people took up arms that they could do everything in VHDL or Verilog
> that could be done with a C based fpga design language such as
> Celoxica's Handel-C, Impulse-C, FpgaC or similar tools. That arguement
> was that VHDL/Verilog really isn't any different that C based HLL/HDL's
> for FPGA design, and frequently with the assertion that VHDL/Verilog
> was better.

Yes. The only advantage to C-based HDLs
is that lots of people already know C.

> Now, we have the looks like a duck, walks like a duck, quacks like a
> duck, must be a duck argument that if in fact VHDL/Verilog is some
> equivalent to C based HDL/HLL's, then it's probably has some
> significant aspects of software development, rather than gate level
> schematic based hardware design.

Yes. Version control, Checkout into an empty directory,
Makefile generation and regression testing is just as effective
on an hdl project as it is on a C++/Java project.

> So is an fpga design in VHDL/Verilog hardware, and the same realized
> equiv gates written in in Celoxica's Handel-C software just because of
> the choice of language?  Or is a VHDL/Verilog design that is the same
> as a Handel-C design software?

They are just different simulation models of the same thing.

         -- Mike Treseler

Article: 97393
Subject: Re: FPGA - software or hardware -2-
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 22 Feb 2006 11:25:54 +1300
Links: << >>  << T >>  << A >>
Hub van de Bergh wrote:
> The background for my question whether an FPGA is viewed as software or as
> hardware comes from the regulations for medical devices.
> 
> From the perspective of regulatory requirements it makes a difference
> whether an FPGA is viewed as software or as purely hardware because of
> regulatory requirements for medical devices are more comprehensive when
> software is involved.

  Well, software certainly IS involved in creating the Bitstream, and
if you read the user feedbacks on ISE V8.x and all the bug issues,
you will see this will require strict version control in anything medical.
  ie Develop/Test/Maintain with ONLY one version of the software.


> Regulatory requirements for medical devices are focussed on safety and
> reliability of the finished medical device. If the resulting product cannot
> be tested in full - which is the case with software - then the regulations
> require to have controlled processes in place for (software) product
> development in order to minimize risks on hazardous situations.
> 
> Is anybody in this NG experienced in the field of applying FPGA's in medical
> devices and the view of regulatory bodies?

  Sounds like you'll need both processes. Some of the FPGA you CAN test 
in full, and in this area, it sounds like a more extensive 'self test'
mode would be a very good idea.
  Seems like one thing a FPGA can do very well
  It moves more of the system into a 'proven to work' tickbox, and out
of the 'we hope it still works' tickbox.

  Do you use a SoftCPU in this ? that is then clearly software.

-jg


Article: 97394
Subject: Re: Is FPGA code called gateware?
From: fpga_toys@yahoo.com
Date: 21 Feb 2006 14:29:34 -0800
Links: << >>  << T >>  << A >>

Gabor wrote:
> At our company we call FPGA configuration code "software" if it
> is stored on the hard drive and uploaded at run time by a user
> application.  When it is stored in a serial PROM or flash memory
> on the board we call it firmware."

Interesting.  So the devices which have flash/eeprom based "solid state
disks" (SSD) such as your typical hand held IPOD, Windows CE based
PDA's, are not "software" based systems?

heck even phones these days are becoming PDA's and MP3 players with
very large SSD's in flash. Even most new "platform flash" FPGA's load
off the same SSD's in the form of compact flash cards.

So if SSD's are the factor for software vs. hardware, then it seems
that any FPGA that loads and runs off SSD related storage technology,
is probably software by the looks like a duck, quacks like a duck, must
be a duck test. No? Why not?

Why is an FSM and data paths controlled by it when written in a C based
HDL/HLL software, and the same FSM and data paths written in
VHDL/Verilog hardware?

It wasn't that many years ago I wrote software/firmware/microcode for
bit sliced "processors" implementing 'smart' high speed data
controllers, but we called it hardware. Now I write
software/firmware/microcode AND instantiate it as hard LUT/FFs in
FPGA's and it just doesn't seem like hardware any more ... when the
same "code" can be moved to a $0.99 microprocessor with a PLD wrapped
around it as a cost reduction.


Article: 97395
Subject: bypass between ilogic and ologic
From: "Brannon" <brannonking@yahoo.com>
Date: 21 Feb 2006 14:32:16 -0800
Links: << >>  << T >>  << A >>
I'm using ISE 8.1.02. I seem to be having trouble making the BYPASS
attribute work on nets. As I understand it, it is supposed to go on the
net that is the output of an OBUFT. This should cause the TFB/OFB in
the ILOGIC block to be activated. FPGA Editor, though, shows no change
between building with or without the BYPASS attribute. Putting the
BYPASS attribute on any other line (including the inputs for the OBUFT)
or object gives me a warning about bad attribute placement.

I don't understand why Xilinx doesn't provide raw primitives for ILOGIC
and OLOGIC. It seems to me that would be just as easy as using the
IDELAY element, and it would allow me to connect the TFB/OFB directly.

I tried using IOPAD directly. IOPAD doesn't even show up in the
documentation as a valid primitive these days. NGDBuild seems to handle
it okay, though it does throw an INFO about raising that net to the
status of port. It did not, however, help with my BYPASS issue.

Another frustrating issue is that the BYPASS attribute doesn't even
show up in the standard documentation. I had to get it from here:
http://www.xilinx.com/xlnx/xil_ans_display.jsp?getPagePath=22137


Article: 97396
Subject: How to make Customized IP which connected with Microblaze through FSL access the OPB bus?
From: "fpga" <hy34@njit.edu>
Date: 21 Feb 2006 14:34:39 -0800
Links: << >>  << T >>  << A >>
I build a system which has a MicroBlaze, a LMB connect BRAM for local
instruction/data memory (8KB) and an OPB connected BRAM(64K) which will
be used as a shared memory for the Microblaze my user defined
coprocessor.

I connected my coprocessor with the MicroBlaze through FSL by using the
tool edit/import peripherals, but how can I make it to access the OPB
connected BRAM(64K). Do I have to write all the OPB ports manually in
the VHDL file in my coprocessor?

Thank you very much for your help.


Article: 97397
Subject: Xilinx ISE 6.3 confusion with CPLD logic results
From: "Dave Pollum" <vze24h5m@verizon.net>
Date: 21 Feb 2006 14:37:43 -0800
Links: << >>  << T >>  << A >>
My VHDL project has out grown a XC95108 CPLD, so I'll be using a
XC95144 instead.  After running the ISE synthesizer and fitter, all of
the XC95144's Function Block Inputs are used. Using exhaustive fit
mode, 92% of the function block inputs are used.  This still doesn't
leave much room for additional features.  I then told ISE to use a
XC95144XL, instead. Only 64% of the function block inputs are used, and

the other resources look good, too.  Even though the XL is a 3.3 volt
chip, it's 5 volt tolerant, so it should work.  The odd thing is that
the XL version uses _8 more_ flip flops than the standard version, and
the timing report shows that the XL is faster than the std part, even
though I selected 10 ns speed grade for both parts.  I haven't
simulated both chips yet.  There's lots of information in the Fitter
Report, but I don't know what I should be looking for.  I'm a bit
overwhelmed.  So far, the Xilinx docs haven't helped.
TIA,
-Dave Pollum


Article: 97398
Subject: Re: Is FPGA code called gateware?
From: Jim Granville <no.spam@designtools.co.nz>
Date: Wed, 22 Feb 2006 11:47:56 +1300
Links: << >>  << T >>  << A >>
Gabor wrote:

> Just to throw in my 2 cents on the semantics of FPGA configuration
> code/bitstream/whatever...
> 
> In the software realm, software vs. firmware is generally the
> difference
> between something easily changed (i.e. stored on your hard
> disk) vs. something not as easily changed (i.e. stored in a ROM).
> 
> There is a bit of grey area here, like the BIOS in your PC which is
> in a flash memory in most modern systems and can be upgraded
> by running a program you download from the Internet.  I would still
> call it firmware, though.
> 
> At our company we call FPGA configuration code "software" if it
> is stored on the hard drive and uploaded at run time by a user
> application.  When it is stored in a serial PROM or flash memory
> on the board we call it firmware.
> 
> I don't think the terms "firmware" or "software" have as much to do
> with the programming paradigm as with the delivery of the bits to
> make the actual hardware run.
> 
> Interesting thread...

  There is another thread, where this actually matters from a medical 
systems /regulatory basis.

  Since you must have SOFTWARE to create the bitstream, then the
admin has to include software-handling discipline.

  Many FPGA systems now include SoftCPUs, and that puts some portion
of the design clearly into the software box.

  -jg




Article: 97399
Subject: Re: FPGA - software or hardware -2-
From: fpga_toys@yahoo.com
Date: 21 Feb 2006 14:50:24 -0800
Links: << >>  << T >>  << A >>

Jim Granville wrote:
>   Seems like one thing a FPGA can do very well
>   It moves more of the system into a 'proven to work' tickbox, and out
> of the 'we hope it still works' tickbox.
>
>   Do you use a SoftCPU in this ? that is then clearly software.

Actually software is FSMs which operate on data streams, doesn't really
matter if the syntax of the language is one's and zeros (for us oldie
moldie coders), assembly language, basic, fortran, cobol, C, C++, Java,
Lisp,  .... or sequential VHDL statements which have functionally
equivalent syntax and high level expression syntax for floating point
equations, and lesser integer expressions.

Any hardware engineer that mistakes an FPGA design as 'proven to work'
didn't do their homework regarding SEU failures at altitudes well above
sea level ..... as nearly all static ram based designs are seriously at
risk.  Vertex-4's go a long way to help that with error detection on
config ram, but are not SEU immune yet.  Nor are microprocessors with
static ram for caches and other memory, while most dynamic designs are.




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