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Well this was actually meant for the serious posters silly. "Hans-Bernhard Broeker" <broeker@physik.rwth-aachen.de> wrote in message news:bb29ag$q5u$1@nets3.rz.RWTH-Aachen.DE... > In comp.arch.embedded Brett Foster <custserv@forums.ws> wrote: > > I thought this was largely disproven. Or at least the effect rather minimal > > (negligible). > > Depends on what kind of "trace" you're talking about. ;-P > > If it happens to be a proper race track for electrons, a.k.a. > high-energy particle accelerator, you'll have a rather "interesting" > time trying to survive standing on the outside of any of its curved > segments without heavy shielding in between. Kids: please _don't_ try > this at home! > -- > Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de) > Even if all the snow were burnt, ashes would remain.Article: 56076
Hi, I've been experimenting with xflow, but I still do not see why I would use it instead of a makefile, or within a script (c-shell, tcl, perl, etc.) It is hard to tell from Xilinx's documentation what the value of xflow is. But for one thing, it seems to be used in the edk environment to automate the build process. Any comments? *** AlfredoArticle: 56077
On 28 May 2003 06:27:27 -0700, iluvfpgas@yahoo.ca (Alfredo) wrote: >Hi, >I've been experimenting with xflow, but I still do not see why I would >use it instead of a makefile, or within a script (c-shell, tcl, perl, >etc.) > >It is hard to tell from Xilinx's documentation what the value of xflow >is. But for one thing, it seems to be used in the edk environment to >automate the build process. > >Any comments? With the exception of fpga editor and floorplanner, I haven't used a GUI from Xilinx for at least two years. Scripts work, and work well, and can be made to be surprisingly portable across tools. Allan.Article: 56078
Does anyone knows when new Xilinx serial PROMs (e.g XCF02S) will be available? I don't see them at distributors yet. -- Regards ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Robert PudlikArticle: 56079
Yes, One can put the input through a simple frequency doubler (see Peter's circuit tricks Xclusive), and then into the input. This gets the frequency down to 12 MHz for the DLL. One then uses the duty cycle correction ON (to help fix the asymmetry of the doubled clock). Since taps are updated every 6 times the 2's complement of the jitter filter settings, the asymmetry of the doubled clock does not violate the input jitter specification. Haven't tried this, but there is no reason why it shouldn't work. If anyone has it working, let us know. Austin Heavenfish wrote: > > So my question is if there any alternate way to implement both DLL and DFS > function when my input clk is less than 24MHz? > or I have to change my application. > > "Austin Lesea" <Austin.Lesea@xilinx.com> > ??????:3ED3C590.F0C93004@xilinx.com... > > Jon, > > > > The DCM CLKFX feature works down to a 1 MHz input frequency (as long as > > the output being synthesized is greater than 24 MHz). > > > > Note that you can not use "sync to DLL" (ie connect CLK0 to CLKFB) in > > this mode (DFS only mode). > > > > AustinArticle: 56080
On Tue, 27 May 2003 22:54:12 -0700, Ralph Mason wrote: > "Muthu" <muthu_nano@yahoo.co.in> wrote in message > news:28c66cd3.0305272041.4361c105@posting.google.com... >> Hi, >> >> With an N depth RAM, I could build a FIFO of depth N. Right? >> >> But this may not be true with asynchrnous FIFO. some where i heard >> that, for asynchrnous FIFO 1 location is wasted. why? and How? >> >> In general all the Circular FIFO documents also, saying that only N-1 >> depth is possible with N location RAM.? why? >> >> Thanks in advance >> >> Regards, >> Muthu > > You can never fill the FIFO to N because then the write pointer and the > read pointer would be equal and it would look like the fifo was empty. > > > Ralph If you really want to use that last location, make the read and write pointers 1 bit greater than needed to span the RAM addresses (log2(N) +1) and use the top bits of both pointers only for the fifo-full/empty compare... PCWArticle: 56081
It is possible to use the Nth word, but the fifo flag logic is far
simpler if you don't because the empty and full conditions look the same
if all the words are used.
Muthu wrote:
> Hi,
>
> With an N depth RAM, I could build a FIFO of depth N. Right?
>
> But this may not be true with asynchrnous FIFO. some where i heard
> that, for asynchrnous FIFO 1 location is wasted. why? and How?
>
> In general all the Circular FIFO documents also, saying that only N-1
> depth is possible with N location RAM.? why?
>
> Thanks in advance
>
> Regards,
> Muthu
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 56082ararghNOSPAM@NOT.AT.enteract.com wrote: > ... > > I haven't been near PCB design for 20 years. Things change. > Among the changes, nobody uses tape for any but the most trivial jobs. Artwork is made by computer. With multilayer boards, anything else would be decidedly awkward. Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 56083
Hi! I am working with an Altera Apex 20KE device. I have gotten some
hold violation errors. I am using a PLL for the clock so I though
clock skew was not going to be a problem. It turns out that in some
RAMs (lpm_ram_dp), it is a problem. I don't really know what to do.
Can somebody help me? Here is an example of the report from the
Quartus software: Thanks a lot!
Info: Minimum slack time is -1.984 ns for clock
PLL1:PLL1_inst|altclklock:altclklock_component|outclock0 between
source register hudsonbay2_core:inst_hudsonbay2_core|card_hw_if:inst_Card_HW_IF|msacom_m_txr:inst_msacom_m_txr|com_rxd_14_
and asynchronous destination memory
hudsonbay2_core:inst_hudsonbay2_core|card_hw_if:inst_Card_HW_IF|msacom_m_txr:inst_msacom_m_txr|rx_qpram_1:p1_rx_qpram_inst|lpm_ram_dpZ1:lpm_ram_dp_component|LPM_RAM_DP:U1|altdpram:sram|q[14]~mem_cell_din
Info: + Shortest register to memory delay is 3.867 ns
Info: 1: + IC(0.000 ns) + CELL(0.165 ns) = 0.165 ns; Loc. =
LC3_13_P3; REG Node =
'hudsonbay2_core:inst_hudsonbay2_core|card_hw_if:inst_Card_HW_IF|msacom_m_txr:inst_msacom_m_txr|com_rxd_14_'
Info: 2: + IC(1.033 ns) + CELL(2.669 ns) = 3.867 ns; Loc. =
EC6_1_P3; MEM Node =
'hudsonbay2_core:inst_hudsonbay2_core|card_hw_if:inst_Card_HW_IF|msacom_m_txr:inst_msacom_m_txr|rx_qpram_1:p1_rx_qpram_inst|lpm_ram_dpZ1:lpm_ram_dp_component|LPM_RAM_DP:U1|altdpram:sram|q[14]~mem_cell_din'
Info: Total cell delay = 2.834 ns
Info: Total interconnect delay = 1.033 ns
Info: - Smallest register to memory requirement is 5.851 ns
Info: + Hold relationship between source and destination is 0.000
ns
Info: + Latch edge is -4.365 ns
Info: Clock period of Destination clock
PLL1:PLL1_inst|altclklock:altclklock_component|outclock0 is 15.151 ns
with offset of -4.365 ns and duty cycle of 50
Info: Multicycle Setup factor for Destination register is 1
Info: Multicycle Hold factor for Destination register is 1
Info: - Launch edge is -4.365 ns
Info: Clock period of Source clock
PLL1:PLL1_inst|altclklock:altclklock_component|outclock0 is 15.151 ns
with offset of -4.365 ns and duty cycle of 50
Info: Multicycle Setup factor for Source register is 1
Info: Multicycle Hold factor for Source register is 1
Info: + Smallest clock skew is 6.064 ns
Info: + Longest clock path from clock
PLL1:PLL1_inst|altclklock:altclklock_component|outclock0 to
destination memory is 7.774 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. =
PLL_2; CLK Node = 'PLL1:PLL1_inst|altclklock:altclklock_component|outclock0'
Info: 2: + IC(1.710 ns) + CELL(0.507 ns) = 2.217 ns; Loc. =
LC9_16_P1; REG Node =
'hudsonbay2_core:inst_hudsonbay2_core|card_hw_if:inst_Card_HW_IF|msacom_m_txr:inst_msacom_m_txr|TXR_CTRL:txr_ctrl1|RX1_WEN'
Info: 3: + IC(3.608 ns) + CELL(1.949 ns) = 7.774 ns; Loc. =
EC6_1_P3; MEM Node =
'hudsonbay2_core:inst_hudsonbay2_core|card_hw_if:inst_Card_HW_IF|msacom_m_txr:inst_msacom_m_txr|rx_qpram_1:p1_rx_qpram_inst|lpm_ram_dpZ1:lpm_ram_dp_component|LPM_RAM_DP:U1|altdpram:sram|q[14]~mem_cell_din'
Info: Total cell delay = 2.456 ns
Info: Total interconnect delay = 5.318 ns
Info: - Shortest clock path from clock
PLL1:PLL1_inst|altclklock:altclklock_component|outclock0 to source
register is 1.710 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. =
PLL_2; CLK Node = 'PLL1:PLL1_inst|altclklock:altclklock_component|outclock0'
Info: 2: + IC(1.710 ns) + CELL(0.000 ns) = 1.710 ns; Loc. =
LC3_13_P3; REG Node =
'hudsonbay2_core:inst_hudsonbay2_core|card_hw_if:inst_Card_HW_IF|msacom_m_txr:inst_msacom_m_txr|com_rxd_14_'
Info: Total interconnect delay = 1.710 ns
Info: - Micro clock to output delay of source is 0.342 ns
Info: + Micro hold delay of destination is 0.129 ns
-- Paulo Valentim
Article: 56084
> But you don't have an 8x clock. If you could get 8 samples
> staggered by 1/8th of a clock each, then you could write a
> state machine that would process 8 samples at a time. It's
> probably easier to think about the 2 samples at a time first.
> If you are processing 8 samples/clock you have to worry about
> the case where the state machine puts out 2 bits on one clock.
>
> I'm not quite sure how to build that state machine, but it might
> be possible.
Well, it is acutally just a state machine that walks through eight
state transistions at once.
If you want to design it by hand, you draw your original state
machine.
Then you make a copy the states to a new machine and for each eight
bit pattern you walk your original machine for eight steps and insert
a transistion into the new machine to the state at the end of the
eight transition.
You can also let the VHDL synthesis tool do this for you.
The following code will walk eight steps through the original state
machine in each cycle.
for I in 0 to 7 loop
case state(i) is
when STATE1 =>
if input(i)='1' then
state(i+1) <= STATE2;
else
state(i+1) <= STATE3;
end if;
-- insert other states here
end case;
end loop;
process
begin
wait until rising_edge(clk)
state(0) <= state(8);
end process;
Kolja Sulimma
Article: 56085Robert wrote: > Does anyone knows when new Xilinx serial PROMs (e.g XCF02S) will be > available? I don't see them at distributors yet. > > announced for Q4 03 Laurent Gauch www.amontec.com ------------ And now a word from our sponsor ---------------------- For a quality mail server, try SurgeMail, easy to install, fast, efficient and reliable. Run a million users on a standard PC running NT or Unix without running out of power, use the best! ---- See http://netwinsite.com/sponsor/sponsor_surgemail.htm ----Article: 56086
Brett Foster wrote: > > Well this was actually meant for the serious posters silly. > > "Hans-Bernhard Broeker" <broeker@physik.rwth-aachen.de> wrote in message > news:bb29ag$q5u$1@nets3.rz.RWTH-Aachen.DE... > > In comp.arch.embedded Brett Foster <custserv@forums.ws> wrote: > > > I thought this was largely disproven. Or at least the effect rather > minimal > > > (negligible). > > > > Depends on what kind of "trace" you're talking about. ;-P > > > > If it happens to be a proper race track for electrons, a.k.a. > > high-energy particle accelerator, you'll have a rather "interesting" > > time trying to survive standing on the outside of any of its curved > > segments without heavy shielding in between. Kids: please _don't_ try > > this at home! > > -- > > Hans-Bernhard Broeker (broeker@physik.rwth-aachen.de) > > Even if all the snow were burnt, ashes would remain. Come, now! CBFalconer's remark was a joke in the first place. Injury? Smiley! Jerry -- Engineering is the art of making what you want from things you can get. ŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻŻArticle: 56087
Antti Lukats wrote: > ben@ben.com (Ben Jackson) wrote in message news:<ieSAa.1043647$S_4.1046948@rwcrnsc53>... > >>In article <80a3aea5.0305270412.307530aa@posting.google.com>, >>Antti Lukats <antti@case2000.com> wrote: >> >>>latest Xilinx iMpact doesnt seem to support the old style Parallel III >>>cable any more, >> >>I just built one and just upgraded to the latest WebPack SP (which includes >>an impact update) and used it to write XC9536/72. >> >>In what way is it "not supported"? > > > my fault I guess, I did not get it working with iMpact (cable not detected) > and after reading xil docs, did decide that cable III is not any more > supported (what seems not to be the case) - in xilinx docs they only > state that Parallel IV is supported, that was the misleading part for me > > antti > P.S. still have not figured out why I cant download with iMpact, all other > parallel port tools work Amontec released the parallel-cable III on Chameleon POD, it works very well for webpack 4.2 to the actual 5.2.02, no troubles with svf format too with 5.2.02 . Maybe try Chameleon POD at www.amontec.com/chameleon.shtml Laurent Gauch Amontec Team www.amontec.com PS: for Arm designers, the Chameleon POD can works like a Raven JTAG Emulator ... see today a real advantage of the programmable logic advantages, see www.amontec.comArticle: 56088
That's not quite true, there are simple ways to avoid this. All "my" FIFO designs use all available positions, but some of the available cores "waste" one position. I think this is mainly an "academic" issue,( in the bad sense of the word). A FIFO should be big enough so that it hardly ever gets full, and whether it has 1023 or 1024 locations should be irrelevant, in almost all cases. Peter Alfke, Xilinx Ralph Mason wrote: > > > You can never fill the FIFO to N because then the write pointer and the read > pointer would be equal and it would look like the fifo was empty. > > RalphArticle: 56089
In article <3ED3F57F.DA151F5F@yahoo.com>, cbfalconer@yahoo.com says... > Brett Foster wrote: > > "Mike Rosing" <rosing@neurophys.wisc.edu> wrote in message > > > > > > The short stubs are important, and the traces shouldn't have > > > any sharp angles - you want a really clean signal all around. > > > I assume you've got ground planes and not a 2 layer board? > > > That'll help a lot too. > > > > Why no sharp angles? > > Those electrons are moving at an appreciable fraction of the speed > of light, and tend to oversteer. The rear end breaks loose going > around those corners, and they are likely to go straight through > the wall and injure somthing. :-) Why do you think pads and vias are round. ;-) -- KeithArticle: 56090
"Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote in message news:IhXAa.32629$3t6.476804@news.xtra.co.nz... > "Muthu" <muthu_nano@yahoo.co.in> wrote in message > news:28c66cd3.0305272041.4361c105@posting.google.com... > > Hi, > > > > With an N depth RAM, I could build a FIFO of depth N. Right? > > > > But this may not be true with asynchrnous FIFO. some where i heard > > that, for asynchrnous FIFO 1 location is wasted. why? and How? > > > > In general all the Circular FIFO documents also, saying that only N-1 > > depth is possible with N location RAM.? why? > > > > Thanks in advance > > > > Regards, > > Muthu > > You can never fill the FIFO to N because then the write pointer and the read > pointer would be equal and it would look like the fifo was empty. Never say never unless you mean it. Anyway as many have pointed out, you can design anything any way you like. Why did I say never - well for one fifo space is it worth the extra complexity? Are there implementations that would use the same resources to use all the ram and the above? Are there just plain better implementations? RalphArticle: 56091
rickman <spamgoeshere4@yahoo.com> writes:
> I am finding JTAG to be a major hassle to try to use for both debug and
> production boundary scan. Seems there are conflicting requirements
> which the two camps are not generally interested in dealing with.
RISCTrace/Watch from IBM used to have the same issues. We had the
PowerPC in the middle of the chain.
If I remember correctly we (i.e. my colleague) solved this by:
1) connecting all TMS and TCK in parallel.
2) rotuing TDI/O from part A to connector X to part P and split to
connector X and part B (see fig).
3) When debugging, connector was used so that only part P was in the
chain. Pullups on TDI for other parts kept them out of trouble.
4) When tetsing for production, connector was used so that the entire
chain was used (strap in X to connect TDo of A with TDI on P).
5) The last part could also be achieved with resistor.
The issue with long stubs on TDI/O we didn't think mattered,
considering it's a synchronous system with a failry low system clock. TCK on the other hand was routed as a long clock winding to all parts and ending in a Thevenin termination.
All this from memory, if it doesn't work, blame someone else.
(fig 1)
|--------| |--------| |--------|
--| part A |--| |--| part P |-----| part B |---
|--------| | | |--------| | |--------|
| | |
| | |
|----------------------|
| connector X |
|----------------------|
Homann
--
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se
Article: 56092hmurray@suespammers.org (Hal Murray) wrote in message news:<vct8tbjgbnk31b@corp.supernews.com>... > It's also worth noting that LFSRs generate a "random" sequence of bits. > If you need random bytes/words, taking N bits out of the register every > clock will not give you very random data. (The n+1-st sample is just the > n-th shifted a bit with a random bit shifted in.) I think it works > OK if you can clock it N times between grabbing a sample. Not necessarily. The textbook example is to take (x,y) pairs generated by this method and graph them on a dot plot - you will instantly see patterns in the result. To quote a line from NR: "We guarantee that each number is random individually, but we don't guarantee that more than one of them is random." :-) A fix (sometimes dirty, sometimes not so dirty) is to permute the samples pseudorandomly. Tim.Article: 56093
I am certain it is not cable dependent. It would be interesting to know which device you are reading and which version of (the now obsolete) JTAGProgrammer you are using. Are you using the same JEDEC file for both JTAGProgrammer and iMPACT? Since the signature value is in the JEDEC file and the mechanism for reading the value is identical in both applications, answering these questions would be helpful.Article: 56094
I've now ordered the BurchEd board. It looks suitable for what I want. Im also downloading the WebPack at the moment. Im on a slow Modem so only another 9 hours to go and I should have it. Thanks for your help, "Spam Hater" <spam_hater_7@email.com> wrote in message news:na68dvktd19d2ktcusr91e3mu019vskma8@4ax.com... > On Tue, 27 May 2003 17:02:49 -0700, "Ed Stevens" > <ed@stevens8436.fslife.co.uk> wrote: > > > > >Do you know if the XILINX Student software places any restrictions on the > >VHDL for the Spartan 2 FPGA's? For example code size etc. > > > > IIRC, the limitation is that the 2 largest Virtex parts are missing. > > Why student edition? Why not down-load WebPack? It has similar > limitations (none that you care about), it's up-to-date, and you can > get a simulator to go with it. > > SH7 >Article: 56095
I am looking at revamping the FIFO cores, giving you many options: asynchr. vs synchronous, with exact empty and full extra one-clock-early empty and full indicators programmable almost empty and full indicators, readable occupied size , etc Any additional suggestions? Peter Alfke, Xilinx ================ Ralph Mason wrote: > > "Ralph Mason" <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote > in message news:IhXAa.32629$3t6.476804@news.xtra.co.nz... > > "Muthu" <muthu_nano@yahoo.co.in> wrote in message > > news:28c66cd3.0305272041.4361c105@posting.google.com... > > > Hi, > > > > > > With an N depth RAM, I could build a FIFO of depth N. Right? > > > > > > But this may not be true with asynchrnous FIFO. some where i heard > > > that, for asynchrnous FIFO 1 location is wasted. why? and How? > > > > > > In general all the Circular FIFO documents also, saying that only N-1 > > > depth is possible with N location RAM.? why? > > > > > > Thanks in advance > > > > > > Regards, > > > Muthu > > > > You can never fill the FIFO to N because then the write pointer and the > read > > pointer would be equal and it would look like the fifo was empty. > > Never say never unless you mean it. > > Anyway as many have pointed out, you can design anything any way you like. > > Why did I say never - well for one fifo space is it worth the extra > complexity? Are there implementations that would use the same resources to > use all the ram and the above? Are there just plain better implementations? > > RalphArticle: 56096
Hi all,
I have to find the best solution to do a TTL level converter.
I have to convert 5v <-> 3.3v 2.5v 1.8v 1.2v.
I have an external Vref signal for the second part.
I have some bidirectional signal :-(
The shem would be some think like this:
Ĥ-------------Ĥ
Ĥ +<----- Vref from 1.2v to 3.3v
Ĥ Ĥ
Ĥ TTL level Ĥ
5v TTL signals <--->+ converter +<----> 1.2v to 3.3v LVTTL signals
Ĥ-------------Ĥ depending on Vref
Which solutions to do that?
Is there any device to do that?
MANY thanks for your help.
Laurent Gauch
Amontec Team
www.amontec.com
Article: 56097I suggest using the outputs of several different-length LFSRs to generate a parallel word. Needless to say, the run length should all be relatively prime, which is actually hard to avoid. LFSRs are dirt-cheap especially using SRL16s in Virtex, and very fast. Peter Alfke, Xilinx ===================== Tim Shoppa wrote: > > hmurray@suespammers.org (Hal Murray) wrote in message news:<vct8tbjgbnk31b@corp.supernews.com>... > > It's also worth noting that LFSRs generate a "random" sequence of bits. > > If you need random bytes/words, taking N bits out of the register every > > clock will not give you very random data. (The n+1-st sample is just the > > n-th shifted a bit with a random bit shifted in.) I think it works > > OK if you can clock it N times between grabbing a sample. > > Not necessarily. The textbook example is to take (x,y) pairs generated > by this method and graph them on a dot plot - you will instantly see > patterns in the result. To quote a line from NR: "We guarantee that each > number is random individually, but we don't guarantee that more than one > of them is random." :-) > > A fix (sometimes dirty, sometimes not so dirty) is to permute the samples > pseudorandomly. > > Tim.Article: 56098
Keith R. Williams <krw@btv.ibm.com> writes: > Why do you think pads and vias are round. ;-) Because donuts are so tasty?Article: 56099
Amontec Team <laurent.gauch@delallcapsamontec.com> wrote: : Hi all, : I have to find the best solution to do a TTL level converter. : I have to convert 5v <-> 3.3v 2.5v 1.8v 1.2v. : I have an external Vref signal for the second part. : I have some bidirectional signal :-( : The shem would be some think like this: : Ĥ-------------Ĥ : Ĥ +<----- Vref from 1.2v to 3.3v : Ĥ Ĥ : Ĥ TTL level Ĥ : 5v TTL signals <--->+ converter +<----> 1.2v to 3.3v LVTTL signals : Ĥ-------------Ĥ depending on Vref : Which solutions to do that? : Is there any device to do that? A fast comparator with dual supply and push/pull output comes to mind. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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