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Hello again, you all ! The advice on my previous post (see below) was to upgrade to Modelsim version 5.7. So I did, but unfortunately, the program running on my winXP system, still collapses when I try to add signals to the wave window. And here I have no solution or workaround yet. It occured to me, that perhaps the system collapses if I'd try to add signals to the wavetable, if they haven't been forced a particular value at all. So I forces the signals a value and simulated the model for some time, and THEN added the signals to the wave table. Unfortunately, still no success. Is somebody able to help this student out here? Thanks in advance. Best regards, Dennis Maasbommel ----- Original Message ----- From: "Dennis Maasbommel" <aabbccdd00@hotmail.com> Newsgroups: comp.arch.fpga Sent: Thursday, May 08, 2003 3:01 AM Subject: Modelsim generating (Sigsegv BadPointer Access)-error on winXP > Hi Folks, > > Using FPGA Advantage V5.4 on my WinXP SP1 system, > I am having some problems with the integrated modelsim (v5.6d) > component. > > After a succesful compilation, I try to simulate the model, > But with many models I get this error > > ** Fatal: (SIGSEGV) Bad pointer access. > > > I searched using Google and it took me to the GNU C Library, > where this error was explained; From this point my guess is > that maybe Modelsim is not suitable for WinXP yet. > > I have tried all the compatibilty modes > (i.e. win95, win98/winME, winNT4 SP5, win2k) > but neither of these modes prevented modelsim from > generating this error. > > I have also tested a very simple model, which COULD be simulated, > but unfortunately Modelsim collapsed (program exits without further notice) > when I wanted to add signals to the wave-table. I guess maybe this has > someway the same cause as the 'Bad Pointer Access'-error. > > Beside this behavior, I have no other clue that my installation > version is corrupted > > Does any of you have experienced likewise problems with this tool, > and/or know how to solve these problems? I would be glad to hear it! > > Best Regards, > Dennis Maasbommel > >Article: 55751
I am searching for some technical references on the mac design in a typical 802.11 design. I have studied the hcf-light document s0005-11-light-rtf, but and looking for more along the same lines (without prostrating myself in front of either Intersil or Agere). Would anyone have any ideas where such documents can be found?? -- Charles Krinke http://home.pacbell.net/cfk cfk@pacbell.netArticle: 55752
Peter C. Wallace <pcw@freeby.mesanet.com> wrote in message news:pan.2003.05.15.23.24.22.967566.16848@freeby.mesanet.com... > On Thu, 15 May 2003 15:52:51 -0700, lc wrote: > > What would be the simplest and smallest CPU core for an FPGA ? I saw a > > lot of cores that mimic existing controllers but I would not mind to > > have something simpler. Low LE count is my goal. > > Anybody had similar objectives? Any ideas ? Would somebody point me in > > the right direction ? > > Thanks. > > Luis Cupido. > > P.S. - The application is logic intensive (a very large correlator) > > however the system output happens only once every second. Using logic > > for the output processing become tremendously big, a total waist of > > resources for something that happens only once every second. > > If its for a Xilinx FPGA take a look at the KCPSM/PicoBlaze. It's quite > small but still very usable, main limitation is 256 max instruction unless you > want to do program memory bank switching... > PCW Peter, the VirtexII version of the Picoblaze has a 1024 instuction limit. See the download page on my web-site (below) for a discussion on and example of converting it for use in a SpartanII, if 256 addresses isn't enough. Nial -- ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 55753
In article <YMNxa.11912$Ny5.354869@twister2.libero.it>, Selenium <uranium2003@libero.it> wrote: >On some telecom devices boards I have found some CPLDs EPM7032QI44-15, >unfortunately on the site of the Altera it is not it traces of it. If you type EPM7032 into Google the very first link is a pinout on the Altera website. >Are these CPLDs compatible JTAG? ...and one thing you notice on the pinout is TDI, TMS, TCK, TDO. There's a caveat in the footnote saying JTAG isn't always available. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 55754
On Sun, 18 May 2003 15:35:31 -0700, Nial Stewart wrote: > Peter C. Wallace <pcw@freeby.mesanet.com> wrote in message > news:pan.2003.05.15.23.24.22.967566.16848@freeby.mesanet.com... >> On Thu, 15 May 2003 15:52:51 -0700, lc wrote: >> > What would be the simplest and smallest CPU core for an FPGA ? I saw >> > a lot of cores that mimic existing controllers but I would not mind >> > to have something simpler. Low LE count is my goal. Anybody had >> > similar objectives? Any ideas ? Would somebody point me in the right >> > direction ? >> > Thanks. >> > Luis Cupido. >> > P.S. - The application is logic intensive (a very large correlator) >> > however the system output happens only once every second. Using logic >> > for the output processing become tremendously big, a total waist of >> > resources for something that happens only once every second. >> >> If its for a Xilinx FPGA take a look at the KCPSM/PicoBlaze. It's quite >> small but still very usable, main limitation is 256 max instruction >> unless > you >> want to do program memory bank switching... PCW > > Peter, the VirtexII version of the Picoblaze has a 1024 instuction > limit. > > See the download page on my web-site (below) for a discussion on and > example of converting it for use in a SpartanII, if 256 addresses isn't > enough. > > > Nial > -- > > ------------------------------------------------ Nial Stewart > Developments Ltd > FPGA and High Speed Digital Design > www.nialstewartdevelopments.co.uk Thanks, unfortunately we are usually cost and Block Ram bound, (at least until Spartan3 gets here), so the 18 bit instructions are a a bit (or 2bits) of a pain. We have already moved to using our own 1 clk/inst 16 bit CPU with 4K address range. At the time we decided to do our own processor, the PicoBlaze source was not available, and it was valuable to be able to tailor the instruction set to our needs (Motion control -- funny bound and saturate instructions). PCWArticle: 55755
For something I am working on now, I think an FPGA based uP/uC isn't a bad idea. I need a 32-bit RISC processor with 10/100 Ethernet + close coupled SDRAM access. Mating an FPGA based SDRAM controller with a flexible in-built uP would eliminate the need for an off-the shelf ARM or MIPS variant. Problem is multi-fold though. Right now you need to buy a development kit to get the "soft" processors and I don't know what long term pricing will be like (it's not on the websites) for the core itself. Since this is an experimental project (maybe it'll never go anywhere) it's not going to guarantee quantity one billion parts, so sales people at A or X will be less than cooperative. Along with getting familiar with yet another processor architecture and dealing with FPGA integration issues(and the compilers), spending min. $495 (or more) for the tools outweighs seems to out weigh the cost of a $10-15 microprocessor + $10-15 FPGA which you can drive with free tools. If you don't go the soft core route, you have the ability to dump the processor or FPGA if you aren't satisfied. If you go softcore, you're firmly tied to one vendor for it all. Plus there's the OS support issue too... S.R.Article: 55756
Thank for all your inputs. I solved the problem after sorting out the which reset to use on the second IFF. As you pointed out - there are quite a few rules to follow. The rule i missed out on was: Reset logic on both FFS are required if at least one of them needs it. Ufortunately, I need to run this at PCIX-133 MHz later so I will have a new problem later (thank for thw info Michael). I guess I need to tap the signals after the Xilinx core has sampled the PCI data in the IOB. Best regards, John "Michael Rhotert" <mrhotert@yahoo.com> wrote in message news:ba34jv$mub$02$1@news.t-online.com... > John, > FYI, the fast version of the Xilinx PCI-X core already uses both IFFs of the > PCIX-IOBs. > If you want to operate your circuit at PCI-X/133MHz later, you shouldn't use > the spare > input registers for other functions. > > Michael > > > "John Daae" <john.daae@datarespons.no> wrote: > > I am implementing a system using a PCI-X core from Xilinx and I want to to > > use the spare input registers (the second DDR input register) that the > core > > is not using. I have tried using IOB attribute on the actual signals in my > > VHDL code and I have tried IOB = TRUE constraint in the UCF file, but the > > PAR seems to ignore these guidings. > > > > Any suggestions? > > Is there a primitive for inputs register that I can instatiate? > > > >Article: 55757
I need to specify a workstation that will use for FPGA development (around 300K gates) i.e. simulate, synth, place and route flow (e.g. Foundation ISE + ModelSim XE). I plan to use RedHat Linux, as I was told it improves stability and 30% performance relative to Windows2000. I'm trying to set priorities to and find the tradeoffs between: Processor: Single or Dual (e.g. Pentium IV 2.4GHz) HDD type and speed: SCSI or ATA/EIDE (e.g. 18GB SCSI 10,000rpm or 15,000 rpm vs. 80GB ATA 7200rpm) RAM size: 512MB/1GB I will very much appreciate your feedback.Article: 55758
> Problem is multi-fold though. Right now you need to buy a development > kit to get the "soft" processors and I don't know what long term pricing > will be like (it's not on the websites) for the core itself. Since this The Xilinx MicroBlaze core netlist along with a bunch of peripherals is part of the EDK which costs $495....not sure what you mean by long term pricing for the core.... <invalid@invalid.com> wrote in message news:vK6cnYgDYLqyCFWjXTWcpg@speakeasy.net... > For something I am working on now, I think an FPGA based uP/uC isn't a > bad idea. I need a 32-bit RISC processor with 10/100 Ethernet + close > coupled SDRAM access. Mating an FPGA based SDRAM controller with a > flexible in-built uP would eliminate the need for an off-the shelf ARM > or MIPS variant. > > is an experimental project (maybe it'll never go anywhere) it's not > going to guarantee quantity one billion parts, so sales people at A or X > will be less than cooperative. > > Along with getting familiar with yet another processor architecture and > dealing with FPGA integration issues(and the compilers), spending min. > $495 (or more) for the tools outweighs seems to out weigh the cost of a > $10-15 microprocessor + $10-15 FPGA which you can drive with free tools. > > If you don't go the soft core route, you have the ability to dump the > processor or FPGA if you aren't satisfied. If you go softcore, you're > firmly tied to one vendor for it all. Plus there's the OS support issue > too... > > S.R. >Article: 55759
Current Xilinx ISE does not support native Linux....only Win2K or XP, though I read somewhere there are plans to support Native linux in the next major release. Current version can run on Linux/wine and there's a big thread in this NG on the topic, if you're interested. "Tsvika Hirst" <tsvika.hirst@minicom.com> wrote in message news:a688cfa9.0305190101.79cfedaa@posting.google.com... > I need to specify a workstation that will use for FPGA development > (around 300K gates) i.e. simulate, synth, place and route flow (e.g. > Foundation ISE + ModelSim XE). I plan to use RedHat Linux, as I was > told it improves stability and 30% performance relative to > Windows2000. > > I'm trying to set priorities to and find the tradeoffs between: > Processor: Single or Dual (e.g. Pentium IV 2.4GHz) > HDD type and speed: SCSI or ATA/EIDE (e.g. 18GB SCSI 10,000rpm or > 15,000 rpm vs. 80GB ATA 7200rpm) > RAM size: 512MB/1GB > > I will very much appreciate your feedback.Article: 55760
Whenever I run ngdbuild from a script (guile) I get the message below
Release 5.2.02i - ngdbuild F.30a
Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Command Line: ngdbuild -p v600ebg432-6 fpga-v600ebg432.edf
Launcher: Executing edif2ngd "fpga-v600ebg432.edf" "fpga-v600ebg432.ngo"
INFO:NgdBuild - Release 5.2.02i - edif2ngd F.30a
INFO:NgdBuild - Copyright (c) 1995-2002 Xilinx, Inc. All rights reserved.
Writing the design to "fpga-v600ebg432.ngo"...
Reading NGO file "/export/home/pegu/v600ebg432/fpga-v600ebg432.ngo" ...
ERROR:Parsers:47 - File Pr_Logical.dfa is not found!
ERROR:Parsers:47 - File Pr_Logical.llr is not found!
ERROR:Parsers - SSYacc0101e: Open file failed,
ERROR:Parsers:10 - Error occurred while creating Parse engine. Please check the
data directory to see that the .dfa and .llr files have been properly
installed and that the paths and permissions are properly set to access these
files.
It works fine when I run the ngdbuild command from bash or the script
under ISE 4.2iSP3. I'm using Solaris 9.
Are there any environment variables which controls where the parser
will locate the DFA and LLR files? Any other ideas how I can make
ngdbuild
Petter
--
________________________________________________________________________
Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter
Article: 55761"Neeraj Varma" <neeraj@cg-coreel.com> writes: > Current Xilinx ISE does not support native Linux....only Win2K or XP, though > I read somewhere there are plans to support Native linux in the next major > release. Does anybody know if Xilinx has any plans to support Opteron (64-bit mode) in the native Linux version? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 55762
You didn't specify for what type of projects you like to buy the new computer. Today FPGAs range from 500 to 5million gates :) ReHat Linux improves performance over Win2K by 30% in what?! While you don't have the native support for Linux in Foundation you can't even expect the same performance, now let alone any improvements... Aside the OS, my suggestions are: -Processor: Get a 'single' processor system, with the fastest CPU you can afford. Most EDA tools do not use multiprocessor very well. Even running on Pentium IV with Hyperthreading support, you should try to see if in reality turning of HT support would increase the performance or not. -HDD: Get a large harddisk if you need to run large designs/simulations. Also designs and their files and also the EDA tools themselves tend to grow so big as time passes. 15,000 rpm SCSI is certainly very fast but note that besides the access-time, rpm and cache it's important to know for what type of application the firmware of the drive has been optimized. Usually, the target for such SCSI drives are SQL database servers and web-servers so I don't think they will excel specially well for the "access pattern" of simulations and PAR. I suggest you to get a good big ATA drive like WesterDigital JB series (something like the 120GB drive that comes with a 8MB cache) that has been optimized for a broader range of access patterns. -RAM: Get as much as you can! Even with 3GB RAM, the simplest post-place and route simulation can run out of memory! But for the MINIMUM get 1GB and nothing less than that. -Personally when working with EDA tools I like to use a dual monitor config. It gives you a larger desktop and for example you can browse the source on one monitor while looking at the waveforms (yeah, I'm talking about ModelSim) on the other one both in full-screen. Yeah, it costs a bit more, but once you have used it for a while, you can't go back :) "Tsvika Hirst" <tsvika.hirst@minicom.com> wrote in message news:a688cfa9.0305190101.79cfedaa@posting.google.com... > I need to specify a workstation that will use for FPGA development > (around 300K gates) i.e. simulate, synth, place and route flow (e.g. > Foundation ISE + ModelSim XE). I plan to use RedHat Linux, as I was > told it improves stability and 30% performance relative to > Windows2000. > > I'm trying to set priorities to and find the tradeoffs between: > Processor: Single or Dual (e.g. Pentium IV 2.4GHz) > HDD type and speed: SCSI or ATA/EIDE (e.g. 18GB SCSI 10,000rpm or > 15,000 rpm vs. 80GB ATA 7200rpm) > RAM size: 512MB/1GB > > I will very much appreciate your feedback.Article: 55763
Hello there! We are working on a project to test memories under high temperature. Basically we are placing up to 9 memory chips in an oven, apply test patterns and read out the results. The idea is to use an FPGA to generate the patterns and employ it to send the output signals further to Labview for analysis. This means that the FPGA needs the following I/O's: - 144 = 9 memories x 16 bit bidirectional data signals - approx. 10 address and control signals - possibly 16 output signals to connect to the Labview DAQ-board, The system should run at a frequency of at least 10 MHz. Do you think this is a feasible and reasonable application for an FPGA? Is it a problem for the FPGA to drive 9 memories in parallel? If it's feasible to use an FPGA, which products would be most suitable? Many thanks in advance for your help. Kindest Regards, HenningArticle: 55764
Tsvika Hirst wrote: > > I need to specify a workstation that will use for FPGA development > (around 300K gates) i.e. simulate, synth, place and route flow (e.g. > Foundation ISE + ModelSim XE). I plan to use RedHat Linux, as I was > told it improves stability and 30% performance relative to > Windows2000. > > I'm trying to set priorities to and find the tradeoffs between: > Processor: Single or Dual (e.g. Pentium IV 2.4GHz) > HDD type and speed: SCSI or ATA/EIDE (e.g. 18GB SCSI 10,000rpm or > 15,000 rpm vs. 80GB ATA 7200rpm) > RAM size: 512MB/1GB > > I will very much appreciate your feedback. I'm not sure what you are looking for in the way of advice. Clearly the fastest processor is the best to reduce your run times. I'm not sure why you list a P4 2.4GHz. The 3.06 GHz chip will run faster if you don't mind paying a lot more for a little more performance. I don't think the software can use a dual processor. But the dual will allow you to do other things with the machine without slowing the FPGA work. The HDD is the same, SCSI will be faster if you don't mind paying the extra $200 or more. But if your designs don't swap memory, it won't matter much. If your designs do swap memory there won't be a fast enough HDD on the planet. You should put as much RAM in the machine as you can find. 1 GB is not a lot of RAM anymore. I would consider that a minimum, not a goal. In my opinion there are two ways to go. You can spend a lot on the machine today and get a screamer that will do the work about 50% faster (or less) than a more reasonably priced machine. Or you can pay less than $1000 today and get most of the performance of the top end machine, and then spend the other $1000 in six to twleve months and have a second, *faster* machine that you would have bought today for the full $2000. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55765
Martin,
We have encrypted spice models available on the web ("spice lounge").
One reason we encrypt them, is because they contain foundry model
information, which proprietary to our two fab partners (IBM and UMC).
Thus only Hspice is supported.
Austin
Martin Schoeberl wrote:
>
> Greg,
>
> thanks for your explanation and the link. I was only looking for literature
> of the devices I'm actually using. But there is a lot more info on a little
> bit older devices than Cyclone. I expect the output buffer of the Cyclone
> are simmilar with the of Stratix.
>
> About simulation: I would like to simulate my load, but I've only SPICE and
> no tool for ISIS modles. But I think there are no SPICE models available
> (for both A and X), right?
>
> Martin
> --
> --------------------------------------------------------
> JOP - a Java Processor core for FPGAs now
> on Cyclone: http://www.jopdesign.com/cyclone/
>
> "Greg Steinke" <gregs@altera.com> schrieb im Newsbeitrag
> news:5c1de958.0305161617.221ec4ec@posting.google.com...
> > Martin,
> > As my colleague has pointed out, the change in the slew rate is very
> > much dependent on your load and so should be simulated with IBIS or
> > SPICE. We (and other FPGA companies) do publish tables of IO adders
> > for various IO standards, slew rates, and drive strengths. These are
> > used to determine the tCO of the device for different cases, although
> > assuming a standard load such as 10 pF for LVTTL. While this can give
> > you an idea of the tCO difference between fast and slow slew rate,
> > analog simulation is necessary for full understanding. There is a
> > difference between edge rate and tCO variation (for example a 2 ns
> > delay does not mean that the edge rate is 2 ns longer) but this can
> > help you determine if the tCO of the device with slow slew rate on
> > will meet your requirements.
> >
> > For example, page 4-57 of the Stratix Handbook shows the IO adders for
> > various IO standards when fast slew rate is used, while 4-59 shows the
> > IO adders when slow slew rate is used. The Stratix handbook is
> > available here:
> > http://www.altera.com/literature/lit-stx.html?xy=dev_sdh
> >
> > Also please note that Quartus II software will show different input
> > and output buffer delays depending on what IO standard is used, but
> > again assuming the standard load for that IO standard.
> >
> > Sincerely,
> > Greg Steinke
> > gregs@altera.com
> >
> >
> > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
> news:<c2Kta.61402$e8.646243@news.chello.at>...
> > > Greg,
> > > thanks for the information. It would be nice if the change of the slew
> rate
> > > could be stated in the datasheet. You don't always want to run a
> simulation
> > > (with tools you don't have access to) to get a simple information like:
> > > When I turn the slow sr on, do I meet my timing e.g. for an async. ram?
> > >
> > > Sorry for my ignorance about the IBIS models on the web.
> > >
> > > Martin
Article: 55766> Current Xilinx ISE does not support native Linux....only Win2K or XP, though > I read somewhere there are plans to support Native linux in the next major > release. > > Current version can run on Linux/wine and there's a big thread in this NG on > the topic, if you're interested. > I assume you mean the thread Peter started "Alliance for Linux" on Jan 8th, 2001. In http://www.polybus.com/xilinx_on_linux.html it says that "04/25/2003: Xilinx officially began supporting Xilinx tools under Wine as of the 4.1 release, native Linux support is promised for the fall of 2003 (the 6.1 release)." Please comment on the hardware (single/dual, SCSI/IDE, RAM) priorities & tradeoffsArticle: 55767
Henning, this is what Americans call a "piece of cake". Pick any Virtex or even Spartan chip with the appropriate pin-out, and use it to build your tester. Linear-Feedback Shift registers (LFSRs) can generate pseudo-random address sequences very efficiently. Are you putting the FPGA also into the oven? Then you may consider Industrial grade devices. Greetings Peter Alfke, Xilinx Applications. Henning Bahr wrote: > > Hello there! > > We are working on a project to test memories under high temperature. > Basically we are placing up to 9 memory chips in an oven, apply test > patterns and read out the results. The idea is to use an FPGA to > generate the patterns and employ it to send the output signals further > to Labview for analysis. This means that the FPGA needs the following > I/O's: > > - 144 = 9 memories x 16 bit bidirectional data signals > - approx. 10 address and control signals > - possibly 16 output signals to connect to the Labview DAQ-board, > > The system should run at a frequency of at least 10 MHz. > Do you think this is a feasible and reasonable application for an > FPGA? > Is it a problem for the FPGA to drive 9 memories in parallel? If it's > feasible to use an FPGA, which products would be most suitable? > Many thanks in advance for your help. > Kindest Regards, > HenningArticle: 55768
Is $500 really too much money? It's less than one man-day of your cost to your employer, and when you figure "lost opportunity cost", spending $500 to save an hour or two may look like a good investment. Have you looked at what a plumber or a dentist charges per hour, let alone a lawyer or a psychiatrist? You may need one after you knitted your own cpu Just kidding.... Peter Alfke, Xilinx Applications =========================== invalid@invalid.com wrote: > > For something I am working on now, I think an FPGA based uP/uC isn't a > bad idea. I need a 32-bit RISC processor with 10/100 Ethernet + close > coupled SDRAM access. Mating an FPGA based SDRAM controller with a > flexible in-built uP would eliminate the need for an off-the shelf ARM > or MIPS variant. > > Problem is multi-fold though. Right now you need to buy a development > kit to get the "soft" processors and I don't know what long term pricing > will be like (it's not on the websites) for the core itself. Since this > is an experimental project (maybe it'll never go anywhere) it's not > going to guarantee quantity one billion parts, so sales people at A or X > will be less than cooperative. > > Along with getting familiar with yet another processor architecture and > dealing with FPGA integration issues(and the compilers), spending min. > $495 (or more) for the tools outweighs seems to out weigh the cost of a > $10-15 microprocessor + $10-15 FPGA which you can drive with free tools. > > If you don't go the soft core route, you have the ability to dump the > processor or FPGA if you aren't satisfied. If you go softcore, you're > firmly tied to one vendor for it all. Plus there's the OS support issue > too... > > S.R.Article: 55769
Tsvika Hirst wrote: > I need to specify a workstation that will use for FPGA development > (around 300K gates) i.e. simulate, synth, place and route flow (e.g. > Foundation ISE + ModelSim XE). I plan to use RedHat Linux... As far as I know, there is not a Modelsim XE for Linux, and I am not aware of anyone running it under Wine. Modelsim SE is available for Linux, but that is the $20K (last time I looked) version. -- My real email is akamail.com@dclark (or something like that).Article: 55770
> > on my actual board the trace length from the FPGA to the SRAM are under 10 > > mm (the RAMs are on the back side of the board under the FPGA pins). With > so > > short traces I think I've only the capacitive load. > > If it is properly terminated, it looks the same at any length. If the > transmission line impedance is lower than the source/sink impedance then it > will look like a capacitive load. I think I don't want to terminate 5-10 mm traces. That makes no sense for me. We can talk about series resistors to reduce the initial current. But this takes to many components and is better achieved by using the proper driving strength in the FPGA. > > > But it really depends on the slew rate. If you can slow it down to e.g. 2 > ns > > you can still treat it as a lumped system for traces up to 5 cm. > > If it is less than 5cm, 50 ohm impedance and 50 ohm source and load > impedance, you wouldn't notice the capacitance with a 2ns edge, compared to > the current driving the 50 ohm resisitor. When the capacitance does not count comparde to the 50 ohm than the length does not count ether. Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/Article: 55771
In article <3ec8cbb2$1@epflnews.epfl.ch>, Arash Salarian <arash dot salarian at epfl dot ch> wrote: >Aside the OS, my suggestions are: >-Processor: Get a 'single' processor system, with the fastest CPU you can >afford. Most EDA tools do not use multiprocessor very well. Even running on >Pentium IV with Hyperthreading support, you should try to see if in reality >turning of HT support would increase the performance or not. Dual processor has a big advantage: you can get other work done on the same system without (mostly) bogging down your CAD flow. It's a tough call. The other option is a KVM switch and a "dinky system" so you can do web browsing or something while waiting for the tools to run. >-HDD: Get a large harddisk if you need to run large designs/simulations. >Also designs and their files and also the EDA tools themselves tend to grow >so big as time passes. 15,000 rpm SCSI is certainly very fast but note that >besides the access-time, rpm and cache it's important to know for what type >of application the firmware of the drive has been optimized. Usually, the >target for such SCSI drives are SQL database servers and web-servers so I >don't think they will excel specially well for the "access pattern" of >simulations and PAR. I suggest you to get a good big ATA drive like >WesterDigital JB series (something like the 120GB drive that comes with a >8MB cache) that has been optimized for a broader range of access patterns. The big thing is RPM and access speed (seek time). Cache is less important as a Windows box or *nix box will use a lot of the RAM as cache (I think Windows may even be "all otherwise unused memory" or something like that). RAID will help on throughput, but NOT latency, and it is latency that is the killer when things start swapping. Likewise, SCSI's out of order request model helps throughput but not latency. MAKE SURE you have a backup system. >-Personally when working with EDA tools I like to use a dual monitor config. >It gives you a larger desktop and for example you can browse the source on >one monitor while looking at the waveforms (yeah, I'm talking about >ModelSim) on the other one both in full-screen. Yeah, it costs a bit more, >but once you have used it for a while, you can't go back :) A useful trick for dual-headed setups is have a high quality monitor in the front, and a "Big and cheap" on the side, as that's where you put the stuff you refer back to. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 55772
Has anyone used the CeSys USB2FPGA (USB2.0 Spartan II) board?Article: 55774
Hi,all I designed an fir filter and simulated in quartusII. but I found that the function simulation result differ from the timing result.Would someone give me some possible reasons. thank you very much. Regards! -- Best Regards
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