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Christian <cw@nikocity.de> wrote: > Hi There, > I am currently working on a FPGA based System using a serial arbitration > strategy. > I want to implement a dominant "low", and a recessive "high", > and for that I need to know if APEX 20k have the possibility to use pullups > on certain signals. The APEX have no internal pullups, you must use external pullups. Only Stratix and Cyclons have programmable pullup/downs Roman > hope you can help me > best regards > Chris.Article: 54101
Petter Gustad wrote: > I'm currently using QuartusII (2.2sp1) under Linux. I prefer not to > use the GUI except for floorplanning. Hence I prefer the quartus_cmd > tool. > > Is there a smart way to wait for the completion of the "cmp start" > command without doing an idle loop? Since I'm not running the GUI I > don't need to do any refresh. > Consider trying nonblocking tcl commands like vwait or fileevent. http://groups.google.com/groups?q=tcl+vwait+fileevent+example -- Mike TreselerArticle: 54102
> OK, but beware that if you use decoded WE directly to clock > data into some registers, the FPGA tools will probably try to > put it on to a dedicated clock net ... That's a good point. Is there a way to tell the tools (ISE Foundation 5.1) to not use clock nets for a particular signal? I'll research the UCF file immediately on this. > Any special reason for choosing the async write? I know it's > conceptually easier, but I've always found it was less pain > in the long run to stay synchronous where possible (and you > clearly *can* stay synchronous in this case). Well. Yes, but, in retrospect, none firm enough not to consider a synchronous solution. I just wanted to mimic the way a typical microprocessor interfaceable chip works (something like an 8255 PIO or 2691 UART). Most of these appear to have a non-synchronous interface to the uP and probably synch internaly upon utilization of the register data. That's a bird's-eye observation, of course. I have no way of knowing if that's endeed the case. I'm new to FPGA's so I don't quite have that second sense as to what will get me into trouble yet. Should I switch this interface to be synchronous on the uP side? Thanks, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 54103
Hello, I am using Virtex-II, Xilinx ISE 5.2 SP1. I would like to use the bufgmux to select between one of two possible clocks. One clock comes in through an IBUFGDS_LVDS_33 block (LVDS clock). The second clock is generated by an on board DCM driven from an external crystal. The bufgmux is configured like this: BUFGMUX xxx ( .O(clk_out), // output clock .I0(ext_lvds_clk), // external lvds clock .I1(int_dcm_clk), // internally generated clock .S(select) // select line ); If ext_lvds_clk and int_dcm_clk are present and stable, then I can configure the bufgmux to select and output either input clock. However, if ext_lvds_clk is not present (pins are floating), then the bufgmux does not select the correct output. I get nothing out at all. More accurately, I think it stays stuck in a state where I0 is output. Is there some unwritten (or obscurely written) requirement for both clocks to be present in order for the bufgmux to function correctly? Thanks, DougArticle: 54104
> Many (most?) designers do this with their favorite tool like Perl, > Python, Ruby, Guile, Dylan, etc. Personally I prefer Common Lisp. Of these the only tool I know is LISP ... to be more precise AutoLISP which is the original programming language included with AutoCAD. I've used it extensively to customize AutoCAD. I could see using it to simplify HDL coding. There are some things that I've done with Excel that would proabably not fit well into the above --just thinking out loud. For example, in trying to simplify the maintainability of a very large state machine that runs a menu on an LCD screen (not FPGA; 8051) I created a solution that allows me to type in the menu tree and out the other end comes the lookup table with states, state transitions and function calls encoded. The indentation level (via columns in the sheet) creates the menu tree relationship. This could be done, of course, with an ASCII based tool or even graphically with VB or C++ and a TreeView type object. I just happen to have used Excel. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 54105
Martin Euredjian wrote: > > I'm new to FPGA's so I don't quite have that second sense as to what will > get me into trouble yet. This is number one on my top ten list. > Should I switch this interface to be synchronous > on the uP side? I would consider it well worth the effort. -- Mike TreselerArticle: 54106
Douglas, Both clocks must be transistioning in order for the mux to operate. This is because the mux will always switch without creating a glitch, or runt pulse (it is not a simple mux). Austin douglas fast wrote: > Hello, > > I am using Virtex-II, Xilinx ISE 5.2 SP1. > > I would like to use the bufgmux to select between one of two possible > clocks. One clock comes in through an IBUFGDS_LVDS_33 block (LVDS > clock). The second clock is generated by an on board DCM driven from > an external crystal. The bufgmux is configured like this: > > BUFGMUX xxx ( > .O(clk_out), // output clock > .I0(ext_lvds_clk), // external lvds clock > .I1(int_dcm_clk), // internally generated clock > .S(select) // select line > ); > > If ext_lvds_clk and int_dcm_clk are present and stable, then I can > configure the bufgmux to select and output either input clock. > However, if ext_lvds_clk is not present (pins are floating), then the > bufgmux does not select the correct output. I get nothing out at all. > More accurately, I think it stays stuck in a state where I0 is > output. > > Is there some unwritten (or obscurely written) requirement for both > clocks to be present in order for the bufgmux to function correctly? > > Thanks, > > DougArticle: 54107
> Any special reason for choosing the async write? I know it's > conceptually easier, but I've always found it was less pain > in the long run to stay synchronous where possible (and you > clearly *can* stay synchronous in this case). I'd agree with Jonathan here. Re-time we in several times and use we_delay2 and we_delay3 to detect edges. You can put the first register in an IOB to ease timing, everything runs off the global clock and the tools have an easier time of it (it's also easier to analyse that the P+R results are right). You might need to re-time your data to take into account the delayed write pulse, but it's a price worth paying :-) Nial. ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 54108
Mike Treseler <tres@fluke.com> writes: > Petter Gustad wrote: > > I'm currently using QuartusII (2.2sp1) under Linux. I prefer not to > > use the GUI except for floorplanning. Hence I prefer the quartus_cmd > > tool. > > Is there a smart way to wait for the completion of the "cmp start" > > command without doing an idle loop? Since I'm not running the GUI I > > don't need to do any refresh. > > > > Consider trying nonblocking tcl commands like vwait or fileevent. Is there a variable set by cmp start which I can vwait on? Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54109
On Wed, 02 Apr 2003 08:26:32 -0800, Garrett Mace wrote: >> > > + There is a way to configure your FPGA with PCI9080/54/54 signals >> > > witout PROM and additional PLDs. Think a little and you would find >> > > it yourself. I'm not going to tell you how :) >> > >> > ummm, use an ISP CPLD? >> > >> > >> Nah. No CPLD. Just PCI9056, FPGA and one pullup resistor... >> >> > Seriously, tho', I guess you would use the FPGA's parallel config >> > mode. >> > >> > >> No, I don't. Everything works with Passive Serial (speaking in >> A-terms). > > Well, there is a user output pin...though perhaps DEVSEL could be > pressed into service. Actually there's any number of outputs that could > conceivably be wiggled. Its possible to use slave parallel mode as well with no extra hardware (at least with the PLX9030) I think the trick there was to use the local bus write signal as CONFIG CS.. PCWArticle: 54110
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:b6e883$tsq$1@news.tu-darmstadt.de... > Ralph Mason <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote: > : ... > > : Thanks for your help, it turns out that the CPLD wouldn't run in low power > : mode, until I feed a WR line into a global clock pin. > > It should work anyhow, until very fast signals (> 20 MHz) were > involved. Did you give a sensible constraints file? The signals are about 8Mhz. I don't have a constraints file, I use the attribute pin_assign to assign signals to pins. As you can tell I am not so experienced, should I have a constraints file? > : There was a thread here a while back about feeding an input signal out a > : global clock pin and then using the global clock signal - thus letting any > : pin be a global clock. > > If you still have a GCLK pin unconnected, feed the signal to that output and > read it back as GCLK signal. XST is normally good at doing this > automatically. Read the log files. I did this, created a signal of a different name in vhdl and then created an output called nWR on the GCK pin. But that made nWR an output, so I couldn't read it as an input. Thus couldn't compile. Is there another way? Thanks for you help RalphArticle: 54111
C-mode can offer slightly higher performance than J-mode. For J-mode Direct Slave and DMA transfers, there is a turnaround cycle between back-to-back local bus transfers. For reads, the turnaround cycle provides time for the local bus slave to tri-state its outputs and enable its inputs for the next address, after driving data for the previous read cycle. In C-mode there is no explicit turnaround cycle. Carter Buck Technical Applications Engineer PLX Technology, Inc. http://www.plxtech.com already5chosen@yahoo.com (Michael S) wrote in message news:<f881b862.0304011428.7c3c128e@posting.google.com>... > Bassman59a@yahoo.com (Andy Peters) wrote in message news:<9a2c3a75.0304010937.79425738@posting.google.com>... > > already5chosen@yahoo.com (Michael S) wrote in message news:<f881b862.0304010021.1e95769b@posting.google.com>... > > > > > We use J mode exclusively in all our newer designs. We feel really > > > sorry that we used C mode earlier. For the systems like ours which > > > have nothing, but FPGA, on the PLX local bus, C mode is pure wast of > > > pins with zero advantage. > > > > Now that I've thought about it, "J" mode is probably perfect if you > > are implementing an SDRAM controller in the FPGA. > > > > It boils down to: "do I need to have the local bus give me an address > > every cycle?" > > No. It doesn't boil down to anything. If FPGA[s] is/are the only > slave/sleeve sitting on the local bus, the J mode is superior to the C > mode. Period. During the C mode burst transaction the address bus is > incremented linearly, so it doesn't carry usefull information.Article: 54112
Ralph Mason <masonralph_at_yahoo_dot_com@thisisnotarealaddress.com> wrote: : "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message : news:b6e883$tsq$1@news.tu-darmstadt.de... : I did this, created a signal of a different name in vhdl and then created an : output called nWR on the GCK pin. But that made nWR an output, so I : couldn't read it as an input. Thus couldn't compile. VHDL should know about bidirectional pins. In Verilog "inout" is the keyword. It would work like inout clkpin; assign clkpin = (your clock expression); always @ (posedge clkpin) ... Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54113
Hi, Will someone that knows please help me out a bit. I am trying to use BlockRAM on a Spartan II, running ICE 5.1.02i - first time for me. Eventually I want to use dual-port memory but in desperation simplified things to the point where I only have single port memory in it's own VHDL module. The only ports that the module has, are Clk(in), address(in-12 bits) and data(out-8 bits) I am instantiating 8 blocks of RAMB4_S1, one block for each bit of the data bus. I read the Xilinx article "Using Block SelectRAM+ Memory in Spartan-II FPGAs" and found that it differs from the "help" in my iCE. In the component declaration of the 4K block, I have: generic ( INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; repeated up to INIT_0F Then in the instantiation, (8 times) I do the following generic map ( INIT_00 => X"000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F", INIT_01 => X"000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F", again repeated up to INIT_0F with real data. I map the ports like this: DI => "0", EN => '1', WE => '0', RST => '0', CLK => Clk, ADDR => VRAMA(11 downto 0), DO => VRAMD(7 downto 7)); -- different bit for each instantiation Whatever I do, I always get 0 back from the memory. Must be something very simple that I am doing wrong. Thanks Stephen du ToitArticle: 54114
Stephen du Toit wrote:
> Hi,
>
> Will someone that knows please help me out a bit.
>
> I am trying to use BlockRAM on a Spartan II, running ICE 5.1.02i -
> first time for me. Eventually I want to use dual-port memory but in
> desperation simplified things to the point where I only have single
> port memory in it's own VHDL module. The only ports that the module
> has, are Clk(in), address(in-12 bits) and data(out-8 bits) I am
> instantiating 8 blocks of RAMB4_S1, one block for each bit of the data
> bus. I read the Xilinx article "Using Block SelectRAM+ Memory in
> Spartan-II FPGAs" and found that it differs from the "help" in my iCE.
> In the component declaration of the 4K block, I have:
>
> generic (
> INIT_00 : bit_vector :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
> INIT_01 : bit_vector :=
> X"0000000000000000000000000000000000000000000000000000000000000000";
> repeated up to INIT_0F
>
>
> Then in the instantiation, (8 times) I do the following
> generic map (
> INIT_00 => X"000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F",
> INIT_01 => X"000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F",
> again repeated up to INIT_0F with real data.
>
These strings are used for simulation only. You also need these
attributes in the declarations area of the architecture:
-- These attributes are used for synthesis
attribute INIT_00 : string;
attribute INIT_01 : string;
attribute INIT_00 of rom_d: label is
"000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F";
attribute INIT_01 of rom_d: label is
"000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F";
Yes, it is annoying that you need the string twice in slightly different
forms.
--
My real email is akamail.com@dclark (or something like that).
Article: 54115
First question is whether either of the matrices is a constant, or if not if it is
relatively constant. If so then you can use distributed arithmetic, although if you
need to update the coefficient matrix, you'd be better off using Xilinx because of the
SRL16 capability. If both matrices are variable, you may still be able to use DA if
you have time to reprogram the LUTs (using SRL16 in Xilinx) between each set. For a DA
solution, you'd only need 36 * input bits/parallel sections clocks, so if you input
were 16 bits you could get by with 2 parallel sections and have 112 clocks available
for reloading the LUTs. If you can make the DA work, it may be the most compact
solution.
jerry1111 wrote:
> > You didn't say how fast it has to run.
>
> Sorry - I was so absorbed with this problem that I forgot to write it:
>
> 10us with 40MHz clock => 400 cycles would be perfect, but it's almost
> impossible - at least from my current point of view.
> I'll be happy getting any reasonable speed of course, but this timing gives
> an idea how should it be....
>
> I have to do 6 muls and cumulate them (6 adds) for each element from result matrix.
> Matrix is 6x6, so 36 elements gives 216 muls and 216 adds....
>
> Now I'm thinking about some sort of parralel operations, but it's not so
> simple because of storing data in ram. The best would be to store each row
> from A in separate block, columns from B in another 6 blocks, multiplying with
> 6 parallel logic pieces and feed results to FIFO. Each row/column is 6x36 bits -
> - maybe it would be better to make some pipelinig...
>
> Now I have 10 sheets of paper with various solutions, but I'd like to hear
> opinions from 'another point of view'....
>
> Selected device is EP1C6 from Altera.
>
> PS: Sorry for my bad english, but I'm more reading than writing.
>
> --
> jerry
>
> "The day Microsoft makes something that doesn't suck is probably
> the day they start making vacuum cleaners." - Ernst Jan Plugge
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54116Petter Gustad wrote: > Is there a variable set by cmp start which I can vwait on? It's not hard to make one. For an example, make an exception to your rule and bring up GUI: File, New, Other, Tcl Script, OK Edit, Insert Template, QuartusII tcl, Compile. -- Mike TreselerArticle: 54117
Ralph Mason wrote: > > I did this, created a signal of a different name in vhdl and then created an > output called nWR on the GCK pin. But that made nWR an output, so I > couldn't read it as an input. Thus couldn't compile. > > Is there another way? http://groups.google.com/groups?q=vhdl+qao -- Mike TreselerArticle: 54118
No need to reply. I found the answer while on an unrelated search through the archives. d@vcom.com (douglas fast) wrote in message news:<981fe2ba.0304021124.42160b3@posting.google.com>... > Hello, > > I am using Virtex-II, Xilinx ISE 5.2 SP1. > > I would like to use the bufgmux to select between one of two possible > clocks. One clock comes in through an IBUFGDS_LVDS_33 block (LVDS > clock). The second clock is generated by an on board DCM driven from > an external crystal. The bufgmux is configured like this: > > BUFGMUX xxx ( > .O(clk_out), // output clock > .I0(ext_lvds_clk), // external lvds clock > .I1(int_dcm_clk), // internally generated clock > .S(select) // select line > ); > > If ext_lvds_clk and int_dcm_clk are present and stable, then I can > configure the bufgmux to select and output either input clock. > However, if ext_lvds_clk is not present (pins are floating), then the > bufgmux does not select the correct output. I get nothing out at all. > More accurately, I think it stays stuck in a state where I0 is > output. > > Is there some unwritten (or obscurely written) requirement for both > clocks to be present in order for the bufgmux to function correctly? > > Thanks, > > DougArticle: 54119
I'm thinking about using a Linear Technology LTC3406B synchronous buck regulator for the 2.5V core Vdd for an XC2S150. Has anyone else used this? It's rated for 600 mA, so it should be able to handle the 500 mA required current at power-on (and my application will need less than that when operating), but I'm concerned about whether the ramp will be too fast, too slow, non-monotonic, or otherwise make the FPGA unhappy. It's not too expensive, and requires few external components. Since it operates at 1.6 MHz, it can use a very small inductor. Thanks, EricArticle: 54120
"Carter Buck" <cbuck@plxtech.com> wrote in message news:e57cc9c3.0304021321.88c08fe@posting.google.com... > C-mode can offer slightly higher performance than J-mode. For J-mode > Direct Slave and DMA transfers, there is a turnaround cycle between > back-to-back local bus transfers. For reads, the turnaround cycle > provides time for the local bus slave to tri-state its outputs and > enable its inputs for the next address, after driving data for the > previous read cycle. In C-mode there is no explicit turnaround cycle. > > Carter Buck > Technical Applications Engineer > PLX Technology, Inc. > http://www.plxtech.com But in burst mode, you get about a 50ns setup/address cycle, then succeeding data word transfers are approx. 30ns each. The turnaround time shouldn't present much of a problem, say, on 128-word bursts at a frequency of 26KHz. The FPGA can handle the addressing to write data blocks consecutively in memory, so the CPU response frequency does not have to be 26KHz. Then the CPU can process a set of data blocks (simple array lookup and increment) while the burst transfers occur in another section of memory. Carter: has PLX ever considered putting out a miniature, lower-pin-count version of the PLX series that only uses J mode? I'm having trouble convincing a potential client that this is a good alternative to SDRAM directly interfaced to the FPGA. Once you've gone through an SDRAM [address, read, increment, address, write] cycle, you are thinking 30ns is not all bad. Plus the desired access cycle was 300ns or less. Note that the major advantage of SDRAM -- burst writes again -- can't be used...the memory has to be an indexed array and increment. Meanwhile the embedded system would just sit there idly waiting around, just running an inactive program and leafing through the newspaper. And then...SDRAM chips do go out. In two years I know I will be able to find either a RAM module that fits in the embedded system, or a PC104 board that does and still uses the PCI bus. Can't say the same for low-megabit SDRAM chips. And to get the desired download speed, we'll have to use PCI anyway...requiring an FPGA with more pins and a FBGA package cuz there just aren't enough pins to run PCI and SDRAM at the same time...that is, unless they can be run on the same bus (shhh....). I do not endorse or approve of the banner my new ISP's news server places below! \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ \/ -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 54121
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:eWGia.2$ms3.12754046@newssvr14.news.prodigy.com... > > Many (most?) designers do this with their favorite tool like Perl, > > Python, Ruby, Guile, Dylan, etc. Personally I prefer Common Lisp. > > Of these the only tool I know is LISP ... to be more precise AutoLISP which > is the original programming language included with AutoCAD. I've used it > extensively to customize AutoCAD. I could see using it to simplify HDL > coding. > > There are some things that I've done with Excel that would proabably not fit > well into the above --just thinking out loud. For example, in trying to > simplify the maintainability of a very large state machine that runs a menu > on an LCD screen (not FPGA; 8051) I created a solution that allows me to > type in the menu tree and out the other end comes the lookup table with > states, state transitions and function calls encoded. The indentation level > (via columns in the sheet) creates the menu tree relationship. This could > be done, of course, with an ASCII based tool or even graphically with VB or > C++ and a TreeView type object. I just happen to have used Excel. Hey, you use the tools that you have and know. It's something most people have or can find a free equivalent for, and it does provide more of a two-dimensional perspective, rather than scripting which is more of a one-dimensional or branched perspective. It's only a matter of time before you write an AutoLISP application that lets you *generate code* by drawing various *lines and shapes* in some alien-looking structure. Like a circle becomes a loop, and objects intersecting the circle take on different functions, it would be like generating LOGO code from watching the turtle...I'd best not give you ideas that can waste considerable amounts of your time. -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 54122
Duane Clark <junkmail@junkmail.com> wrote in message news:<b6fohe027ie@enews4.newsguy.com>... > Stephen du Toit wrote: > > Hi, > > > > Will someone that knows please help me out a bit. > > > > I am trying to use BlockRAM on a Spartan II, running ICE 5.1.02i - > > first time for me. Eventually I want to use dual-port memory but in > > desperation simplified things to the point where I only have single > > port memory in it's own VHDL module. The only ports that the module > > has, are Clk(in), address(in-12 bits) and data(out-8 bits) I am > > instantiating 8 blocks of RAMB4_S1, one block for each bit of the data > > bus. I read the Xilinx article "Using Block SelectRAM+ Memory in > > Spartan-II FPGAs" and found that it differs from the "help" in my iCE. > > In the component declaration of the 4K block, I have: > > > > generic ( > > INIT_00 : bit_vector := > > X"0000000000000000000000000000000000000000000000000000000000000000"; > > INIT_01 : bit_vector := > > X"0000000000000000000000000000000000000000000000000000000000000000"; > > repeated up to INIT_0F > > > > > > Then in the instantiation, (8 times) I do the following > > generic map ( > > INIT_00 => X"000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F", > > INIT_01 => X"000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F", > > again repeated up to INIT_0F with real data. > > > > These strings are used for simulation only. You also need these > attributes in the declarations area of the architecture: > -- These attributes are used for synthesis > attribute INIT_00 : string; > attribute INIT_01 : string; > > attribute INIT_00 of rom_d: label is > "000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F"; > attribute INIT_01 of rom_d: label is > "000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F"; > > Yes, it is annoying that you need the string twice in slightly different > forms. Thanks very much for that. I am reading up about attribute declarations and specificationsArticle: 54123
Have a look at verilog-mode for emacs. I have it running both on my PC at home and on the 'nix machine in the office. Its capabilities overlap some of what you're doing but it has a long list of other capabilities. Do a search for "emacs verilog mode". -Stan "Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:rCwia.428$_e1.31582651@newssvr14.news.prodigy.com... > I find Excel incredibly valuable in various programming tasks, not just > FPGA's. On that topic though, I've been wondering if anyone has published > useful worksheets/utilities in order to facilitate the use of Excel in FPGA > programming. I'm working with Verilog, however, more generalized solutions > are of interest as well, hence the cross-post to comp.arch.fpga. > > I have, for example, created Excel worksheets to generate the Verilog code > to initialize large RAM blocks with data. The desired data is entered or > calculated on a column, a graph shows it to the right and the whole thing is > reformatted into Verilog code that can be cut and pasted right into a > module. > > Another example is a little VBA utility I wrote that lets me generate module > instantiation code (or other variants) by taking a sample instantiation, > say: > > widget U1 (.A(8'h23), .B(8'h99), .C(8'hAB)); > > replacing the parameters/instance name with "%n%": > > widget %1% (.A(%2%), .B(%3%), .C(%4%)); > > and then using rows and columns withing Excel to enter/calculate the > parameters for multiple instances of this module. As in the prior example, > the code can then be cut and pasted right into Excel. > > My thinking is along the lines of trying to limit repetitive error-prone > typing and automating as much as possible. Another candiate is the > repetitive signal, port type declaration style that requires typing the same > thing three times. In Excel this can be done once and then transfered into > your Verilog editor in one shot. > > > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > > >Article: 54124
"Garrett Mace" <g.ryan@macetech.com> writes: > It's only a matter of time before you write an AutoLISP application that > lets you *generate code* by drawing various *lines and shapes* in some or schematics in DXF format which could be imported into Xilinx ISE, Altera Quartus II or similar :-) Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petter
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