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Thanks for your suggestion, I'll try it when I've figured out how FPGA_Editor works. Caleb Hess <hess@cs.indiana.edu> schreef in berichtnieuws b6v6c4$m04$1@hood.uits.indiana.edu... > Try using FPGA_Editor to look at how the logic is actually implemented on > the chip. It would appear that your synthesis is not correctly producing > a single reset signal from "(CP_offline='1' or Reset='1')". > > In article <3e931135$0$24147$ba620e4c@reader0.news.skynet.be>, > P. Joeste <pekmenNOSPAM@skynet.be> wrote: > >Hi > >For a project in school i am using a Xilinx FPGA of the XC4000E family. > >The source code is almost ready but in many parts of the code I'm having > >problems when simulating.(I'm using the Project Manager's built-in simulator > >of Xilinx Foundation F3.1i) > >This is the piece of the code that doesn't work: > > > >process (STROBE,Reset,CP_offline) > >begin > > if (CP_offline='1' or Reset='1') then ControlPanel_Online <= '0'; > > elsif (STROBE'event and STROBE='0') then > > if (X='1') then > > ControlPanel_Online <= '1'; > > end if; > > end if; > >end process; > > > >I suppose it's obvious what this should do. The signal ControlPanel_Online > >is set to '1' when there's a negative edge on STROBE and X='1'; > >This works in the simulation. > >But when I try to set ControlPanel_Online back to '0' by making signal > >CP_Offline '1', nothing happens! Only when I use the GlobalReset, I can get > >ControlPanel_Online back to zero. > >It must have something to do with the GSR-network of the FPGA, since I can > >only use the GlobalReset and no other signal I intended to use as a reset > >(like CP_offline). > >Why is my CP_offline signal ignored? I'm not getting any warnings or errors > >after synthesis so I really don't have a clue. > > > >I hope my question is clear and that it is a common problem? > >Can someone help me out here? > > > >Thanks alot! > >Peter > > > > > > > > > > > > > -- > Caleb Hess hess@cs.indiana.edu >Article: 54377
Austin, I just can't resist... ;-) Alternatively, to balance out the offerings, you could also check out the following pages in the same vein: https://buy.altera.com/etraining/etraining.asp or, if you're a student: http://www.altera.com/education/univ/unv-index.html though I must say that I do like Bill Turnips suggestion at http://www.al-williams.com/pldhome.htm. If Just Some Guy is a designer working for a company that is currently seriously looking at taking the plunge into FPGA design on a structural basis, I would suggest that he he should invite a bunch of FPGA vendors (Actel, Altera, Lattice, Xilinx) for a cup of coffee to discuss his needs and wants. Just about all of them will be more than willing to get him started. Plus, of course, asking questions on comp.arch.fpga may enlighten him too. As my wife always says: "There are no stupid questions". Just my $.02Article: 54378
Ben, Thanks for balancing things out. Nothing wrong with that, as I am certainly not an expert browser of the competition's sites. Check out the offerings. By all means. Look at the quality and quantity of the information. See what you are comfortable with, and how you get along with the local disti/reps/fae's (if you are in business). Austin Ben Twijnstra wrote: > Austin, I just can't resist... ;-) > > Alternatively, to balance out the offerings, you could also check out the > following pages in the same vein: > > https://buy.altera.com/etraining/etraining.asp > > or, if you're a student: > > http://www.altera.com/education/univ/unv-index.html > > though I must say that I do like Bill Turnips suggestion at > http://www.al-williams.com/pldhome.htm. > > If Just Some Guy is a designer working for a company that is currently > seriously looking at taking the plunge into FPGA design on a structural > basis, I would suggest that he he should invite a bunch of FPGA vendors > (Actel, Altera, Lattice, Xilinx) for a cup of coffee to discuss his needs > and wants. Just about all of them will be more than willing to get him > started. > > Plus, of course, asking questions on comp.arch.fpga may enlighten him too. > As my wife always says: "There are no stupid questions". > > Just my $.02Article: 54379
On Wed, 9 Apr 2003 19:18:53 +0530, "LIJO" <lijo_eceNOSPAM@hotmail.com> wrote: >Hi, >Can anyone tellme What will be average difference in max frequencies we get >for pre layout(with gate level netlist) and post layout simulation for an >asic. > >thanks > > That depends on a lot of things: the accuracy of your wire load models, whether you made custom wlms, the size and aspect ratio of the block etc. You should expect somewhere between %10 to %30 decrease if you just used a synthesis with foundary supplied wlm to P&R flow. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 54380
On Wed, 9 Apr 2003 00:41:07 -0700, "George Fang" <gfang10@cox.net> wrote: >Thanks for everyone's response. Our options are somewhat limited by having >to use generic solutions since we are prototyping an ASIC chip. Even though >DCM is a very attractive solution but it's out of our reach. >What I'm always confused by is the I/O constraints. What does "OFFSET IN >BEFORE" (and the Synopsys equivalent "set_input_delay") do? Will tools react >to different setting of these constraints? I think so, but how well they do depends on the tools. My experience suggests that the "offset" constraints have little effect on the placement, and routing is subsequently constrained in what it can achieve by good or poor placement. >I did not observe any changes >when using different values for these constraints under Xilinx environment. If you have migrated the input FFs into the IOBs (as opposed to routing unclocked input signals into clocked CLB FFs) there is obviously nothing that placement or routing can do to affect the input timings, since the FF is in the input block with no routing between them! This will give you tightly defined timings and (IMO) is better than using on-chip routing to generate input delay. >Could someone point me to the >right direction for information in this regard? >I really appreciate everyone's help. While these options (IOB FFs, input delay(below)) ARE technology specific, there are probably similar options in the ASIC technology you plan to use. This is less likely with the DCM approach. Your ASIC vendor's IO cells are the next place I would look. If you cannot solve the problem in the IO blocks (in a similar way for FPGA and ASIC) I would agree that falling edge of clock is a viable alternative, with caveats about the duty cycle of the clock. - Brian >> ... I/O blocks have input delays selectable by user >> constraints. Something like this, for each input you want to delay, in >> the UCF file. >> >> NET "mynetname" IOBDELAY=IFD >> >> - Brian >Article: 54381
Hi, To install bus macros in my design, I use two kinds of power supply: Vcc e Gnd pins for each reconfigurable area group. (see XAPP290 example). So I use four IO pins and I set these as PULLUP or PULLDOWN. But I don“t want to use IO pins. I heard to talk about GND and VCC signals that are created with internal LUTs. How do I create and instanciate these signals inside LUTs? Do someone have a suggestion? I apreciate any kind of help. Regards Eduardo Wenzel Brićo Catholic University of Rio Grande do Sul state Porto Alegre city BrazilArticle: 54382
Through search sites, I found this application note: "XAPP404 - Xilinx Alliace3.1i - Modular Design" in http://www.xilinx.com/xapp/xapp404.pdf But I didn“t find any link inside Xilinx site about this document. Is this document update? There is a recent document (application note) about Modular Design? I can follow this document to implement any design in Modular Design flow? Eduardo Wenzel Brićo Catholic University of Rio Grande do Sul state - PUCRS Porto Alegre city BrazilArticle: 54383
Eric Smith wrote: > > I wrote: > > I'm thinking about using a Linear Technology LTC3406B synchronous buck > > regulator for the 2.5V core Vdd for an XC2S150. Has anyone else used > > this? It's rated for 600 mA, so it should be able to handle the 500 mA > > rickman <spamgoeshere4@yahoo.com> writes: > > I would recommend the TI TPS54315PWP. This is a 3 Amp, 2.5 volt > > switcher in a TSSOP20 package <7mm sq. The fixed voltage versions only > > require three small passives other than the main components. They have > > This looks promising. > > Are you soldering down the power pad on the bottom of the part? I can't > figure out how to do that without using reflow soldering, but my board > is probably going to be hand assembled. > > Thanks! > Eric I don't know what to tell you. I am fairly sure the pad on the bottom is just for thermal dissipation. But I do belive they talk about signal sensitivity of this pad, so it might not be a good idea to leave it unconnected. I do know that most assembly houses have hot air equipment that can solder this without using an oven. The same machine can take parts off or put them on. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54384
"John_H" <johnhandwork@mail.com> wrote in message news:T9Hka.9$716.2363@news-west.eli.net... > Has anyone figured out a nice, clean method to track which phase of a Xilinx > DLL's 1x clock corresponds to a 2x clock cycle? One 2x rising edge > corresponds to the 1x rising edge, the other 2x rising edge corresponds to > the 1x falling edge. > > When I start getting up in frequencies, the ability to use the 1x clock and > inverted 1x clock to generate two signals that I can XOR for a phase is > compromised. It's not inherently safe to use the 1x edges and 2x rising > edges as "effectively" the same edge due to clock skews and input jitter > issues. Using the falling edge of the 2x clock to sample the 1x generated > signals works, but at the 1/4 period timing budget is too tight at the > frequencies I'm working. > > For those who are Verilog friendly, the code here shows how I would > "normally" extract the phase without running a clock through a LUT. The > "negedge x2clk" is where the timing gets tough since the Tcko+Tnet+Tick is a > little over the 1/4 period of my x1clk. > > always @(posedge x1clk) posTog <= ~posTog; > always @(negedge x1clk) negTog <= posTog; > always @(negedge x2clk) rawPhase <= posTog ^ negTog; > always @(posedge x2clk) phase <= rawPhase; > > Is there a cleaner way to figure out the which half of the x1clk I'm in? > > Thanks, > - John_H > > It really only takes 2 flops working on rising edge. always @(posedge x1clk) Toggle <= ~Toggle; always @(posedge x2clk) Delayed <= Toggle; assign Phase = DelTog ^ Tog; EricArticle: 54385
"Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message news:vapn8v0cpn19jh8t7pa8ki84n13ar041m2@4ax.com... > On Thu, 03 Apr 2003 17:33:33 +1000, Allan Herriman > <allan_herriman.hates.spam@agilent.com> wrote: > > >Hi, > > > >Does anyone have experience with VHDL tool suppport for bit vectors > >(or vectors of other types) that have lots of elements? > > > >I'm thinking of using one for a generic or a constant (not a signal) > >to hold the initialisation value for a Xilinx block ram (18432 bits). > > > >I'm interested in both simulation and synthesis. > > Oops. I forgot to say that I have arrays of block rams, and the > vector will need to have up to several hundred thousand bits. > > Thanks, > Allan. I used block ram in a XILINX SpartanII device and if you look up the datasheet explaining using RAM in xilinx devices you will see examples of VHDL code how to use this ram and also how to initialise it. You can do that right after decleration of the component and there will be no need for this long vectors. I hope this will help you further, look up the datasheets at the xilinx site. Best regards from Holland, Melle JonkerArticle: 54386
Hi all I want to use a Quicklogic QL4090 in a project. Do you have any advice about Quicklogic family (QuickRAM) or QL4090 ? ThanxArticle: 54387
"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> wrote in message news:PnXka.281$KF1.80232@amstwist00... > If Just Some Guy is a designer working for a company that is currently > seriously looking at taking the plunge into FPGA design on a structural > basis, I would suggest that he he should invite a bunch of FPGA vendors > (Actel, Altera, Lattice, Xilinx) for a cup of coffee to discuss his needs > and wants. Just about all of them will be more than willing to get him > started. I'm a consultant working on a specific project for a customer. They've got requirements that're beyond the abilities of individually-packaged logic gates to implement, so FPGA is in my future. I'm going to use this as an opportunity to expand my skills on my customer's (partial) dime. Good advice on talking to several vendors. I had hoped to first learn enough about how FPGA is done to at least understand what they're telling me when we meet. > > Plus, of course, asking questions on comp.arch.fpga may enlighten him too. > As my wife always says: "There are no stupid questions". As my brother says "... just stupid people." I try to stay out of that category :-).Article: 54388
Hi all, I know this is an old topic, but now I facing it. I want to implement a double edge triggered flipflop in Virtex. There's another factor : the clock signal is bursting (sometime it totally flat, some time running), so I can't use the "clock double" trick. Any suggestion is apreciated,Article: 54389
I'm looking at cheaper alternatives to configuring my FPGA's. Currently, I use Atmel parts to configure my Xilinx FPGA's. I need ISP, and there isn't a processor on board for configuring the FPGA so don't suggest that. The 1Mb Atmel parts (ATLV010 or Cypress equivalents) are between $13-$20. Alternatives I know of are parallel EEPROM's with a CPLD for address generation, or a "serial data" flash part from Atmel that I think I could get to configure a Xilinx part with a simple state machine in a 16V8. The first alternative has the problem of space, and now there are two programmable parts on the board. The second, is smaller, but a little more complex (only in the fact that I haven't tried/verified it yet), and still has two programmable parts. Here is my real question. I see that Altera's EPCS1 (a 1Mb flash) is only around $3.50. It would save me some time if anyone has determined if it can easily be used to configure a Xilinx part. If so, what are the issues? Does anyone have any other solutions?Article: 54390
David Hawke wrote: > Hi all, > > I can in fact inform you that this will card will work with iMPACT. I use one > myself on a Dell Latitude C400. Excellent news - the laptop I've ordered is the Dell C400! :) Cute little things aren't they? > You will need to set the following env. > variable: > > XIL_IMPACT_ENV_LPT_BASE_ADDRESS=DFF8 > > or whatever your machine decides is the address of the PCMCIA card. OK cool, thanks. JohnArticle: 54391
Hi Chris, I agree, Altera has MUCH better options for 5V FPGA support than Brand-X. IIRC, there's a 1-time $840 fee to keep the Altera-specific version of Leonardo alive. For the record, Quartus-II doesn't support 5V parts. Max+II does, but it's not really at the same level as Quartus or ISE. $.02, SH On 8 Apr 2003 17:42:13 -0700, cbalough@altera.com (Chris Balough) wrote: >Hello, > >First, it's important to be clear that there are several high quality >synthesis options available for all Altera products. > >Altera is committed to ensuring our customers have a full range of >synthesis solutions for all of our devices, from our MAX CPLD devices >to our high performance Stratix and Stratix GX families and the >low-cost Cyclone family. Altera has strong partnerships with all of >the major 3rd party synthesis tool vendors, including Mentor, >Synopsys, and Synplicity. We also offer an integrated synthesis option >that is included with all of the Quartus II Design Software packages. >As a further service to our customers, Altera has worked with Mentor >and Synplicity to make available some very attractive promotional >offers for Altera synthesis solutions. > >For more information on the 3rd party synthesis tools available for >Altera devices, please see the following page on our website: >http://www.altera.com/products/software/pld/eda/partners/eda-index.html > >For more information on Altera's integrated synthesis tool, please >download the following application note: >http://www.altera.com/literature/an/an238.pdf > >Cheers, Chris > >Spam Hater <spam_hater_7@email.com> wrote in message news:<96319v4udn64fnkeqp04tr2q50srustpov@4ax.com>... >> Kevin, >> >> Because Xilinx did the same thing a year and a half ago. >> >> Basically, both used OEM'd synthesis tools for their 5V FPGAs. Altera >> used Leonardo, Xilinx used Foundation. >> >> Both have terminated their OEM agreements. >> >> Xilinx currently has -zero- synthesis tools for their 5V FPGAs. And >> no intention to get them. >> >> At last with Altera, you can still use Max+II. >> >> $.02, >> SH >> >> >> On Fri, 04 Apr 2003 23:10:17 -0600, Kevin Brace >> <kev0inbrac1eusen2et@ho3tmail.c4om> wrote: >> >> >Paul, >> > >> >I don't mean to start an A vs. X argument here, if you don't like what >> >Altera did to you, why not switch to Xilinx?Article: 54392
On Wed, 09 Apr 2003 20:16:12 GMT, "Melle Jonker" <--SPAMLESS--mk.jonker@chello.nl> wrote: > >"Allan Herriman" <allan_herriman.hates.spam@agilent.com> wrote in message >news:vapn8v0cpn19jh8t7pa8ki84n13ar041m2@4ax.com... >> On Thu, 03 Apr 2003 17:33:33 +1000, Allan Herriman >> <allan_herriman.hates.spam@agilent.com> wrote: >> >> >Hi, >> > >> >Does anyone have experience with VHDL tool suppport for bit vectors >> >(or vectors of other types) that have lots of elements? >> > >> >I'm thinking of using one for a generic or a constant (not a signal) >> >to hold the initialisation value for a Xilinx block ram (18432 bits). >> > >> >I'm interested in both simulation and synthesis. >> >> Oops. I forgot to say that I have arrays of block rams, and the >> vector will need to have up to several hundred thousand bits. >> >> Thanks, >> Allan. >I used block ram in a XILINX SpartanII device and if you look up the >datasheet explaining using RAM in xilinx devices you will see examples of >VHDL code how to use this ram and also how to initialise it. You can do that >right after decleration of the component and there will be no need for this >long vectors. I hope this will help you further, look up the datasheets at >the xilinx site. That doesn't answer my question at all, but thanks for trying. Allan.Article: 54393
> Here is my real question. I see that Altera's EPCS1 (a 1Mb flash) is > only around $3.50. It would save me some time if anyone has > determined if it can easily be used to configure a Xilinx part. If > so, what are the issues? > > Does anyone have any other solutions? Sandb, Here's an alternative solution :-) For future projects, try using Altera's Cyclone product. It's designed to work with the EPCS1 and EPCS4 products -- they are low-cost (as you point out) and low-footprint (8-pin package). About as easy as it goes for configuration. On top of this, Cyclone supports bitstream decompression, achieving 1.7 - 2.1x compression, depending on how full your design is. So you can store a compressed bitstream in your EPCS device, and the Cyclone part will decompress it. You can also use a single configuration device to program multiple Cyclone devices, with a combination of compressed and uncompressed bitstreams. One other neat thing is that you can access any unused NV memory on the EPCS device from your design. You can use this as storage for a Nios processor, or whatever else you want. Cyclone chips are pretty cheap, have good performance, and have been shipping for a few months now -- so if you are looking for low-cost total solution, Cyclone + EPCS1 is a pretty good way to go. That's my unbiased opinion ;-) Regards, Paul Leventis Altera Corp.Article: 54394
> > Plus, of course, asking questions on comp.arch.fpga may enlighten him too. > > As my wife always says: "There are no stupid questions". > > As my brother says "... just stupid people." I try to stay out of that > category :-). The vendors also have it in their best interests to get you up-to-speed on FPGA work. If you honestly admit you aren't well-versed in the field, they will understand and maybe give you a few tips and a presentation. It is better to approach a lack of knowledge this way; at least when you are on the buying side! Does not hurt to get enough information to determine whether they are stringing you along. But that's something you'll usually find in used car salesmen...I like to think vendors in our field maintain a good level of professionalism. Just don't pretend to know more than you do. There is another saying: "It is better to seem like a fool and remain silent, than to open your mouth and remove all doubt." -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 54395
Just hook your clock to the RAM's clock: lut512 lutPI ( .ADDR(addr), .CLK(clk_index), .DI(PI), .WE(we_PIPQ), .DO(PId)); The lines: > always@(posege clk_index) > begin > we_PIPQ=0; //set LUT to read > clk_PIPQ=0; > clk_PIPQ=1;//Rising clk, We get PId end up making clk_PIPQ=0 for zero time then immediately make it 1 again... and so it'll always be =1. Why are you using coregen, anyway? just look up in the primitives for the type of RAM closest to what you want. I find coregen to produce warnings during compilation, and there are so many warnings, it's too hard to sift through to find warnings that apply to my code. -S "Xateta" <spanishgirlinireland@yahoo.es> wrote in message news:b3b3c6$3et$1@peque.uv.es... > Hello, > Im programming an FPGA Virtex-E using Verilog HDL. > I have used a RAM from Coregen and I instantiate it after defining data > types: > > lut512 lutPI ( > .ADDR(addr), > .CLK(clk_PIPQ), > .DI(PI), > .WE(we_PIPQ), > .DO(PId)); > > The question is: > Can I generate a rising edge for a clk that feeds a RAM inside an always > loop? Like that: > > always@(posege clk_index) > begin > we_PIPQ=0; //set LUT to read > clk_PIPQ=0; > clk_PIPQ=1;//Rising clk, We get PId > > PI=PId*V; > we_PIPQ=1; //set LUT to write > clk_PIPQ=0; > clk_PIPQ=1;//After the rising edge, PI is written into the LUT > > end > > I have tried it and it works like the clock clk_PIPQ didnt move at all. > I understand that it only cares for the ultimate value of clk_PIPQ > inside the always loop. > If I cant do that, How can I generate a rising clock so that I get PId and > make operations with it? > > Thanks for your time, I appreciate your help. > Laura > > >Article: 54396
Hello Eduardo, that App-note is not current at all anymore, that's why it was taken off our site. But the relevant information was put into the documentation coming with the standard installation (the 'Development System Reference Guide'). Normally it should be on the web too but I don't have a direct link. Have a look around on www.support.xilinx.com Cheers, Martin Eduardo Wenzel Brićo wrote: > Through search sites, I found this application note: "XAPP404 - Xilinx > Alliace3.1i - Modular Design" in http://www.xilinx.com/xapp/xapp404.pdf > > But I didn“t find any link inside Xilinx site about this document. Is > this document update? There is a recent document (application note) > about Modular Design? > > I can follow this document to implement any design in Modular Design flow? > > Eduardo Wenzel Brićo > Catholic University of Rio Grande do Sul state - PUCRS > Porto Alegre city > Brazil >Article: 54397
woodyj@pptvision.com (Sandb) writes: > Alternatives I know of are parallel EEPROM's with a CPLD for address > generation, or a "serial data" flash part from Atmel that I think I You can use a plain AMD FLASH with a CPLD like you say. You could use your FPGA to write to the FLASH (easier if you have a Ethernet or PCI interface on the FPGA), or you could use JTAG to control the pins on the FLASH to perform the write operation. I've been playing with my Altera Stratix NIOS Developer Board and it's really neat to write the configuration to the AMD FLASH using tftp from my Linux machine :-) It only takes a second or so to upload the hexout file. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54398
Hi, khimbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote: > hello folks ... while tooling around the arrow site this evening > doing some price comparisons ... I noticed that altera has million > gate plus FPGA's that are priced in the $2000-4000 range , holly geeze 2k$ is a lot for doing mass articles like TV or DVD, but it is no problem for complex systems which will be delivered only a few times. In earlier days you would have produced an ASIC, if your system needs an FPGA >1k$, nowadays there are people thinking its cheaper to spend 2k$ for each selled product right after contract signing, then spending once 1M$ and hopping that you sell more then 500 pieces to reach break-even. Even if the market seems to be big enough to sell a lot more then 1000 pieces over the years. > !! , yes I know a "good price or volume price " is certainly lower ... > but does anyone outside of perhaps the military actually buy and build > product with FPGA's that cost a couple of grand ?? just curious ... Yes, actually there's more than just mil with need of high reliabel fpgas with prizes >>1k$ even for simple functionality *g*. bye ThomasArticle: 54399
Hi, I can at least answer on question for you that is that you can probably not use Alteras EPCS1 for configuring your FPGA. Simple reason for this is that this part is more of a "normal" memory and the configuration support is in the Cyclone FPGA (which is the only Altera FPGA you can use with the EPCS1). Your best way forward in my opinion is to go with the state machine approach in CPLD. You could also try to switch over to Altera cyclone family but then you will have some (a lot of?) work to do. There is an app note to help you tough. (AN-255 from Altera) and the tools for Cyclone family is free of charge (Quartus2Web) so you could have a try. This depending on what Xilinx part you are using of curse. (Wouldn’t try to convert a Virtex-2PRO). Cheers Fredrik woodyj@pptvision.com (Sandb) wrote in message news:<99b0d5ad.0304091327.3088fc3a@posting.google.com>... > I'm looking at cheaper alternatives to configuring my FPGA's. > Currently, I use Atmel parts to configure my Xilinx FPGA's. I need > ISP, and there isn't a processor on board for configuring the FPGA so > don't suggest that. The 1Mb Atmel parts (ATLV010 or Cypress > equivalents) are between $13-$20. > > Alternatives I know of are parallel EEPROM's with a CPLD for address > generation, or a "serial data" flash part from Atmel that I think I > could get to configure a Xilinx part with a simple state machine in a > 16V8. The first alternative has the problem of space, and now there > are two programmable parts on the board. The second, is smaller, but > a little more complex (only in the fact that I haven't tried/verified > it yet), and still has two programmable parts. > > Here is my real question. I see that Altera's EPCS1 (a 1Mb flash) is > only around $3.50. It would save me some time if anyone has > determined if it can easily be used to configure a Xilinx part. If > so, what are the issues? > > Does anyone have any other solutions?
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