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Michael Condon wrote: > Yes you did Plonk.... > "Jim Stewart" <jstewart@jkmicro.com> wrote in message > news:51E3B1BB6FF54211.1891BEB1EF60218C.834ADF2C29D567FF@lp.airnews.net... > >>Michael Condon wrote: >> >>>First of all don't post questions or comments on the board if your going >> > to > >>>be an A-hole about it. As far as your "Famous Last Words" goes that's >> > what > >>>your going to be if you don't get up to speed with the current design >>>techniques. >>> >>>Some people lead, some people follow, and some people go the way of the >>>Do-Do Bird. >>> >>>As far as your clients go; some might prefer schematic now, but that's >>>because they aren't hardware engineers. >>> >>>Yes C is still useful but what about Abel, Fortran, etc. As an engineer >> > you > >>>need to learn the newer techniques or you will be left behind. My post >> > was > >>>meant to be helpful and to point out where the new technology is going. >>> >>>Most if not all design tools now a days can read in VHDL or Verilog code >> > and > >>>convert it to schematic designs. Then you can take the HDL code and >> > give it > >>>to a hardware engineer who can make changes to the code quicker and >> > easier > >>>then if they were given a schematic design. >>> >>>I'm sorry that you want to continue to use schematic entry for your >> > design, > >>>but if you take the time to learn the current design techniques then the >>>power of HDL languages will become apparent to you. >>> >>>But if you just want to be mad and run around like a twelve year old kid >>>upset at the world then you can do that on your own time.....don't post >>>messages here! >> >>I guess I missed the vote that made you moderator of this grouArticle: 55251
On Thu, 1 May 2003 16:07:08 +0100, "Michael Attenborough" <michael_aht_brainboxes_doht_com@say.it> wrote: >I've got a testbench that takes a long time to run, and as it runs the >memory usage of ModelSim slowly ramps up. After about 5 million simulated >clock cycles, I'm out of memory. I don't see why more memory should be >needed as the simulation progresses, when there are no signals on the >waveform viewer. The memory is not released when I restart or reload the >simulation, but only when I close ModelSim. Is there some kind of bug in my >(VHDL) model which could cause this, or is it a memory leak in ModelSim? >Maintenance on ModelSim was allowed to expire a couple of years ago due to >cost-cutting, so any ideas would be appreciated. It is quite possible to have a memory leak in your VHDL, particularly if you are using 'write' to generate strings. http://groups.google.com/groups?as_q=memory%20leak&as_ugroup=comp.lang.vhdl I have observed memory leaks in modelsim itself as well, mostly in the GUI. Regards, Allan.Article: 55252
Jim Granville wrote: > > rickman wrote: > > > <snip> > > The absolute max of 150C is where they say no damage will occur. But > > they don't claim that the parts will operate within spec above the rated > > max of 85C. I *could* use the part above 85C and do my own test that it > > still works (output drive, switching time, etc...). But I don't want to > > have to invest in an oven for all my boards. They have an automotive > > grade that is tested to 125C which is the number I need to support in > > shutdown. I also want to do a shutdown for power consumption issues and > > prefer not to use two pass transistors. To control just one transistor > > for both functions I have to have logic added. It is either a few > > picogates or a PLD. Since I need a 32 or 64 macrocell PLD on the board > > anyway, it seems natural to use the same PLD. But just like with the > > MCUs, I am finding that automotive temperature parts just don't have the > > flexibility as even industrial parts. > > > <snip> > > > - do you believe there is a sudden, drastic failure > > > mode that occurs if the device hits 86'C when biased ? > > > - how is that failure mode avoided if the IO pins are instead run > > > at Abs max 4V ? > > > > This sounds a bit like sarcasm... cool! I don't like to operate a > > device outside the spec. If I am selling a board to someone who is > > using it as test equipment in a locomotive (the actual application which > > is driving the temperature spec) > > So do you have real numbers of Temperature/Time profiles > you need to meet ? > > > I am not going to run parts at 125C > > that are not spec'd to do their job above 85C. I don't really know you, > > but I recognize the name from here. Are you saying that you design > > parts outside their spec? > > No, it boils down to how you define 'run'. > > If you remove Vcc, but keep voltage on the I/O's is that > 'running the device' ? > Which will cause more stress - to push I/O -> Vcc, or to > keep Vcc present, with no thermal load ? > > Some vendors use the terms : > Temperature Under Bias 85'C > Storage Temperature 150'C > > If you want to be inside this spec, you must remove all bias @ 85'C What we have here is a failure to communicate. You are talking about "stresses" and I am talking about operating parameters. The spec sheet clearly says the die is good to 150C with no damange, "TJ Maximum junction temperature". This is a separate spec from "TSTR Storage temperature" which is an even wider number. They also say, "This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification is not implied." Most vendors refer to the Tj spec as "Max temperature under Bias". I am assuming this is the case here since it is distinguishted from the storage temp. Now do we agree that putting a voltage on an IO pin is ok to do at temps up to 150C? > If you compare the Automotive specs, and the Indust spec, they > have the SAME abs MAX Tj (which is what really matters to the chip) > Xilinx's Automotive spec is rather lax, in quoting a Ta > but with no thermal loads ( so how can they KNOW Tj ?!) > ( I think it's lattice who do a more correct spec). I'm not concerned since this is a "zero" power part and will be operated nearly staticly. > Speed and leakage are certainly relaxed with the higher Ta, but I see > no other indicators of sudden failure. (ISTR ISP issues in another > thread at extreme temperatures ?). I will agree, but much of adhearing to specs is a matter of CYA. If your product fails for what ever reason and the design is examined, violating a manufacturer's spec, even in an innocuous way, such as this one, can mean liability or at very least it can cost sales. > Testing will be more costly, and they also have to lower the > performance bar, which is why Automotive spec devices are relatively > rare. > > As I mentioned before, talk with Xilinx, find out what is different > about the Automotive specs, and what does not work. > eg Maybe ISP fails above 85'C - will that bother your app ? > > Atmel effectively admit it's all the same silicon, by giving > rules for how to de-rate Commercial -> industrial usage. > Why not ask Xilinx if they can do the same ? > > Ta for an IC, also means the surface of the (hottest) package, > not the air outside your case, so you will need to factor that > slope into the design - more than one temp sense may be needed. I thought that I had said I *was* talking to Xilinx? We all *know* it is the same silicon. The difference is in the spec and the test. And test is *all* the difference. Just like speed grades. People overclock their PCs all the time. But if you sell a PC running at a faster rate than it was made to run, you will get a bad name in a hurry. I think I have found a way around the MCU temperature vs. supply voltage limitations. If I use a separate RTC, I can run the MCU at 5 volt with the battery backup only on the RTC. This way I use all parts within spec and the battery circuit becomes very simple. The extra IOs on the MCU will take the place of the CPLD. I can't seem to find many RTC that work in the automotive temperature range, but as long as they don't blow up or short out, I can use it. We just won't have the time the board went into shutdown! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55253
Does anyone have experience with the MJL Stratix dev kit. It is the lowest cost Stratix EP1s25 kit I could find. Anyone know whether it can handle devices denser than the 1s25 (i.e. 1s40 or 1s80?). I have an imaging and 3d graphics pipeline project. Does anyone know whether the Virtex II are a better choice or the Stratix? Thanks. Atif Zafar Indiana UniversityArticle: 55254
Mikeandmax wrote: > > Rick Wrote - > > >I have been looking for a CPLD or even an SPLD that will take the full > >automotive temperature range. The parts I have found all have some > >limitation. The Coolrunner parts don't come in a small enough package > >and the Lattice part I found draws too much static current. > > Hi Rick - have you looked at the recent Lattice 4000Z family devices? They are > available industrial and automotive temp, and are in CABGA (.8mm ball pitch) > package. These draw <50% of coolrunner II static power. Pins are 5v tolerant, > and would suffer no ill effects when Vcc goes away. Give it a look - > > Michael Thomas > LSC SFAE > New York/New Jersey > 631-874-4968 fax 631-874-4977 > michael.thomas@latticesemi.com > for the latest info on Lattice products - http://www.latticesemi.com > LATTICE - BRINGING THE BEST TOGETHER Thanks for the info, but yes, I have looked at them. This circuit also needs 5 volt IOs and I don't think the Z series has that. I thought I had a winner in the V series, but the quiesent current is 10 mA which is higher than is useful. Seems the programmable logic world has moved on from the 5 volt domain. They still make the older parts, but they don't produce new products with the newer features. The MCU market still demands 5 volt operations it seems. There is a lot more *new* MCU product with 5 volt power than there are PLDs and such. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55255
Hal Murray wrote: > > >This sounds a bit like sarcasm... cool! I don't like to operate a > >device outside the spec. If I am selling a board to someone who is > >using it as test equipment in a locomotive (the actual application which > >is driving the temperature spec) I am not going to run parts at 125C > >that are not spec'd to do their job above 85C. I don't really know you, > >but I recognize the name from here. Are you saying that you design > >parts outside their spec? > > There is a fine art to reading between the lines on data sheets. > I wish I could do it better. > > My rule of thumb is that I need to be able to justify what I do, > that is explain it to somebody who is smart enough to catch lies > and/or blunders. > > The old Xilinx data books had a nice section on speed corrections > for VCC and temperature. You could get another 5% if you were willing > to design your power supply to stay above nominal. Is that good > enough? Same for temperature. > > How about correcting pad driver speed for reduced load > capacitance when you need another ns or two? ... > > How about metastability? Find anything in the data sheet to cover > that? Seen any numbers at other than "typical" conditions? Was > Peter's lab "typical"? > > So, yes, I have cheated and I'll probably do so again. > > I don't quite have your whole circuit in mind, but I'd be willing to > trust that a CPLD would get the right answer doing unclocked logic > when it was hot. I wouldn't expect it to meet timing, but I don't > think I'd be worried about a few microseconds when I'm turning off > something that is too hot. Vol/Voh might not meet specs either. > Are you loading them at all? > > So if all you need is a few gates, I'd look into putting that in a > corner of a Coolrunner. (I'd probably put a heat gun on one, and > really cook it to verify what I was expecting.) > > That's not trying to discourage anybody from looking for > clean(er) solutions. Especially if the gear they design gets > near something massive like a locomotive. (Are you just recording > data, or controlling things?) > > But you do seem to be fighting a lot of constraints. Sometimes > it's better to put the hard problems in one place so you can > concentrate on them. (That may not apply here.) > > I like the suggestion of taking advantage of the too-hot shutdown > in the regulator chip. I wonder how tight that spec is? Do they > test it? ... That is an interesting idea, but the spec on the regulators are only a "typical" spec and it is 150C! Pretty much everything on this board is a hard design due to the size constraints. But most of it is done and this is the last bit of the hardware to resolve. Like I just wrote to Jim, it is looking like I an use an RTC to keep time when the power is off (not required obove 85C) and the MCU can then run on the 5 volt Vcc at the full automotive temp range. The problem I had was that the MCUs in the wider temperature range could not work on the battery backup voltage to keep time with the power off. Even though this RTC is not essential above the 85C "normal" operation range, the MCU can't meet all the requirements in one chip. Just so I can say I have covered the bases, I am looking for a wide temp range RTC. So far the only ones I have found don't do a good job of the other functions, but I'll keep looking for a day or so while I work out the rest of the details. Thanks to you and Jim for the suggestions and questions. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55256
I'm running into the same problem on my Altera design. My only solution at this time is to create a daughter board that plugs onto the expansion headers on my Altera Development Board. The daughter board will have some comparitor ICs with positive feedback. I also have 'debounce' logic for these inputs in the FPGA but that only helps for occasional big 'spikes' in the data (like switch bouncing). Perpetual lower magnitude noise needs the schmitt trigger solution. I'd be very interested in hearing of an on-chip schmitt trigger solution (altera or xilinix)! Jim "Jock" <ian.mcneil@uk.thalesgroup.com> wrote in message news:<b8r7d1$m21$1@rdel.co.uk>... > Is it possible to define a Xilinx Virtex input as a Schmitt trigger? > > On my application, some inputs have a 30ns rise time which seems to be > causing an intermittant timing problem. Reducing the input capacitance so I > get 10ns rise time fixes the problem, but I get RF problems elsewhere.Article: 55257
rickman wrote: > > Mikeandmax wrote: > > > > Rick Wrote - > > > > >I have been looking for a CPLD or even an SPLD that will take the full > > >automotive temperature range. The parts I have found all have some > > >limitation. The Coolrunner parts don't come in a small enough package > > >and the Lattice part I found draws too much static current. > > > > Hi Rick - have you looked at the recent Lattice 4000Z family devices? They are > > available industrial and automotive temp, and are in CABGA (.8mm ball pitch) > > package. These draw <50% of coolrunner II static power. Pins are 5v tolerant, > > and would suffer no ill effects when Vcc goes away. Give it a look - > > > > Michael Thomas > > LSC SFAE > > New York/New Jersey > > 631-874-4968 fax 631-874-4977 > > michael.thomas@latticesemi.com > > for the latest info on Lattice products - http://www.latticesemi.com > > LATTICE - BRINGING THE BEST TOGETHER > > Thanks for the info, but yes, I have looked at them. This circuit also > needs 5 volt IOs and I don't think the Z series has that. I thought I > had a winner in the V series, but the quiesent current is 10 mA which is > higher than is useful. > > Seems the programmable logic world has moved on from the 5 volt domain. > They still make the older parts, but they don't produce new products > with the newer features. The MCU market still demands 5 volt operations > it seems. There is a lot more *new* MCU product with 5 volt power than > there are PLDs and such. Just so my error is not corrected, Michael called me and explained that the 4000Z and the other 4000 family parts can be 5 volt tolerant if the Vio rail is connected to 3.3 volts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55258
pramod@procsys.com (Pramod) wrote in message news:<a7c0720d.0304292309.2ab9f1f2@posting.google.com>... > Hi, > Tom, thanks for the idea on confluence core. I hope you might have a > case study or app note on an IIR implementation using this core. I > would like to know the resource usage by the core. > Thanks and Regards, > Pramod We just uploaded a C test bench to OpenCores that demonstrates the use of the Confluence State Space Processor. The test bench illustrates the processor's interface and instruction set by running a program that implements a first order IIR filter with 2 coefficients. The test bench is a wrapper around the generated C processor core (16-bit data and 8-bit instruction addressing) and includes an instruction memory, a coefficient memory, processor port variables, and functions for initialization, sample period cycling, and recording simulation data. Just compile and run for simulation: $ gcc -Wall -o cf_ssp_16_8 cf_ssp_16_8.c ssp_first_order.c $ ./cf_ssp_16_8 $ dinotrace cf_ssp_16_8.vcd # Use your vcd viewer here... I don't have the exact resource usage on hand, but the core is very small, especially since mulitplication is done in software. Basically it boils down to: -an instruction counter; -16 registers, decoding logic, and multiplexers in the register file; -and a adder, some gate level logic, and a few multiplexers in the ALU. You'll find the test bench and the Confluence generated Verilog, VHDL, and C cores at: http://www.opencores.org/projects/cf_ssp/ Let me know if you need a different processor configuration other than those posted to OpenCores. Regards, Tom -- Tom Hawkins Launchbird Design Systems, Inc. 952-200-3790 tom1@launchbird.com http://www.launchbird.com/ > > tom1@launchbird.com (Tom Hawkins) wrote in message > > > > You may want to check out the Confluence State Space Processor > > on OpenCores: > > > > http://www.opencores.org/projects/cf_ssp/ > > > > We built the core specifically for linear operations including: > > FIR filters, IIR filters, and general multi-variable state > > space calculations; all of which are common in DSP and control > > applications. > > > > The core is a processor with a very simple instruction > > set -- only 8 instructions -- for addition, shifting, > > sign-extending, limiting, and loading constant coefficients. > > Multiplication is performed by sign-extending the data, then > > performing a series of shifts and conditional adds on an > > accumulator. > > > > The processor is designed for simplicity and takes up very > > little area. Because the processor runs a program every sample > > period, it works well for applications where the clock rate is > > significantly faster that the sample rate of the discrete function. > > > > The architecture gives you 16 registers for I/O, intermediate > > calculation, and state variables. Constants are stored in an > > external memory with an 8-bit address giving you a possible > > total of 256 different coefficients. > > > > The State Space Processor core is generated from Confluence with > > configuration parameters of data width and instruction address > > width. If you don't see the configuration you need, let me know > > and I'll generate a custom processor for you. > > > > Regards, > > TomArticle: 55259
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:3EB14C6E.29872510@yahoo.com... > Hal Murray wrote: > > > > >This sounds a bit like sarcasm... cool! I don't like to operate a > > >device outside the spec. If I am selling a board to someone who is Snip > > > I like the suggestion of taking advantage of the too-hot shutdown > > in the regulator chip. I wonder how tight that spec is? Do they > > test it? ... > > That is an interesting idea, but the spec on the regulators are only a > "typical" spec and it is 150C! > > Pretty much everything on this board is a hard design due to the size > constraints. But most of it is done and this is the last bit of the > hardware to resolve. Like I just wrote to Jim, it is looking like I an > use an RTC to keep time when the power is off (not required obove 85C) > and the MCU can then run on the 5 volt Vcc at the full automotive temp > range. The problem I had was that the MCUs in the wider temperature > range could not work on the battery backup voltage to keep time with the > power off. Even though this RTC is not essential above the 85C "normal" > operation range, the MCU can't meet all the requirements in one chip. > > Just so I can say I have covered the bases, I am looking for a wide temp > range RTC. So far the only ones I have found don't do a good job of the > other functions, but I'll keep looking for a day or so while I work out > the rest of the details. > > Thanks to you and Jim for the suggestions and questions. > Don't laugh - but have you considered cooling? I'm thinking of placing all your components on a PCB with good thermal contact with an aluminium plate. This plate/system is thermally isolated from your machine and has a peltier element to cool down the electronics. This is only a last resort solution. Will cost you 10$ for an element and a couple of watts of power consumption. Benefits is you can use commercial low temp. devices all through your system. Cheers KlausArticle: 55260
Here are two solutions: You can make any input into a Schmitt trigger, but it costs you an extra pin: http://support.xilinx.com/support/techxclusives/6easy-techX37.htm or you can make the inside circuit immune to double-triggering. See www.xilinx.com/xcell/xl34_54.pdf I hope either of these circuits helps. Peter Alfke, Xilinx Applications Jock wrote: > > Is it possible to define a Xilinx Virtex input as a Schmitt trigger? > > On my application, some inputs have a 30ns rise time which seems to be > causing an intermittant timing problem. Reducing the input capacitance so I > get 10ns rise time fixes the problem, but I get RF problems elsewhere.Article: 55261
Any oscillator that is based on internal propagation delays will have fairly wide tolerances, and Vcc and temperature sensitivity. What frequency range and stability are you after? Peter Alfke, Xilinx frank wrote: > > Hello, > > Does anyone know of an fpga that contains at least 2 oscillators whose > frequency can be programmed / tuned ? > I am aware that fpgas contain ring oscillators that are used during > their testing phase, can these oscillators be somehow harnessed ? > Any feed back will be EXTREMELY helpfull. > > thx > -FrankArticle: 55262
Ray Andraka wrote: > > You can make an input with hysteresis by using a pair of external resistors and > two I/Os (one input, one output). I think there is an app note on the Xilinx > website. Yes: http://support.xilinx.com/support/techxclusives/6easy-techX37.htm Peter Alfke >Article: 55263
Jim, look at http://support.xilinx.com/support/techxclusives/6easy-techX37.htm Would work even with Altera ;-) Peter Alfke, Xilinx ======================= "Jim M." wrote: > > I'm running into the same problem on my Altera design. My only > solution at this time is to create a daughter board that plugs onto > the expansion headers on my Altera Development Board. The daughter > board will have some comparitor ICs with positive feedback. > > I also have 'debounce' logic for these inputs in the FPGA but that > only helps for occasional big 'spikes' in the data (like switch > bouncing). Perpetual lower magnitude noise needs the schmitt trigger > solution. > > I'd be very interested in hearing of an on-chip schmitt trigger > solution (altera or xilinix)! > > Jim > > "Jock" <ian.mcneil@uk.thalesgroup.com> wrote in message news:<b8r7d1$m21$1@rdel.co.uk>... > > Is it possible to define a Xilinx Virtex input as a Schmitt trigger? > > > > On my application, some inputs have a 30ns rise time which seems to be > > causing an intermittant timing problem. Reducing the input capacitance so I > > get 10ns rise time fixes the problem, but I get RF problems elsewhere.Article: 55264
The old Spartan and SpartanXL had an internal oscillator where you could choose one of a few different frequencies. But as Peter says, there is wide tolerance - the datasheet says "-50% to +25%" which isn't really useful if you need any sort of accuracy! Peter > Any oscillator that is based on internal propagation delays will have > fairly wide tolerances, and Vcc and temperature sensitivity. > What frequency range and stability are you after? > > Peter Alfke, Xilinx > > frank wrote: > > > > Hello, > > > > Does anyone know of an fpga that contains at least 2 oscillators whose > > frequency can be programmed / tuned ? > > I am aware that fpgas contain ring oscillators that are used during > > their testing phase, can these oscillators be somehow harnessed ? > > Any feed back will be EXTREMELY helpfull. > > > > thx > > -FrankArticle: 55265
I was wondering if anyone had any hints on implementing per bit dynamic alignment on an interface to a Xilinx FPGA (as is used with a SPI-4.2 interface, for example). I understand the overall concept of utilizing a training pattern and a "learning algorithm" to adjust for the correct phase offset for each bit. However, I am more specifically wondering how to implement the per bit phase shift within a Xilinx architecture. I have not seen any app. notes on the details of implementing this type of per bit dynamic delay. Any thoughts? Thanks! -Mark DixonArticle: 55267
The question relates to the handling of timing related issues while designing carry skip adders in FPGAs, or for that matter in ASICS. If a carry skip adder is designed let us say 4 stage in an FPGA, then seeing the unpredictability of carry generation at each stage, how is the timing handled, i.e how do u ascertain whether the initial carry will by pass or whether to wait for the generated carry. Henceforth when do you expect the subsequent sums and carry to be true data and not junk.Because if we take it as the critical apth and wait for the time till the actual carry is generated then the speed benefit goes.Article: 55269
Our project is using Motorola 68HC12 (DG128A) and its MSCAN communication. I am interested in using some other MCUs that may not have built-in CAN support. Is there CAN IP core available in public domain, so I can set up my own FPGA to drive my Philips CAN transceiver chip?Article: 55270
"Brendan Lynskey" <brendan@comodogroup.com> wrote in message news:AuOra.13028$xd5.668531@stones.force9.net... > Hi. > > Just a few questions about SystemC - very grateful for all answers... > > Are SystemC hardware models synthesizeable? Yes, if written in a synthesisable subset of SystemC. There are tools from Synopsys, Forte Design Systems, and Future Design Automation (and possibly others I've forgotten - see www.systemc.org and click on "products and solutions"). > Would the OO nature of SystemC aid hardware re-use? Not necessarily, as another poster said SystemC is a C++ class library which allows all the features of C++ such as operator overloading to be used. The main current use of SystemC seems to be in platform Transaction Level Modelling (platform TLM) rather than at RTL. At the more abstract level then you can achieve high levels of re-use. One of the main aims of SystemC is to promote re-use of testbenches at different levels of abstraction. > Would running a hardware/software co-simulation in SystemC be > significantly faster/slower than in an RTL simulator? > This is one of those "apples and oranges" questions! For platform TLM, SystemC can achieve something like 100x-1000x speed up over RTL co-simulation essentially by using an accurate bus model with simplified (abstract) peripherals. I don't have any figures comparing RTL in say Verilog vs SystemC, but I would expect SystemC to be slower with the reference simulator from www.systemc.org, simply because the kernel has not been developed and improved for 20 years! Some companies are implementing improved versions of the kernel which run faster (e.g. Coware) regards Alan > Thanks in advance, > > -- > Brendan Lynskey > Comodo Research Lab > > Click on www.comodogroup.com/secure-email to keep your emails > confidential with a complementary FREE personal Secure Email Certificate > > -- Alan Fitch HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: alan.fitch@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 55271
On Thu, 01 May 2003 14:01:34 GMT, Ray Andraka <ray@andraka.com> wrote: >The problem is that since version 4.1 of the software, you can no >longer count on the router doing a good job given a good placement. Previous >versions did an excellent job finding pretty much optimal routes for a given >placement. The current router stops improving each net as soon as it has a >positive slack, so unlike the previous router, nearly every net has a delay >close to the period constraint when the design is aggressive and it >unneccesarily eats up routing resources. Have you tried overconstraining the timings by (say) 10% and then relaxing the constraints on a Timegrp consisting solely of the (hopefully few) failing paths? ISTM this could be semi-automated with a script. No I haven't tried it, I'm still using 3.3! :-) But I have tried overconstraining, and sometimes been surprised by how few paths fail constraints. (This may or may not be the case with your aggressively floorplanned designs) - BrianArticle: 55272
Maybe you can look at the new 'zero Power' Lattice parts. They are available in small packages, complete automotive temp. range is covered as well. Inputs are even 5V tolerant. On Wed, 30 Apr 2003 20:28:53 -0400, rickman <spamgoeshere4@yahoo.com> wrote: > Opps, I forgot to include the more important group... c.a.f! > > I have been looking for a CPLD or even an SPLD that will take the full > automotive temperature range. The parts I have found all have some > limitation. The Coolrunner parts don't come in a small enough package > and the Lattice part I found draws too much static current. > > However, I think I may have figured out a way to do this using the > Xilinx Coolrunner industrial grade parts in the much smaller CSP > package. The board will be powered by 5 volts. A small LDO will > provide power to the XCR3032XL or XCR3064XL CPLD. The over temp sensor > will disable the LDO cutting power to the CPLD. This way the CPLD will > be protected. In addition, the CPLD outputs should go high impedance > allowing the power control to the rest of the board to be pulled high > turning off power. > > The only fly in the ointment I can see is voltage on some of the > inputs. These inputs are pulled up to 5 volts at all times and one > comes from off card and may be driven to 5 volts such as with a jumper. > The data sheet says the inputs are only rated for voltage up to 4 volts > above Vcc. Is there a way to provide protection to these inputs with a > resistor in series and still allow inputs to the board to be actively > pulled up to the 5 volt rail while the device is not powered? > > -- Using M2, Opera's revolutionary e-mail client: http://www.opera.com/m2/Article: 55273
Following another thread where data was unclear on device thermal
specs,
below is a summary of 3 suppliers Data specs, for thermal management.
Of the 3, Lattice have the clearest info, and a designer can define
a operating point for given thermal resistances and thermal loads.
Atmel do give some rules for commercial -> industrial, but they do
not specify thermal loads.
Neither Xilinx, nor Atmel quote operating Tj MAX for the three classes,
and as such their data is incomplete. [Peter / Austin ? ]
-jg
Temperature Calculations:
TJ [Die]
/
/ ThetaJ-C
/
Tc
/
/ ThetaC-A
Ta.i
/
Ta.o /
TJ - Junction temperature
Tc - Case Temperature
Ta.i - Ambient temperature (internal to box)
Ta.o - Ambient temperature (outside box)
Theta = thermal resistance, 'C/Watt
Summary: Tj is what really matters.
Cautions: Tc can be elevated by adjacent hot devices, to give a
higher 'local ambient'. The lower the power within the device, and
the lower the thermal resistances, the closer the Tj gets to Ta.i
Conversely, Ta can increase, provided you keep Tj within spec.
------------------- Lattice quote ----------------------
Absolute Maximum Ratings
Storage Temperature -65 to 150°C
Junction Temperature (Tj) with Power Applied -55 to 150°C
Compliance with Lattice Thermal Management document is required.
( found at http://www.latticesemi.com/lit/docs/package/thermal.pdf )
5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed.
Recommended Operating Conditions Tj
Junction Temperature (Commercial) 0-90'C
Junction Temperature (Industrial) -40-105'C
Junction Temperature (Automotive) -40-130'C
[Comment: As the Tj increases, the speed grade decreases, leakages
increase.]
----------------------- Atmel quote -----------------
Absolute Maximum Ratings
Temperature Under Bias -40°C to +85°C
Storage Temperature -65°C to +150°C
Junction Temperature 150°C Max
[Atmel rules for Temp Grade moves]
Using 'C' Product for Industrial:
To use commercial product for Industrial temperature ranges,
down-grade one speed grade from the 'I' to the 'C' device
(7 ns 'C' => 10 ns 'I') and de-rate power by 30%.
--------------------- Xilinx Quote -----------------
Absolute Maximum Ratings
TJ Maximum junction temperature -40 to 150 °C
TSTR Storage temperature -65 to 150 °C
Recommended Operating Conditions
TA Ambient temperature -40 to +125 °C
[Xilinx are remiss in not quoting an operating Tj MAX, nor do they give
a thermal load under which the TA is acceptable]
Article: 55274Mikeandmax wrote: > Hi Rick - have you looked at the recent Lattice 4000Z family devices? They are > available industrial and automotive temp, and are in CABGA (.8mm ball pitch) > package. These draw <50% of coolrunner II static power. Pins are 5v tolerant, > and would suffer no ill effects when Vcc goes away. Give it a look - Michael, When trawling the Lattice 'fine-print', I noticed this tag "5. Maximum of 64 I/Os per device with VIN > 3.6V is allowed." Q: Why is a max pin-count needed for this spec ? Lattice also do not spec a Vcc-IO limit, but do infer that Vcco should be kept within 3-3.6V when IO's are above 3.6V (3.6-5.5V). Q: What happens, if 5.5V is applied, with Vcco closer to 0V ? Xilinx spec's suggest there is a stress rating on this element, and the voltage across the float-enabling diode-FET should be kept below a MAX value. -jg
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