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Hi Mike, You are correct, the PCI32 Nios Target board plugs into the PMC connectors on the APEX Nios board. Unfortunately, the PMC connectors were removed from the Startix and Cyclone Nios boards. As far as prototyping is concerned, I believe you can can do prototyping for designs that will end up in Cyclone using a Stratix board just as well. The reason is because Startix is a superset of the Cyclone and as long as you make sure you do not use a feature in Stratix that is not supported in Cyclone you are well on your way. The best way to do that is just compile the design in Quartus for Cyclone while you are prototyping to ensure that will be able to use Cyclone in the end. If you are doing something wrong with Cyclone, Quartus will tell you. Quartus will also give you the timing you should expect for the design in Cyclone. Altera is about to fully release a Stratix PCI development board. See http://www.altera.com/products/devkits/altera/kit-pci_stx.htm. This board allows you to also prototype Nios Based applications. You will have to do some of your own work to get the Nios stuff to work on the board, but it should not be that hard if you are familiar with Nios. Finally, when you say PCIMG style backplane. Is it Compact PCI, PMC or something else? The board I am talking about is standard PCI and may not address your need for CompactPCI or PMC. Regards, Ziad Abu-Lebdeh mxv@yahoo.com (mike) wrote in message news:<8ea508fe.0304281139.3f6ef067@posting.google.com>... > The Altera PCI32 Target daughtercard doesn't seem to be compatible > with the Cyclone NIOS board. The Cyclone NIOS board doesn't have the > same connectors as the older Apex NIOS this daughtercard was designed > for. Correct me if I'm wrong, Altera. > > Any other vendors out there working on a Cyclone PCI board? I'm > looking for a PCI host version that would fit into a PICMG passive PCI > backplane. That's asking for a lot, but it doesn't hurt to ask. > > BTW, is anyone out there using the Cyclone 1C3 in a PCI application? > It doesn't have PCI buffers, but I'm wondering if anyone has worked > around this issue. > > Thanks. > > > > > "Paul Leventis" <paul.leventis@utoronto.ca> ha scritto nel messaggio > > news:SY8qa.141485$BQi.97105@news04.bloor.is.net.cable.rogers.com... > > > Hi Mike, > > > > > > One product Altera offers is the PCI32 Nios Add-on Dev Kit. This is a > board > > > that you hook-up to any Nios dev kit (including the Cyclone version), and > > > you can plug it into a PCI32 slot. It provides a PCI interface to your > Nios > > > dev board, an API, etc. I don't know anything about it besides what's on > > > our web site. > > > > > > You can read about it here: > > > > > > http://www.altera.com/products/devkits/altera/kit-dev_nios_pci32.html > > > > > > - Paul > > > > > > "mike" <mxv@yahoo.com> wrote in message > > > news:8ea508fe.0304242036.224f0c6e@posting.google.com... > > > > I've searched the web with no luck for a PCI development board with > > > > using an Altera Cyclone part. Probably because it's a new part, but if > > > > anyone knows where I can find one, please post a link. It must be > > > > Cylone, and it can be a PCI board or PMC module. > > > > > > > > Thanks in advance. > > > > > >Article: 55226
Jim Granville wrote: > > rickman wrote: > > > > Opps, I forgot to include the more important group... c.a.f! > > > > I have been looking for a CPLD or even an SPLD that will take the full > > automotive temperature range. The parts I have found all have some > > limitation. The Coolrunner parts don't come in a small enough package > > and the Lattice part I found draws too much static current. > > > > However, I think I may have figured out a way to do this using the > > Xilinx Coolrunner industrial grade parts in the much smaller CSP > > package. The board will be powered by 5 volts. A small LDO will > > provide power to the XCR3032XL or XCR3064XL CPLD. The over temp sensor > > will disable the LDO cutting power to the CPLD. This way the CPLD will > > be protected. In addition, the CPLD outputs should go high impedance > > allowing the power control to the rest of the board to be pulled high > > turning off power. > > I'm not sure I see the problem. > Coolrunner parts in static conditions will have (effectively) no > thermal > adders, and Tj will be == Ta. Why do you want/need to remove the Vcc ? The absolute max of 150C is where they say no damage will occur. But they don't claim that the parts will operate within spec above the rated max of 85C. I *could* use the part above 85C and do my own test that it still works (output drive, switching time, etc...). But I don't want to have to invest in an oven for all my boards. They have an automotive grade that is tested to 125C which is the number I need to support in shutdown. I also want to do a shutdown for power consumption issues and prefer not to use two pass transistors. To control just one transistor for both functions I have to have logic added. It is either a few picogates or a PLD. Since I need a 32 or 64 macrocell PLD on the board anyway, it seems natural to use the same PLD. But just like with the MCUs, I am finding that automotive temperature parts just don't have the flexibility as even industrial parts. <grip mode on> I am still looking for more parts. Too bad that temperature is not something that most vendors put in their selection guides... if they *have* selection guides. I fully expect that Hitachi has an MCU that will do exactly what I want. But I can't download every data sheet they have to find out. They don't have one scrap of information on their MCUs other than what you will find in the data sheets. At over a megabyte each you can likely fill a CD with them and more. <grip mode off> > - do you believe there is a sudden, drastic failure > mode that occurs if the device hits 86'C when biased ? > - how is that failure mode avoided if the IO pins are instead run > at Abs max 4V ? This sounds a bit like sarcasm... cool! I don't like to operate a device outside the spec. If I am selling a board to someone who is using it as test equipment in a locomotive (the actual application which is driving the temperature spec) I am not going to run parts at 125C that are not spec'd to do their job above 85C. I don't really know you, but I recognize the name from here. Are you saying that you design parts outside their spec? As to the voltage spec, I have a question in to Xilinx about it. > If you have a clocked device, that has a high thermal loading, then > removing the clock can buy a good chunk of 'thermal tolerance', > ( and the system effectively goes into 'thermal pause' ) I understand that. That is one reason why I want to use a coolrunner part. Hence the term "Coolrunner". (note my sarcasm... :) I took no offense, I hope you don't either. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55227
rickman wrote: > <snip> > The absolute max of 150C is where they say no damage will occur. But > they don't claim that the parts will operate within spec above the rated > max of 85C. I *could* use the part above 85C and do my own test that it > still works (output drive, switching time, etc...). But I don't want to > have to invest in an oven for all my boards. They have an automotive > grade that is tested to 125C which is the number I need to support in > shutdown. I also want to do a shutdown for power consumption issues and > prefer not to use two pass transistors. To control just one transistor > for both functions I have to have logic added. It is either a few > picogates or a PLD. Since I need a 32 or 64 macrocell PLD on the board > anyway, it seems natural to use the same PLD. But just like with the > MCUs, I am finding that automotive temperature parts just don't have the > flexibility as even industrial parts. > <snip> > > - do you believe there is a sudden, drastic failure > > mode that occurs if the device hits 86'C when biased ? > > - how is that failure mode avoided if the IO pins are instead run > > at Abs max 4V ? > > This sounds a bit like sarcasm... cool! I don't like to operate a > device outside the spec. If I am selling a board to someone who is > using it as test equipment in a locomotive (the actual application which > is driving the temperature spec) So do you have real numbers of Temperature/Time profiles you need to meet ? > I am not going to run parts at 125C > that are not spec'd to do their job above 85C. I don't really know you, > but I recognize the name from here. Are you saying that you design > parts outside their spec? No, it boils down to how you define 'run'. If you remove Vcc, but keep voltage on the I/O's is that 'running the device' ? Which will cause more stress - to push I/O -> Vcc, or to keep Vcc present, with no thermal load ? Some vendors use the terms : Temperature Under Bias 85'C Storage Temperature 150'C If you want to be inside this spec, you must remove all bias @ 85'C If you compare the Automotive specs, and the Indust spec, they have the SAME abs MAX Tj (which is what really matters to the chip) Xilinx's Automotive spec is rather lax, in quoting a Ta but with no thermal loads ( so how can they KNOW Tj ?!) ( I think it's lattice who do a more correct spec). Speed and leakage are certainly relaxed with the higher Ta, but I see no other indicators of sudden failure. (ISTR ISP issues in another thread at extreme temperatures ?). Testing will be more costly, and they also have to lower the performance bar, which is why Automotive spec devices are relatively rare. As I mentioned before, talk with Xilinx, find out what is different about the Automotive specs, and what does not work. eg Maybe ISP fails above 85'C - will that bother your app ? Atmel effectively admit it's all the same silicon, by giving rules for how to de-rate Commercial -> industrial usage. Why not ask Xilinx if they can do the same ? Ta for an IC, also means the surface of the (hottest) package, not the air outside your case, so you will need to factor that slope into the design - more than one temp sense may be needed. -jgArticle: 55228
>This sounds a bit like sarcasm... cool! I don't like to operate a >device outside the spec. If I am selling a board to someone who is >using it as test equipment in a locomotive (the actual application which >is driving the temperature spec) I am not going to run parts at 125C >that are not spec'd to do their job above 85C. I don't really know you, >but I recognize the name from here. Are you saying that you design >parts outside their spec? There is a fine art to reading between the lines on data sheets. I wish I could do it better. My rule of thumb is that I need to be able to justify what I do, that is explain it to somebody who is smart enough to catch lies and/or blunders. The old Xilinx data books had a nice section on speed corrections for VCC and temperature. You could get another 5% if you were willing to design your power supply to stay above nominal. Is that good enough? Same for temperature. How about correcting pad driver speed for reduced load capacitance when you need another ns or two? ... How about metastability? Find anything in the data sheet to cover that? Seen any numbers at other than "typical" conditions? Was Peter's lab "typical"? So, yes, I have cheated and I'll probably do so again. I don't quite have your whole circuit in mind, but I'd be willing to trust that a CPLD would get the right answer doing unclocked logic when it was hot. I wouldn't expect it to meet timing, but I don't think I'd be worried about a few microseconds when I'm turning off something that is too hot. Vol/Voh might not meet specs either. Are you loading them at all? So if all you need is a few gates, I'd look into putting that in a corner of a Coolrunner. (I'd probably put a heat gun on one, and really cook it to verify what I was expecting.) That's not trying to discourage anybody from looking for clean(er) solutions. Especially if the gear they design gets near something massive like a locomotive. (Are you just recording data, or controlling things?) But you do seem to be fighting a lot of constraints. Sometimes it's better to put the hard problems in one place so you can concentrate on them. (That may not apply here.) I like the suggestion of taking advantage of the too-hot shutdown in the regulator chip. I wonder how tight that spec is? Do they test it? ... -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55229
Jhon, Maybe I didn't mention it , but I'm working with Virtex II. In Virtex II slices, the D input to the lower LUT can also come from an input called "ALTDIG". The reason for the That solves my problem with the MUXF5 control. The reason for the one-slice packing is that the slice is of repicated hundreds/thousands of times. The packing is essential to my design. Jason, I like your idea about the feedback. The problem is that an outside mux will cost me more slices. I would be better off putting only one RAM per slice.Article: 55230
Hal Murray wrote: > <snip> > I like the suggestion of taking advantage of the too-hot shutdown > in the regulator chip. ISTR it's in the die-degrade region of 165'C ( 150'C + 10% ) Interesting that IC's tend to have 130'C or 150'C Tj max, whilst PowerMOSFETS often have Tj of 175'C > I wonder how tight that spec is? :) - not very, it's to prevent the smoke release next-step. > Do they test it? ... Yes, but likely not on every device - it will be sample tested. Any extreme thermal cycling has other reliability problems, and fatigue failure mechanisms are common. In a recent design we did, much design effort went into moving the heat from the SMD power FETS, through various paths and out through the plastic case, as well as reducing the milli-ohms in the PCB traces as much as possible. -jgArticle: 55231
Hi Brendan,
> Just a few questions about SystemC - very grateful for all answers...
>
> Are SystemC hardware models synthesizeable?
It's the same story as in VHDL: Some will be and some won't
be synthesizable.
Btw., Synopsys has developed some synthesizer for SystemC right now.
But I can't tell you how advanced it is at the moment.
> Would the OO nature of SystemC aid hardware re-use?
I think the reusability is independent from object orientation.
It's actually the same as in common programming languages.
You don't need an object oriented language (say C++) in order
to reuse functions. The same thing can be achieved in a common
language (say C).
The reason main why SystemC is based on C++ rather than C is
that there you have a chance to overload operators. Generally,
SystemC is not heavily object oriented. This is also explicitely
stated somewhere (i.e. you do not need extensive C++ skills in
order to make use of SystemC).
> Would running a hardware/software co-simulation in SystemC be
> significantly faster/slower than in an RTL simulator?
I can't tell you that as I have made no experiments yet.
But you can make a try by yourself. The simulator core for
SystemC is free - even Open Source!
Regards,
Mario
--
----------------------------------------------------------------------
Digital Force / Mario Trams Mario.Trams@informatik.tu-chemnitz.de
Mario.Trams@wooden-technology.de
Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr
Dept. of Computer Science Tel.: (+49) 371 531 1660
Chair of Computer Architecture Fax.: (+49) 371 531 1818
----------------------------------------------------------------------
Article: 55232"Subroto Datta" <sdatta@altera.com> ha scritto nel messaggio news:5_0sa.81$4V6.15968358@newssvr15.news.prodigy.com... > Andrea, > I assume you mean that the Input signal feeds a register, or the Output > signal is fed by a register, and that you want the register in the IOE (IO > Element) to be used by the place and route tool. In Quartus II you may apply > the Fast Input Register or Fast Output Register assignment to the pins or > registers directly. This assignment can me made using the Assignment > Organizer in Quartus II. > > - Subroto Datta > Altera Corp. > > > "AP" <NSP_a.paterniani@NSP_swapp-eng.it> wrote in message > news:b8p5aq$5l3$1@lacerta.tiscalinet.it... > > Hi all, > > > > How can I control if an I/O pin is registered or not? > > > > Thanks, > > Andrea > > > > > > > > Please tell me the exact steps I have to do Thanks, AndreaArticle: 55233
Hi I am trying to download a design into an FPGA via JTAG. The chain goes through a PROM before the FPGA and I need to associate a dummy mcs file with the PROM to allow the software to pass through. My question is: what is the purpose of the mcs file and what constitutes a 'dummy' mcs file (I.e. what does it contain) ? Thanks in advance and apologies if this is a daft question -- Cheers! MikeArticle: 55234
Michael Nicklas <michaeln@nospam.slayer.com> wrote: : Hi : I am trying to download a design into an FPGA via JTAG. : The chain goes through a PROM before the FPGA and I need to associate a : dummy mcs file with the PROM to allow the software to pass through. : My question is: : what is the purpose of the mcs file and what constitutes a 'dummy' mcs file : (I.e. what does it contain) ? : Thanks in advance and apologies if this is a daft question Associate a .bsd file with the other parts in the chain. The .bsd or dummy files are needed by the programmer to route the signals through the unused parts. The .mcs file is used for programming the PROM otherwise. Ise will produce it. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55235
OK just have my third FPGA project working. This is an area optimized version of some DES like algo. The full expanded version did not fit in the Spartan II 200 (Digilentinc digilab 2), but in this version I use a state machine (loop) for each DES round, and it works sort off. Used 50 MHz clock multiplied to 200 MHz. The following problems apply: I can reset it (using Spartan II startup), but about 1 in 30 times it then gets the result wrong (it does a decode on reset). There can be many reasons for this, but I suspect some timing issue. This COULD have to to with layout in the FPGA. So HOW can I arrange the layout in WebPack? Or do I need to buy some extra too for that? I deed read the nice papers on Ray Andraka's site how to make filters with multipliers and he then has these neatly aligned next to each other on the silicon. How do I do this with webpack? The other thing is: Why do some simple logic circuit I used many times not seem to work in FPGA? For example a D flop, with a 1 on the D is clocked by some pulse on the input. The Q out is inverted and connected to the reset of a counter. The counter then starts counting (clock input connected to system clock), and when TC goes high, this is connected to the reset of the D flop, and the D flop resets and the counter stops. Sort of a one- shot sequence anytime the D flop is clocked. I tried this both in schematic entry, and verilog, both with async and synchr. reset flop and counter, and no way will it work. In the real non FPGA world I have made many little boxes using this simple circuit, for example for dark room timers, and stuff like that (yes those had thumb wheel switches). If I try the verilog version it does not work either, or I get 'template not supported' in WebPack or something. For this same reason I had to make a simple routine that dumps a 64 bit value in hex to the terminal, could not do it with the above circuit, finally made a big 176 bit shift register and that works (16 x (1 start, 8 data, 2 stop bits) )..... So I am now at the point where I have more questions then answers... Any general hints about how to go about these things would be appreciated (references? I did read the 'in depth' Xilinx webpack stuff). Pro is I'm learning. But things should be simpler or anyways I am still not on top of it. Want to thank Xilinx again for the free webpack, and Mr Andraka for his very clear papers. Regards Jan PS does there exist a board with an affordable Spartan II or the like version with 800 k gates? Or will I have to design one? This also brings the problem of simple flat pack (versus ball grid array). For many applications (for example this one only has serial in / serial out , a LED and a reset, simple package (DIL if must be, 'Z80' size?) with fewer pins spaced apart more would be a great help for the avid 'experimenter' I.M.O. I notice a lot of free space on some FPGA boards I have seen, and then what is against a package like 40 pin DIL? So, :-)Article: 55236
Thanks Uwe Now to try and find the .bsd file! Mike "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:b8qvrt$hjp$1@news.tu-darmstadt.de... > Michael Nicklas <michaeln@nospam.slayer.com> wrote: > : Hi > > : I am trying to download a design into an FPGA via JTAG. > > : The chain goes through a PROM before the FPGA and I need to associate a > : dummy mcs file with the PROM to allow the software to pass through. > > : My question is: > > : what is the purpose of the mcs file and what constitutes a 'dummy' mcs file > : (I.e. what does it contain) ? > > : Thanks in advance and apologies if this is a daft question > > Associate a .bsd file with the other parts in the chain. The .bsd or dummy > files are needed by the programmer to route the signals through the unused > parts. > > The .mcs file is used for programming the PROM otherwise. Ise will produce > it. > > Bye > > -- > Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55237
Yes you did "Jim Stewart" <jstewart@jkmicro.com> wrote in message news:51E3B1BB6FF54211.1891BEB1EF60218C.834ADF2C29D567FF@lp.airnews.net... > Michael Condon wrote: > > First of all don't post questions or comments on the board if your going to > > be an A-hole about it. As far as your "Famous Last Words" goes that's what > > your going to be if you don't get up to speed with the current design > > techniques. > > > > Some people lead, some people follow, and some people go the way of the > > Do-Do Bird. > > > > As far as your clients go; some might prefer schematic now, but that's > > because they aren't hardware engineers. > > > > Yes C is still useful but what about Abel, Fortran, etc. As an engineer you > > need to learn the newer techniques or you will be left behind. My post was > > meant to be helpful and to point out where the new technology is going. > > > > Most if not all design tools now a days can read in VHDL or Verilog code and > > convert it to schematic designs. Then you can take the HDL code and give it > > to a hardware engineer who can make changes to the code quicker and easier > > then if they were given a schematic design. > > > > I'm sorry that you want to continue to use schematic entry for your design, > > but if you take the time to learn the current design techniques then the > > power of HDL languages will become apparent to you. > > > > But if you just want to be mad and run around like a twelve year old kid > > upset at the world then you can do that on your own time.....don't post > > messages here! > > I guess I missed the vote that made you moderator of this group. > > > >Article: 55238
Is it possible to define a Xilinx Virtex input as a Schmitt trigger? On my application, some inputs have a 30ns rise time which seems to be causing an intermittant timing problem. Reducing the input capacitance so I get 10ns rise time fixes the problem, but I get RF problems elsewhere.Article: 55239
Hello, Does anyone know of an fpga that contains at least 2 oscillators whose frequency can be programmed / tuned ? I am aware that fpgas contain ring oscillators that are used during their testing phase, can these oscillators be somehow harnessed ? Any feed back will be EXTREMELY helpfull. thx -FrankArticle: 55241
Michael Nicklas <michaeln@nospam.slayer.com> wrote: : Thanks Uwe : Now to try and find the .bsd file! <webpack-directory>/xc18v00/data/ : "Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message : news:b8qvrt$hjp$1@news.tu-darmstadt.de... Please, no full quotes attached below the new text. This poissons the archives. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55242
YIKES! I like to think I understand the technology fairly well, thank you. I wasn't condemning the technology, only the stupid decisions made on the 4.x and 5.x place and route that eliminated the delay based clean up in favor of a faster time to completion. With careful floorplanning and a decent router you can get very dense designs that run at very high clock rates, I do it all the time. The problem is that since version 4.1 of the software, you can no longer count on the router doing a good job given a good placement. Previous versions did an excellent job finding pretty much optimal routes for a given placement. The current router stops improving each net as soon as it has a positive slack, so unlike the previous router, nearly every net has a delay close to the period constraint when the design is aggressive and it unneccesarily eats up routing resources. The result is every path becomes a critical path, the routing gets unnecessarily congested, and for high performance dense designs you often will not meet timing even though the part is perfectly capable thanks to the router stepping all over itself. The fact of the matter is that I can achieve considerably better performance (and more consistent) and lower power consumption using the 3.3sp 8 router with the updated speed files than I can with the newer router. Unfortunately, I can't use the 3.3 router on VirtexII, IIPro, SpartanIIe or spartan3 parts. For large DSP designs, there is no need to use a larger part if the smaller one has sufficient resources. See the gallery on my website for some examples of the stuff I do. evans39084@aol.com wrote: > I can relate to the problems you are having with the place and route > tools. I have spent countless hours tring rewrite and optimze my VHDL or > schematics designs. We all try to obtain the maximum performance in the > smallest real estate possible. You need to better understand the > technology your working with before comdeming it. On a Xilinx device, > maximun performance can usually be obtained until 99% of the slices are > consumed. After that, unrelated logic packing in the slice occures to > fit the design. This unrelated logic, and associated rat nest of routes > used to perform this packing, is where the delays start to become a > problem. The constraints file setup my the designer helps the software > determine which signals are the most critical and give highest priority. > To maintain maximum performance, the size of the FPGA should be large > enough to minimize or eliminate the unrelated logic packing. There will a > large amount of unused resources, but performance usually doesn't come > without a price. For large DSP's, you may need multiple smaller FPGA's > instead of one large one. > > As far as SystemAce is concerned, it is still new software. Any bugs it > may have, will be fixed eventually. > > Welcome to the real world. > > Ray Andraka <ray@andraka.com> wrote in > news:3EA5A01C.3F9E2878@andraka.com: > > > The problem is that there are no third party place and route tools. > > The place and route tools are where the worst bugs (features) are. > > The one that is particularly debilitating is the laziness of the > > router in versions 4.x and 5.x that makes all paths in a design become > > critical paths. > >Article: 55244
Rick Wrote - >I have been looking for a CPLD or even an SPLD that will take the full >automotive temperature range. The parts I have found all have some >limitation. The Coolrunner parts don't come in a small enough package >and the Lattice part I found draws too much static current. Hi Rick - have you looked at the recent Lattice 4000Z family devices? They are available industrial and automotive temp, and are in CABGA (.8mm ball pitch) package. These draw <50% of coolrunner II static power. Pins are 5v tolerant, and would suffer no ill effects when Vcc goes away. Give it a look - Michael Thomas LSC SFAE New York/New Jersey 631-874-4968 fax 631-874-4977 michael.thomas@latticesemi.com for the latest info on Lattice products - http://www.latticesemi.com LATTICE - BRINGING THE BEST TOGETHERArticle: 55245
On Thu, 1 May 2003 14:00:42 +0000 (UTC), Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: >Please, > >no full quotes attached below the new text. This poissons the archives. I thought the archives were fishy. Now I know why. Allan.Article: 55246
For audio rates, you could do a delta-sigma adc and dac, or you could use an
external ADC. I think there are one or two that have audio codecs on them, but
I don't know which boards those might be.
Brendan Lynskey wrote:
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3EAEDDED.B54FD49E@andraka.com...
> > What are the required specs for the ADC and DAC?
>
> I wanted to experiment with FPGA/DSP techniques by playing with some
> real-time spectral audio processing, so I was looking for (ideally) 16-bits
> @ something like 48K samples/s.
>
> I suppose maybe FPGAs aren't the best choice of hardware for this type of
> processing (high complexity with low sample rate) but this choice of
> application was made as an enjoyable vehicle for learning the techniques.
>
> >If the sample rate is low,
> > you might be able to use a run of the mill board and use delta-sigma
> techniques
> > for the converter. I believe xilinx has app notes available on that. If
> you
> > need more than audio rates, then the number of candidate boards is
> narrowed
> > considerably. You might start by looking at the links to 3rd party boards
> on
> > the Xilinx website.
> >
>
> Thanks for your help,
>
> Brendan
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55247
You can make an input with hysteresis by using a pair of external resistors and
two I/Os (one input, one output). I think there is an app note on the Xilinx
website.
Jock wrote:
> Is it possible to define a Xilinx Virtex input as a Schmitt trigger?
>
> On my application, some inputs have a 30ns rise time which seems to be
> causing an intermittant timing problem. Reducing the input capacitance so I
> get 10ns rise time fixes the problem, but I get RF problems elsewhere.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55248I've got a testbench that takes a long time to run, and as it runs the memory usage of ModelSim slowly ramps up. After about 5 million simulated clock cycles, I'm out of memory. I don't see why more memory should be needed as the simulation progresses, when there are no signals on the waveform viewer. The memory is not released when I restart or reload the simulation, but only when I close ModelSim. Is there some kind of bug in my (VHDL) model which could cause this, or is it a memory leak in ModelSim? Maintenance on ModelSim was allowed to expire a couple of years ago due to cost-cutting, so any ideas would be appreciated.Article: 55249
evans39084@aol.com wrote in message news:<vb1508fogi3s1f@corp.supernews.com>...
> I can relate to the problems you are having with the place and route
> tools. I have spent countless hours tring rewrite and optimze my VHDL or
> schematics designs. We all try to obtain the maximum performance in the
> smallest real estate possible. You need to better understand the
> technology your working with before comdeming it. On a Xilinx device,
> maximun performance can usually be obtained until 99% of the slices are
> consumed. After that, unrelated logic packing in the slice occures to
> fit the design. This unrelated logic, and associated rat nest of routes
> used to perform this packing, is where the delays start to become a
> problem. The constraints file setup my the designer helps the software
> determine which signals are the most critical and give highest priority.
> To maintain maximum performance, the size of the FPGA should be large
> enough to minimize or eliminate the unrelated logic packing. There will a
> large amount of unused resources, but performance usually doesn't come
> without a price. For large DSP's, you may need multiple smaller FPGA's
> instead of one large one.
>
> As far as SystemAce is concerned, it is still new software. Any bugs it
> may have, will be fixed eventually.
>
> Welcome to the real world.
>
>
> Ray Andraka <ray@andraka.com> wrote in
> news:3EA5A01C.3F9E2878@andraka.com:
>
> > The problem is that there are no third party place and route tools.
> > The place and route tools are where the worst bugs (features) are.
> > The one that is particularly debilitating is the laziness of the
> > router in versions 4.x and 5.x that makes all paths in a design become
> > critical paths.
> >
> > Evan wrote:
> >
> >> I've worked with various tools since FPGA's first appeared. You
> >> can't beat the price and performance of the software provided by
> >> Xilinx or Altera. Their software may have bugs, but you can usually
> >> work around them. If the vendor put as much effort to make the
> >> perfect software product you wanted. You wouldn't be able to afford
> >> it. Has it stands, the high end software tools cost $10,000 to
> >> $20,000+. Altera and Xilinx provide these tools as a low cost
> >> alternative, to help promote their sales. If you can't deal with it,
> >> put up the big bucks and buy the good software. Don't ruin a good
> >> thing for the rest of us.
> >>
> >> billh40@aol.com (Bill Hanna) wrote in
> >> news:97d137ce.0304171001.5ec5461d@posting.google.com:
> >>
> >> > I have been designing a Digital Signal Processor using the XC2V4000
> >> > chip.
> >> > Software errors in ISE 4.2 and 5.1 have caused long hours of delay
> >> > in developing the design:
> >> >
> >> > Software bugs in SystemAce causes erase problems in the MPM.
> >> > Deleting signal wires in ECS causes Fatal errors that crash the
> >> > system.
> >> > A large design exceeds the 2GB memory limit and generates a
> >> > fatal
> >> > memory error.
> >> >
> >> > I have designed Altera chips for over 6 years and never had a
> >> > problem.
> >> >
> >> > All digital designers should stop designing new projects with
> >> > Xilinx ICs until Xilinx corrects all software problems with ISE.
> >> >
> >> > Bill Hanna
> >
> > --
> > --Ray Andraka, P.E.
> > President, the Andraka Consulting Group, Inc.
> > 401/884-7930 Fax 401/884-7950
> > email ray@andraka.com
> > http://www.andraka.com
> >
> > "They that give up essential liberty to obtain a little
> > temporary safety deserve neither liberty nor safety."
> > -Benjamin Franklin, 1759
> >
> >
> >
Thanks for your information. I exceeded the 99% limit at 23,038
slices on a XC2V4000 and it never finished routing. It ran for 3 days
over the weekend. I ended up stopping the routing process. I am using
a 2GHz P4 with 1GB DDR SDRAM and 3.5GB VM. The normal synthesis time
is 9 hours and 1 hour to route for 17,000 slices (72% of the XC2V4000
chip). I will use your guide line of 99% max of 22,800 slices.
Bill Hanna
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