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On our Virtex2 board we have a single clock input; if we disable the clock signal and than we re-enable it, the device gets 'stuck'. I read a posting in this newsgroup about a similar problem that was traced back to the BUFGMUX. Xilinx folks explained that the BUFGMUX is not a simple mux. Is it possible that also my problem is related to that ? -- Tullio Grassi ====================================== Univ. of Maryland - Dept. of Physics College Park, MD 20742 - US Tel +1 301 405 5970 Fax +1 301 699 9195 ======================================Article: 55301
Let's look at this from the inside out. Your 800k-gate FPGA chip will measure about 7 x 7 mm. (I remember that the XC2V6000 die is about 21 x 21 mm, and you want about 8 times less in area, about 3 times less on each side. We can argue about gate count metrics, but this will be close.) If you stuff this little chip of less than 300 mil on-a-side into a big 40-pin package with 600 mil width, 100 mil pin spacing, and 2 inch total length, (I remember those things well) you inevitably end up with some very long bonding wires or lead-frame metal runs, once you get away from the nice central pins (which should be dedicated to Vcc and ground) The worst wires will be an inch or even 30 mm long, and their inductance will be totally unacceptable for modern fast output transitions. And don't even mention wire-wrap... So, the 40-pin DIP is a dead issue for modern circuits, even if FPGA vendors wanted to cater to the small market for very low pin-to-logic-ratio devices. Peter Alfke ========================== Jan Panteltje wrote: > > On a sunny day (Fri, 02 May 2003 11:35:42 GMT) it happened Ray Andraka > <ray@andraka.com> wrote in <3EB258D6.D81F9E08@andraka.com>: > > >The long wires on the 40 pin DIL make it impractical for the high edge > >speeds on modern FPGAs. > Well if I look at my digilab 2 then there is a l o n g set of wires coming > from the FPQ208 or whatever. > If you use the middle pins on the DIL 40 for supply, the wires are short (for > decoupling). > 70 ties he? > I started designing with RTL that was long before that... > Then we had DTL too. > > > >If you really want a 40 pin package, use an > >adapter such as those made by Ironwood. Make sure you put bypass caps on > >the adapter close to the FPGA. 40 pin DIPs are so 70's. Time to move > >into the new millenium. BTW, there is a step in between BGAs and DIPs. > >The smaller Xilinx parts, for instance, come in 44 pin quad flat packs. > Yes but I want 800 K gates in ONE package. > > Really I see those manufacturers have some strange concept about more gates > -> more pins. > More then 700 pins on the Actel 750 k gates for example. > Why? > IO depends on the IO, not on the complexity of the logic. > It is just an assumption, that cannot possible hold either in the long run, > 7000 pins for a 7 million gates? > No logic here. > > The 40 pin DIL is easy to use on protoboard, you can make your own boards, > double sided will do, man even single sided. > MY opinion is that a lot of people have no idea what FPGA sales could improve > if the chips were more relaxed in packaging. > Many people start with DIL PIC micro controllers, they sell by the > millions. > High density FPGA with few pins is ideal for crypto and for example filters. > As your own short-wave filters... > I designed some transceivers with real stuff (like coils oops), it is > ALWAYS a tradeoff. > How about a good SAW filter :-) FPGA will beat it in flexibility. > I would like to experiment with that one day if I find the time. > So many projects going on... > Anyways thank you for the nice site, fascinating stuff. > Regards > JanArticle: 55302
Well, I just looked at opencores.org, and there it is. It was posted in March 2003. I checked their site frequenty last year, but I am getting really busy lately. Thank you very much! Will definitely try it when I get time... "Lorenzo Lutti" <lorenzo.lutti@DOHtiscalinet.it> wrote in message news:0tysa.85501$iy5.2621432@twister2.libero.it... > "Ching Wang" <bwang@remove.hal-pc.org> ha scritto nel messaggio > news:3eb221ee$0$67179$a726171b@news.hal-pc.org... > > > support. Is there CAN IP core available in public domain, > > Try there: > > www.opencores.org > > Seems like they have a CAN IP core, but I haven't tried it yet. > > -- > Lorenzo > >Article: 55303
Hi Im currently working on a project which will have a camera data digitisted at 20MHz 16 bit data. Then brought into FPGA and converted to 32 bit data and then written into external SDRAM. The Data is then Read from the SDRAM back into FPGA and put onto USB Bus and then displayed screen. I need the DRAM as I will need to hold up to 5 frames of Data 1 Frame will be 0.5Mb so 5 frames will be 2.5MB Would anyone have experience of this type of project and if so any advice would be gratefully recieved. AndyArticle: 55307
Hi all, Can anyone tell the diffferences between Cadence NCSim and NCSim Desktop. Also Which is the best one for VHDL/Verilog Simulation. Please compare Modelsim and VCS too. thanks LIJOArticle: 55308
"ah" <andrew@hanvey82.freeserve.co.uk> schrieb im Newsbeitrag news:b906aq$n3t$1@newsg4.svr.pol.co.uk... > Hi > Im currently working on a project which will have a camera data digitisted > at 20MHz 16 bit data. > Then brought into FPGA and converted to 32 bit data and then written into > external SDRAM. > The Data is then Read from the SDRAM back into FPGA and put onto USB Bus and > then displayed screen. > > I need the DRAM as I will need to hold up to 5 frames of Data > 1 Frame will be 0.5Mb so 5 frames will be 2.5MB > > Would anyone have experience of this type of project and if so any advice > would be gratefully recieved. www.micron.com They are one of the big suppliers of SDRAM & stuff. They have also good datasheets. Have a look at some xapps from xilinx, they describe a SDRAM interface, complete with VHDL code. This task should be straight forward. -- MfG FalkArticle: 55309
Should be straightforward up to the point saying 'USB', although you might find that using static ram, and therefore not requiring refresh, would make the job a little easier. The USB side of things is not so straightforward, and you should look for a suitable module and don't forget the required system software ! Probably the easiest way to do something like this is to buy one of the standard PCI interface chip eval cards, and couple the camera directly to it. Then use the PCI bus to stream video into PC memory - giving you hundreds of Mb !. Just a couple of days work ... Good luck ! Dave "ah" <andrew@hanvey82.freeserve.co.uk> wrote in message news:b906aq$n3t$1@newsg4.svr.pol.co.uk... > Hi > Im currently working on a project which will have a camera data digitisted > at 20MHz 16 bit data. > Then brought into FPGA and converted to 32 bit data and then written into > external SDRAM. > The Data is then Read from the SDRAM back into FPGA and put onto USB Bus and > then displayed screen. > > I need the DRAM as I will need to hold up to 5 frames of Data > 1 Frame will be 0.5Mb so 5 frames will be 2.5MB > > Would anyone have experience of this type of project and if so any advice > would be gratefully recieved. > > Andy > >Article: 55310
Hi Atif, I am not familiar with the MJL kit you are talking about, but Altera does have a 1S80 Kit for DSP. Check it out here: http://www.altera.com/products/devkits/altera/kit-dsp_stratix_pro.html Ziad Abu-Lebdeh azafar@iupui.edu (Atif Zafar) wrote in message news:<6ed146ef.0305010820.682b01be@posting.google.com>... > Does anyone have experience with the MJL Stratix dev kit. It is the > lowest cost Stratix EP1s25 kit I could find. Anyone know whether it > can handle devices denser than the 1s25 (i.e. 1s40 or 1s80?). I have > an imaging and 3d graphics pipeline project. Does anyone know whether > the Virtex II are a better choice or the Stratix? Thanks. > > Atif Zafar > Indiana UniversityArticle: 55311
I must tell you that I have not tried to get the DDR SDRAM on ACEX 1K but I have worked with DDR SDRAM on Stratix and I know that Cyclone was also designed to work with DDR SDRAM applications. ACEX 1K family was released several years before the DDR SDRAM. I know that DDR SDRAM has minium 100 MHz. I think that the EP1K100 -3 will have a difficult time making the tight timing you will need for the DDR. DDR requires very tight setup and hold times that you will have to meet to actually get the DDR SDRAM to work. You will also need to get two registers on every output to clock data within very low timing tolerances. Cyclone and Stratix both have special circuits in the I/O that can actually get the tight timing without too much effort from you. By the way, Cyclone is the lowest cost FPGA in the market. The only thing that ACEX 1K has over it is the 5.0 Volt tollarnace which is a little outdated for DDR based designs. Regards, Ziad Abu-Lebdeh "AP" <NSP_a.paterniani@NSP_swapp-eng.it> wrote in message news:<b8p0lp$2s2$1@lacerta.tiscalinet.it>... > Hi all, > > has anybody experience of designing a DDR SDram Controller on ACEX1K > (EP1K100QC208-3) ? > I need informations on: > * does EP1K100QC208 speed grade -3 include a pll cell? > * maximum reachable frequency > * possible skew problems between fpga internal clock and ram clocks and some > suggestion on how manage them. > > Moreover, does DDR SDram need a minimum clock frequency? > > Thanks in advance! > > AndreaArticle: 55312
Mike, The Stratix board I was talking about will work as an add-on card in that backplane if the backplane meets the PCI standard. If you want to make it a Host card, then you will have to do some soldering. You can use the 64-bit signals on the Stratix card to just solder jumpers to any pin on the 32-bit side of the connector. This should be enough for you to get REQ, GNT and the interrupt pins to work. You will have to make sure you do very clean soldering and keep the wires as short as you can. For the clock, get a shielded wire that you can solder a ground with it on both ends. You can just put a wire between one of the clock crystals on the board to the clock pin on the PCI connector and that will give you a PCI clock. The one thing that I do not know is how they get the clocks to the other slots. I thought I saw some clock traces on the backplane board so I do not think you will have any issues in meeting the clock skew. Good luck, Ziad mxv@yahoo.com (mike) wrote in message news:<8ea508fe.0305020832.7736174e@posting.google.com>... > Ziad, > > Thanks for the information. > > We are trying to prototype a PCI host bridge for an embedded system. > > A PCI development board that would function in the CPU slot of a PCI > only version of a PICMG 1.0 passive backplane would address our needs. > See PBP-04P at http://www.portwell.com/backplane.htm#pci for an > example of the backplane we're considering. > > A card in the CPU slot has to supply the PCI clock and REQ and GNTs to > the other slots. The arbitration signals are straitforward to > implement if the FPGA pins are connected to the appropriate pins on > the edge connector, but the clocks have meet PCI skew requirements. > > Would the Altera Stratix PCI development board meet these > requirements? > > Thanks, > Mike > > > > > zabulebdeh@yahoo.com (Ziad Abu-Lebdeh) wrote in message news:<f784b02b.0304302031.a3476d9@posting.google.com>... > > Hi Mike, > > > > You are correct, the PCI32 Nios Target board plugs into the PMC > > connectors on the APEX Nios board. Unfortunately, the PMC connectors > > were removed from the Startix and Cyclone Nios boards. > > > > As far as prototyping is concerned, I believe you can can do > > prototyping for designs that will end up in Cyclone using a Stratix > > board just as well. The reason is because Startix is a superset of > > the Cyclone and as long as you make sure you do not use a feature in > > Stratix that is not supported in Cyclone you are well on your way. > > The best way to do that is just compile the design in Quartus for > > Cyclone while you are prototyping to ensure that will be able to use > > Cyclone in the end. If you are doing something wrong with Cyclone, > > Quartus will tell you. Quartus will also give you the timing you > > should expect for the design in Cyclone. > > > > Altera is about to fully release a Stratix PCI development board. See > > http://www.altera.com/products/devkits/altera/kit-pci_stx.htm. > > > > This board allows you to also prototype Nios Based applications. You > > will have to do some of your own work to get the Nios stuff to work on > > the board, but it should not be that hard if you are familiar with > > Nios. > > > > Finally, when you say PCIMG style backplane. Is it Compact PCI, PMC > > or something else? The board I am talking about is standard PCI and > > may not address your need for CompactPCI or PMC. > > > > Regards, > > > > Ziad Abu-Lebdeh > > > > mxv@yahoo.com (mike) wrote in message news:<8ea508fe.0304281139.3f6ef067@posting.google.com>... > > > The Altera PCI32 Target daughtercard doesn't seem to be compatible > > > with the Cyclone NIOS board. The Cyclone NIOS board doesn't have the > > > same connectors as the older Apex NIOS this daughtercard was designed > > > for. Correct me if I'm wrong, Altera. > > > > > > Any other vendors out there working on a Cyclone PCI board? I'm > > > looking for a PCI host version that would fit into a PICMG passive PCI > > > backplane. That's asking for a lot, but it doesn't hurt to ask. > > > > > > BTW, is anyone out there using the Cyclone 1C3 in a PCI application? > > > It doesn't have PCI buffers, but I'm wondering if anyone has worked > > > around this issue. > > > > > > Thanks. > > > > > > > > > > > > > "Paul Leventis" <paul.leventis@utoronto.ca> ha scritto nel messaggio > > > > news:SY8qa.141485$BQi.97105@news04.bloor.is.net.cable.rogers.com... > > > > > Hi Mike, > > > > > > > > > > One product Altera offers is the PCI32 Nios Add-on Dev Kit. This is a > board > > > > > that you hook-up to any Nios dev kit (including the Cyclone version), and > > > > > you can plug it into a PCI32 slot. It provides a PCI interface to your > Nios > > > > > dev board, an API, etc. I don't know anything about it besides what's on > > > > > our web site. > > > > > > > > > > You can read about it here: > > > > > > > > > > http://www.altera.com/products/devkits/altera/kit-dev_nios_pci32.html > > > > > > > > > > - Paul > > > > > > > > > > "mike" <mxv@yahoo.com> wrote in message > > > > > news:8ea508fe.0304242036.224f0c6e@posting.google.com... > > > > > > I've searched the web with no luck for a PCI development board with > > > > > > using an Altera Cyclone part. Probably because it's a new part, but if > > > > > > anyone knows where I can find one, please post a link. It must be > > > > > > Cylone, and it can be a PCI board or PMC module. > > > > > > > > > > > > Thanks in advance. > > > > > > > > > >Article: 55313
Or just use a PCI data logging card and dump right into memory. e.g. national instruments have such a card. Do your colour space or corrections in software? I have also done what you are trying to do. I used 40MHz (burst) 32bit data and 32MB. I had input and output 'simultaneously'. If you can afford to simplify to doing a whole memory page worth for input or output and then seeing what needs to be done next to balance load between buffered input and output, this is simplest to control and is effective use of the SDRAM bandwidth without too many overlapping SDRAM commands etc. Very simple particularly if you pick up one of the SDRAM manufacturer testbenches that simulate the memory and report any violations you created. Micron have a VHDL one that was relatively painless to use. Sadly I can't let you have the design :( Paul "dave garnett" <dave.garnett@metapurple.co.uk> wrote > Probably the easiest way to do something like this is to buy one of the standard PCI interface chip eval cards, and couple the > camera directly to > it. Then use the PCI bus to stream video into PC memory - giving you hundreds of Mb !. Just a couple of days work ...Article: 55314
At 10MHz clock the thing would be technically doable. The original poster never mentioned the usual 200MHz+. A do-your-own 68000 cpu kind of. Rene Peter Alfke wrote: > Let's look at this from the inside out. > Your 800k-gate FPGA chip will measure about 7 x 7 mm. (I remember that > the XC2V6000 die is about 21 x 21 mm, and you want about 8 times less in > area, about 3 times less on each side. We can argue about gate count > metrics, but this will be close.) > If you stuff this little chip of less than 300 mil on-a-side into a big > 40-pin package with 600 mil width, 100 mil pin spacing, and 2 inch > total length, (I remember those things well) you inevitably end up with > some very long bonding wires or lead-frame metal runs, once you get away > from the nice central pins (which should be dedicated to Vcc and ground) > The worst wires will be an inch or even 30 mm long, and their inductance > will be totally unacceptable for modern fast output transitions. And > don't even mention wire-wrap... > > So, the 40-pin DIP is a dead issue for modern circuits, even if FPGA > vendors wanted to cater to the small market for very low > pin-to-logic-ratio devices.Article: 55315
Hi - On Sat, 03 May 2003 18:26:14 GMT, Rene Tschaggelar <tschaggelar@dplanet.ch> wrote: >At 10MHz clock the thing would be technically doable. >The original poster never mentioned the usual 200MHz+. >A do-your-own 68000 cpu kind of. If there's one thing that gets designers into signal integrity trouble, it's the, "But it's only going to be running at (fill in your own low clock rate)" line of reasoning. Risetime tends to be far more critical than clock rate. One of the worst clocks I've ever seen was running at only 1 MHz, but had a sub-nanosecond driver and was badly terminated. You can slow down the clock to one Hz, but if the asynchronous signals (e.g., clocks) are glitchy and the ground is buzzing like a box full of bees, the design still may not work. Strongly in favor of SMT packages, despite the fact that my eyes can no longer focus on stuff that small, Bob Perlman Cambrian Design WorksArticle: 55316
Bob Perlman wrote: > Hi - > > On Sat, 03 May 2003 18:26:14 GMT, Rene Tschaggelar > <tschaggelar@dplanet.ch> wrote: > > >>At 10MHz clock the thing would be technically doable. >>The original poster never mentioned the usual 200MHz+. >>A do-your-own 68000 cpu kind of. > > > If there's one thing that gets designers into signal integrity > trouble, it's the, "But it's only going to be running at (fill in your > own low clock rate)" line of reasoning. Risetime tends to be far more > critical than clock rate. One of the worst clocks I've ever seen was > running at only 1 MHz, but had a sub-nanosecond driver and was badly > terminated. > > You can slow down the clock to one Hz, but if the asynchronous signals > (e.g., clocks) are glitchy and the ground is buzzing like a box full > of bees, the design still may not work. > > Strongly in favor of SMT packages, despite the fact that my eyes can > no longer focus on stuff that small, You're right. The slewrates would have to be limited too. BTW: A pair of 4 dioptries reading glasses can do wonders. ReneArticle: 55317
On a sunny day (Fri, 02 May 2003 21:10:05 GMT) it happened Rene Tschaggelar <tschaggelar@dplanet.ch> wrote in <38a2492e9fe271a36567dcc69baa5f2a@TeraNews>: >Jan Panteltje wrote: >> 5 on an euro card 160 x 100 mm >> 10 cards in a 19 inch rack. >> >> For my brute force key cracker. >> >> If not Xilinx then any other manufacturer if it comes with free tools. >> >> There is a market here, I am sure. >> If you FPGA manufacturers stick with ball grid you close off >> many possible inroads to FPGA. >> >> Hopefully the market forces will fill this space. > >Very unlikely. >A device with 800k gates produces quite a bit of heat at the intended >frequencies. FBGA solves part of this. Further, 40 pins for 800k gates >are considered far below the lean side. Meaning the market would be far >too small, just a handful of cavemen actually. >You cannot use wrapwires at 200MHz either. Forget it. >FBGA is doable. With some luck and especially with little IO requirement >perhaps even with a 2 layer pcb. > >Rene >-- >Ing.Buero R.Tschaggelar - http://www.ibrtses.com >& commercial newsgroups - http://www.talkto.net > Agreed on the heat, already experienced that when running this Spartan II 200 to maximum, it almost burned out the little AC adapter that comes with the proto- board. Somehow the FPGA survived, but you could see it starting doing very strange things when it got that hot. I do not know what the maximum is it will still clock, but a lot more then 200 MHz I think. Sort of accidently had part of my DES algo see its input.... hehe Have to look up some timings... JanArticle: 55318
On a sunny day (Fri, 02 May 2003 15:50:47 -0700) it happened Peter Alfke <peter@xilinx.com> wrote in <3EB2F647.6187A7A8@xilinx.com>: >Let's look at this from the inside out. >Your 800k-gate FPGA chip will measure about 7 x 7 mm. (I remember that >the XC2V6000 die is about 21 x 21 mm, and you want about 8 times less in >area, about 3 times less on each side. We can argue about gate count >metrics, but this will be close.) >If you stuff this little chip of less than 300 mil on-a-side into a big >40-pin package with 600 mil width, 100 mil pin spacing, and 2 inch >total length, (I remember those things well) you inevitably end up with >some very long bonding wires or lead-frame metal runs, once you get away >from the nice central pins (which should be dedicated to Vcc and ground) >The worst wires will be an inch or even 30 mm long, and their inductance >will be totally unacceptable for modern fast output transitions. And >don't even mention wire-wrap... > >So, the 40-pin DIP is a dead issue for modern circuits, even if FPGA >vendors wanted to cater to the small market for very low >pin-to-logic-ratio devices. > >Peter Alfke > Hi, thank you for the reply. I am honored to hear from such a knowledgeable persons. Have been reading some of your posts and also the tech-notes on the Xilinx site. As you probably know I am just getting into FPGA. Some projects: Solid state video camera recording to flash memory. Super DES (sort of) brute force key searcher. Digital satellite TV receiver (still in 'contemplation phase'). So I am new but not to electronics. You are right about the problems with long leads, but if slow rise time is specified I think it will work. Of cause DIL 40 is an indication, there are the other packages, but in the higher gate count FPGAs (from any manufacturer it seems) they only come as ball grid, with +++ more pins then I even need. So you think it is a small market,, well, if you want to draw people into playing with FPGA having a more relaxed package will help. Personally for me I will likely stay away from ball grid, unless I get some mayor financial incentive. In many projects I worked you could get a cigar if you saved 10% on the cost of a design. Cheaper boards do help. You know, the WHOLE industry LOVES iic (i2c) bus, lower pin count, serial. Man even Rambus memory and so many thing go serial. The reason is cost. Why should this not apply to FPGA? Think about it. Right in front of me I now have a proto board with a Spartan II 200 and iic chips (Philips) for the camera stuff connected to it. The widest data bus in the whole system will be 8 bits at about 37 MHz. Of cause if I need more then 200 k gates (and I do) I need more FPGAs and the interconnect would be a wider bus. But if everything fits into one FPGA then the wiring is very simple. I just downloaded 'picoblaze' and although I found nice PCI emulation on www.opencores.com, this seems small and interesting 'pre-cooked'. Then what I have (still have to get it working) is a small micro with digital filters in one chip for signal processing. No need for 700 pins, no way. So, you guys know more then me about FPGAs I am sure. So, feel free to disagree, and you could be right. On the other hand there are thousands of potential electronic minded people who, if boards with high gate count FPGA could be easily made, would use more and more of that good stuff you guys make. So, anyways, it will take me time to get to grips with all this. Having a proto-type board helps. Regards JanArticle: 55319
On a sunny day (Fri, 02 May 2003 21:26:19 GMT) it happened Ray Andraka <ray@andraka.com> wrote in <3EB2E344.65185F37@andraka.com>: >The package, and therefore the number of pins is driven to a large extent by the >die size and the cavity sizes in the packages. FPGA dies are large, so they >won't fit in many of the small packages, especially as you get towards the >million gates density. It is also far easier for you to not use the extra pins >than it is for another user to work around a shortage of pins, and each package >option adds a very real cost to the manufacturer's as well as the distributor's >bottom line. There is also the issue of dynamic ground current on the larger >devices, which requires low impedance connections, which in turn translates to >lots of power/ground pairs. 40 pins isn't much if you need 30+ of them for power >supply. With the small geometries of the current fab technologies, an inch to >the bypass leaves a very significant inductance between the supply plane and the >chip, enough to make the bypass cap pretty much useless. > >40 pin devices were in their heyday in the late 70's and early 80's. Before >that, there were very few devices with enough pins, after that they fell out of >favor for the smaller and better electrically quad flat packs and PLCC packages. >I don't recall *any* RTL or DTL devices in 40 pin DIPs. Even if you do manage to >put the FPGA on an adapter, you'll likely encounter all sorts of signal integrity >gremlins with a single or double sided board given the very fast edge speeds of >modern FPGAs (it is not so much the clock speed, rather it is the rise and fall >times that will bite you). It can be done, but it takes an incredible amount of >SI work to get something that works right out of the chute. It is far cheaper >(when engineering hours are considered) to use a 4+ layer board with proper vcc >and ground planes than to invest in the huge signals integrity work or the seat f >the pants engineering (with it's associated debug). Sorry to break it to you, >but this is a different league than your RTL,DTL and TTL. For hobby use, the >easiest approach is to use one of the many premanufactured FPGA boards, many of >which are available for about what you'd pay for the parts on the board and for >making your single/double layer board. The shortwave receiver, for example is >done on an Insight SpartanII board, which sells for about $125. That one even >has a prototype area for adding your own circuits if you need it (I added 2 >resistors, 2 capacitors and a mini phone jack for the radio demo). OK, many good points, yes, no RTL in 40 DIL of cause... I use the digilentinc Spartan II 200 board, added veroboard connected to it with to 40 pin headers that was only 99$ (for the digilentic) (www.digilentinc.com digilab 2). It is exactly here where you shoot your own argument, as the leads from the FPGA to the connectors of that board and then continued via the headers to my proto-board are at least 10 cm. And no problems (I am using slow edge). Remains the decoupling. Yes this can be in the middle under the 40 PIN DIL (done that some times). Am I imagining this or are the leads then closer to the dye? And as far as power pins (quantity) goes, well, bond to the same (now much thicker) pins of the DIL package. See also my reply to Mr Alfke on this same subject for about iic bus. Regards JanArticle: 55320
Are there any examples of 802.11 verilog code available for appreciation either partially or fully completed. I am looking mostly for examples that I can use to appreciate architecture designs, not looking for a complete product. I have allready searched through opencores, just their ethernet mac is their. I am really looking for some additional knowledge on implementation details of the 802.11 specific details such as the various services (authentification, association, MSDU delivery, SIFS/PIFS/DIFS counters) and an example or two that I can study of their implementation. -- Charles Krinke http://home.pacbell.net/cfk cfk@pacbell.netArticle: 55321
Is there any obvious PLL chip to use with an FPGA? I want to do things like generate 100.0003001 MHz from 10 MHz. (Or generate 100 MHz from 9.999999371 MHz) I did a quick search the other day and didn't see much. I found lots of clock generation/distribution chips, typically 0 delay buffers but sometimes including mul/div by 2 or 4. There are a few chips that include mul/div registers, but they are small integers. I want to put that logic in the FPGA so I can implement many low order bits. Are there any good articles on this aspect of PLLs? I'm expecting there are some tricks for filtering out the low frequency noise injected by the occasional steps when the low bits accumulate to a whole tick and a cycle gets inserted/dropped. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55322
The choice of ACEX1K was not mine. I'm a consultant and I have to work on existent hardware and fit a DDR SDRAM controller and other in the FPGA. The memory is a MT46V8M16 and reading datasheet I see that the minimum frequency is 75 MHz (not 100 MHz). Do you think that this frequency may be acceptable for ACEX 1K? Also, to simplify the design, I'm thinking about the possibility of using the memory as a SDR SDRAM doubling the burts length (4 instead of 2) and using datas only on one edge (obviously loosing half of the memory space). What do you think about this? Andrea "Ziad Abu-Lebdeh" <zabulebdeh@yahoo.com> ha scritto nel messaggio news:f784b02b.0305030555.78acad95@posting.google.com... > I must tell you that I have not tried to get the DDR SDRAM on ACEX 1K > but I have worked with DDR SDRAM on Stratix and I know that Cyclone > was also designed to work with DDR SDRAM applications. ACEX 1K family > was released several years before the DDR SDRAM. I know that DDR > SDRAM has minium 100 MHz. I think that the EP1K100 -3 will have a > difficult time making the tight timing you will need for the DDR. DDR > requires very tight setup and hold times that you will have to meet to > actually get the DDR SDRAM to work. You will also need to get two > registers on every output to clock data within very low timing > tolerances. Cyclone and Stratix both have special circuits in the I/O > that can actually get the tight timing without too much effort from > you. > > By the way, Cyclone is the lowest cost FPGA in the market. The only > thing that ACEX 1K has over it is the 5.0 Volt tollarnace which is a > little outdated for DDR based designs. > > Regards, > > Ziad Abu-Lebdeh > > "AP" <NSP_a.paterniani@NSP_swapp-eng.it> wrote in message news:<b8p0lp$2s2$1@lacerta.tiscalinet.it>... > > Hi all, > > > > has anybody experience of designing a DDR SDram Controller on ACEX1K > > (EP1K100QC208-3) ? > > I need informations on: > > * does EP1K100QC208 speed grade -3 include a pll cell? > > * maximum reachable frequency > > * possible skew problems between fpga internal clock and ram clocks and some > > suggestion on how manage them. > > > > Moreover, does DDR SDram need a minimum clock frequency? > > > > Thanks in advance! > > > > AndreaArticle: 55323
"Ray Andraka" <ray@andraka.com> wrote in message news:3EB2E430.2D44E007@andraka.com... > Xilinx can't tell you what the power is going to be. It depends very heavily on > your design. If you need to know the power, Xilinx does provide the XPOWER tool > that will compute your power based on the actual place and route and simulation > vectors you feed the tool. THe accuracy will depend on how representative your > simulation vectors are of the actual operation. Xilinx also has some spread > sheets that can be used to get an estimate based on your estimates of the logic > used, your assessment of 'routing complexity', and your declaration of clock > rates and toggle rates. Those spread sheets will get you to about +/-12dB. The original question was in the XC4000 days, so I don't know if things have changed since. 12dB is probably good enough. The important question was if a fan and/or heatsink would be required. It is easy to imagine high clock rates with a significant fraction of FF's changing state on each clock cycle. -- glenArticle: 55324
"cfk" <cfk_alter_ego@pacbell.net> writes: D Are there any examples of 802.11 verilog code available for appreciation > either partially or fully completed. I am looking mostly for examples that I > can use to appreciate architecture designs, not looking for a complete > product. I have allready searched through opencores, just their ethernet mac > is their. I am really looking for some additional knowledge on > implementation details of the 802.11 specific details such as the various > services (authentification, association, MSDU delivery, SIFS/PIFS/DIFS > counters) and an example or two that I can study of their implementation. A lot of that is normally done in firmware, not hardware. The hardware typically only handles the lowest level of packet framing to interface to the radio.
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