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Try using FPGA_Editor to look at how the logic is actually implemented on the chip. It would appear that your synthesis is not correctly producing a single reset signal from "(CP_offline='1' or Reset='1')". In article <3e931135$0$24147$ba620e4c@reader0.news.skynet.be>, P. Joeste <pekmenNOSPAM@skynet.be> wrote: >Hi >For a project in school i am using a Xilinx FPGA of the XC4000E family. >The source code is almost ready but in many parts of the code I'm having >problems when simulating.(I'm using the Project Manager's built-in simulator >of Xilinx Foundation F3.1i) >This is the piece of the code that doesn't work: > >process (STROBE,Reset,CP_offline) >begin > if (CP_offline='1' or Reset='1') then ControlPanel_Online <= '0'; > elsif (STROBE'event and STROBE='0') then > if (X='1') then > ControlPanel_Online <= '1'; > end if; > end if; >end process; > >I suppose it's obvious what this should do. The signal ControlPanel_Online >is set to '1' when there's a negative edge on STROBE and X='1'; >This works in the simulation. >But when I try to set ControlPanel_Online back to '0' by making signal >CP_Offline '1', nothing happens! Only when I use the GlobalReset, I can get >ControlPanel_Online back to zero. >It must have something to do with the GSR-network of the FPGA, since I can >only use the GlobalReset and no other signal I intended to use as a reset >(like CP_offline). >Why is my CP_offline signal ignored? I'm not getting any warnings or errors >after synthesis so I really don't have a clue. > >I hope my question is clear and that it is a common problem? >Can someone help me out here? > >Thanks alot! >Peter > > > > > -- Caleb Hess hess@cs.indiana.eduArticle: 54351
Hi Andreas, The CoolRunner XPLA3 family allows the JTAG pins to multifunction as I/Os (after configuration). I am guessing that you have programmed the part that switches the JTAG pins to I/O pins. This would give you a warning similar to the one you described below. Check out this application note that describes how to reclaim the JTAG pins (see section "Port Enable Pin")... http://www.xilinx.com/xapp/xapp343.pdf Hope this helps, Jennifer Andreas Georgiou wrote: > Hello, > > I am using a Xilinx Coolrunner CPLD XCR3384. I test the board with > some simple designs and it was working ok (using webpack 5.2 and > iMPACT). > > Then I tried to load the entire design and it failed halfway while > programming the CPLD. Since then, the CPLD cannot be detected by the > software. Instead it says: > "Communications with the cable could not be establish. Check the cable > connections and cable power source" > > Other CPLDs are detected fine from the same software and same power > supply. Also, I tired older versions of the webpack without success. > > It seems that I somehow "lock" the CPLD or configured it improperly so > that I can do nothing to it now. If it is that, is there a simple way > to erase it without taking it off the board? > > Thanks, > > AndreasArticle: 54352
Andreas Georgiou wrote: > Hello, > > I am using a Xilinx Coolrunner CPLD XCR3384. I test the board with > some simple designs and it was working ok (using webpack 5.2 and > iMPACT). > > Then I tried to load the entire design and it failed halfway while > programming the CPLD. Since then, the CPLD cannot be detected by the > software. Instead it says: > "Communications with the cable could not be establish. Check the cable > connections and cable power source" > > Other CPLDs are detected fine from the same software and same power > supply. Also, I tired older versions of the webpack without success. > > It seems that I somehow "lock" the CPLD or configured it improperly so > that I can do nothing to it now. If it is that, is there a simple way > to erase it without taking it off the board? > > Thanks, > > Andreas Make sure about that the port_en is driven 'high'. laurent gauch www.amontec.comArticle: 54353
I wrote: > I'm thinking about using a Linear Technology LTC3406B synchronous buck > regulator for the 2.5V core Vdd for an XC2S150. Has anyone else used > this? It's rated for 600 mA, so it should be able to handle the 500 mA rickman <spamgoeshere4@yahoo.com> writes: > I would recommend the TI TPS54315PWP. This is a 3 Amp, 2.5 volt > switcher in a TSSOP20 package <7mm sq. The fixed voltage versions only > require three small passives other than the main components. They have This looks promising. Are you soldering down the power pad on the bottom of the part? I can't figure out how to do that without using reflow soldering, but my board is probably going to be hand assembled. Thanks! EricArticle: 54354
Just Some Guy wrote: > I have degrees in EE and Computer Science, > but am coming from a virtual zero knowledge point in programmable logic. If you were using schematics on your previous designs, consider doing the same on your first FPGA. This will be a good tutorial even if you end up using an HDL in the future. -- Mike TreselerArticle: 54355
"Dimitris Theodoropoulos" <theodor@mhl.tuc.gr> wrote in message news:<b6ub32$mjn$1@ulysses.noc.ntua.gr>... > Hello! I am trying to find the Hammond FPGA board from Embedded > Solutions Ltd with Xilinx's XC4028XLA HQ160 FPGA. Does anyone knows where I > can find more information and prices about it? Thank you very much for your > time! > > Regards, > Dimitris ESL is now Celoxia, & maybe Hammond is dust. Google didn't help.Article: 54356
Has anyone figured out a nice, clean method to track which phase of a Xilinx DLL's 1x clock corresponds to a 2x clock cycle? One 2x rising edge corresponds to the 1x rising edge, the other 2x rising edge corresponds to the 1x falling edge. When I start getting up in frequencies, the ability to use the 1x clock and inverted 1x clock to generate two signals that I can XOR for a phase is compromised. It's not inherently safe to use the 1x edges and 2x rising edges as "effectively" the same edge due to clock skews and input jitter issues. Using the falling edge of the 2x clock to sample the 1x generated signals works, but at the 1/4 period timing budget is too tight at the frequencies I'm working. For those who are Verilog friendly, the code here shows how I would "normally" extract the phase without running a clock through a LUT. The "negedge x2clk" is where the timing gets tough since the Tcko+Tnet+Tick is a little over the 1/4 period of my x1clk. always @(posedge x1clk) posTog <= ~posTog; always @(negedge x1clk) negTog <= posTog; always @(negedge x2clk) rawPhase <= posTog ^ negTog; always @(posedge x2clk) phase <= rawPhase; Is there a cleaner way to figure out the which half of the x1clk I'm in? Thanks, - John_HArticle: 54357
Hi Alex, > Between about 4 people none of us has managed to > get a usb to parallel port adaptor working as advertised. Yep, it's sounding pretty hopeless. As Jim said in his followup the bit banging is clearly happening quite low level... > Laptops > I'm a big fan of the Compaq EVO 400C. > Had one for a year. > [snip] > If you can wait a month or more until the new Intel chip(Banias) > starts coming out should be some decent price cuts. Ah yes but in university world we live with preferred supplier agreements and the like. It seems I can buy any brand I like, as long as it's a Dell.... :-/ They have the rather cute little C400 which is tiny, about the size of an A4 page, weighs very little, with enough grunt for what I need. No parallel port though, hence my query (although the docking station has one...) The next model up has an lpt port, but it's bigger and weighs more etc. A PCMCIA lpt port might be the ticket here, or mini-PCI or whatever it's called, I'll look into it. JohnArticle: 54358
Hi Jim, Jim Kearney wrote: >>>Anybody had success in this regard? Can you tell me which USB->LPT >>>adaptor you used? > > > I don't believe any of them will work for this kind of application. Xilinx > installs a device driver thats main purpose is to gain I/O port access to > the parallel port hardware in order to bit-bang the data lines. USB > adapters that I'm familar with work at a completely different level and > don't emulate the hardware at all and so won't work. Yup. > There are PCMCIA parallel port cards available that provide 'normal' > hardware, like the Quatech SPP-100. Interesting idea. Can anyone confirm or deny this? :) JohnArticle: 54359
Hi Folks, Thanks for all your suggestions so far. The following questions just illustrate how much I am unsure of relating to signed nos, so I hope you will give me a fools pardon. I did implement a C version of the fft converting each of the stage results to fixed point, but the results didn't match with what I saw in Modelsim so I was hoping you could point out any glaring errors. You are correct. Keeping track of the binary point and the sign bit is difficult. Here is what I was doing. Perhaps you can tell me if you think I am wrong. I think I have the butterfly stages correct, just the number of resulting bits that I am passing in and out of the various stages.. Note the operation inside the butterflys (especially 2nd butterfly is wrong). I know that, but I just want to get an idea of the number of bits I should be working with. I am particularly interested in the number of extra bits I need to add to the result for sign extension when a...multiplying (both for positive and negative eg Q15 numbers) b...adding (eg adding a Q15 number and a Q23 number) c...subtracting (eg subtracting a Q23 number and a Q15 number) Final thing I need to know is...does changing the output from the ist stage from Q15 to Q23 mess things up ? Ist butterfly stage a...I read in two words of 16 bit data Q15, X and Y b...I multiply one of the words Y by the twiddle factor which is 1 (0111111111111111) to get a 30 bit number plus 1 sign bit (total 31 bits) Note is this correct for multiplying negative nos ? ..ie number of bits c...I then add this 31 bit result to to the other 16 bit number X. I have allocated 32 bits for the result (31 bit number plus 1 sign bit) Total 32 bits....Result X d...I also have to subtract the multiplication result obtained in b, from X as well. I have also allocated 32 bits for this result (31 bit number plus 1 sign bit) Total 32 bits...Result Y ...Is this correct ? e...I then have to halve each of these results, so I do this by adding an extra sign bit onto each.(effectively shift right by 1...Now total number of bits is 33 f...I then pass out the two 24 MS bits to the next butterfly stage 2nd Butterfly Stage I a...I read in two words of 24 bit data Q23, X and Y b...I multiply one of the words Y by the twiddle factor (Q15 binary) to get a 38 bit number plus 1 sign bit (total 39 bits) Note is this correct for multiplying negative nos ? ..ie number of bits c...I then add this 39 bit result to to the other 24 bit number X. I have allocated 40 bits for the result (39 bit number plus 1 sign bit) Total 40 bits....Result X d...I also have to subtract the multiplication result obtained in b, from X as well. I have also allocated 40 bits for this result (39 bit number plus 1 sign bit) Total 40 bits...Result Y ...Is this correct ? e...I then have to halve each of these results, so I do this by adding an extra sign bit onto each.(effectively shift right by 1...Now total number of bits is 41 f...I then pass out the two 24 MS bits to the next butterfly stage Thats about it. Thanks BobArticle: 54360
The easiest, and cheapest (because FREE) solution is to request a license extension for LeonardoSpectrum-Altera directly from Mentor Graphics at ... http://www.mentor.com/alterapromo/ Moreover, Mentor Graphics is offering perpetual LeonardoSpectrum software licenses for very little money. And, as a very special offer, perpetual (not just a 1 month or a 1 year appertizer) licenses of the brand new Precision-RTL software. Juergen Jaeger Group Director, Mentor Graphics "Paul Baxter" <pauljnospambaxter@hotnospammail.com> wrote in message news:<3e8ca4c0$0$21990$cc9e4d1f@news.dial.pipex.com>... > From Altera: > Dear LeonardoSpectrum(TM)-Altera Software User, > > Beginning April 1, 2003, Altera will no longer include > LeonardoSpectrum-Altera software licenses in software subscriptions or > with free software products. Altera will, however, continue to provide > Mentor Graphics(R) ModelSim(R) products for subscription customers and > will continue to work with Mentor Graphics as a key EDA partner to > support Altera(R) devices in commercial Mentor Graphics products. > Existing LeonardoSpectrum-Altera software licenses will continue to > work and Altera will continue to provide support for existing > LeonardoSpectrum-Altera software licenses distributed by Altera. > > ----------------------- > > Firstly, my hope was April fool's joke, but I'm not sure if they would be so > cruel.... so > > Oh dear, Altera's software solution just got worse. > They have dropped Leonardo synthesis tools. > > Leonardo was largely essential for getting decent synthesis over the full > range of VHDL constructs. > > Oh well, lets hope Altera just sells a PAR solution for a lower cost, > because I really need to get away from the below par bug-ridden stuff I keep > having to deal with. > > Cue Altera telling me its all now wonderful. Like I've heard a hundred times > already. I'm getting worked up because I've spent years overcoming tool > deficiencies and was comfortable with Leonardo + ActiveHDL + Altera PAR. I > however am bitter that I need to pay Altera for a 'full' design flow just > for PAR. > > Altera - I don't want your tools with half-baked promises of things working. > How about a feature freeze and a bit more time aiming for robust and > reliable. > > By the way, I'm not suggesting that Leonardo didn't have bugs, or other > manufacturer's tools are any better, just that after years of fighting and > getting a least worse low-cost solution I now have to either pay for > Leonardo (fair enough especially if Altera's PAR can be provided on its own > for much lower $$$) or have more Altera synthesis grief. > > Paul Baxter, my opinions are my ownArticle: 54361
Hello, First, it's important to be clear that there are several high quality synthesis options available for all Altera products. Altera is committed to ensuring our customers have a full range of synthesis solutions for all of our devices, from our MAX CPLD devices to our high performance Stratix and Stratix GX families and the low-cost Cyclone family. Altera has strong partnerships with all of the major 3rd party synthesis tool vendors, including Mentor, Synopsys, and Synplicity. We also offer an integrated synthesis option that is included with all of the Quartus II Design Software packages. As a further service to our customers, Altera has worked with Mentor and Synplicity to make available some very attractive promotional offers for Altera synthesis solutions. For more information on the 3rd party synthesis tools available for Altera devices, please see the following page on our website: http://www.altera.com/products/software/pld/eda/partners/eda-index.html For more information on Altera's integrated synthesis tool, please download the following application note: http://www.altera.com/literature/an/an238.pdf Cheers, Chris Spam Hater <spam_hater_7@email.com> wrote in message news:<96319v4udn64fnkeqp04tr2q50srustpov@4ax.com>... > Kevin, > > Because Xilinx did the same thing a year and a half ago. > > Basically, both used OEM'd synthesis tools for their 5V FPGAs. Altera > used Leonardo, Xilinx used Foundation. > > Both have terminated their OEM agreements. > > Xilinx currently has -zero- synthesis tools for their 5V FPGAs. And > no intention to get them. > > At last with Altera, you can still use Max+II. > > $.02, > SH > > > On Fri, 04 Apr 2003 23:10:17 -0600, Kevin Brace > <kev0inbrac1eusen2et@ho3tmail.c4om> wrote: > > >Paul, > > > >I don't mean to start an A vs. X argument here, if you don't like what > >Altera did to you, why not switch to Xilinx?Article: 54362
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:b6vgbe$rmd$2@bunyip.cc.uq.edu.au... > > There are PCMCIA parallel port cards available that provide 'normal' > > hardware, like the Quatech SPP-100. > Interesting idea. Can anyone confirm or deny this? :) All I can do is quote their data sheet: "Quatech's SPP-100 fully supports the IEEE 1284 EPP standard, and functions exactly like a computer's native parallel port. Thus, unlike the many USB to parallel converters on the market, Quatech's SPP-100 will work seamlessly with any hardware or software that requires either an EPP or standard parallel port for operation or for security dongles." at http://www.quatech.com/catalog/parallel_pcmcia.php. It's not particularly cheap, though, considering that a parallel port is basically a few buffers - $129 list. There may be other brands, too.Article: 54363
Lis,
Quartus II 2.2 has very good language coverage for both synthesizable
VHDL and Verilog. Please feel free to email me any questions about language
constructs, and we can verify if there will be a problem or not.
- Subroto Datta
Altera Corp.
"Lis Hu" <lishu99@yahoo.com> wrote in message
news:4faf3f56.0304071140.2c053d3d@posting.google.com...
> Now that Altera has announced discontinuation of LeonardoSpectrum,
> I feel even more motivation to explore the alternatives. I plan
> to do a signal processing intensive application on a Stratix,
> and I wonder if anyone has any advice about the alternatives
> to Leonardo.
>
> Personally, I had a heck of time with the Leonardo GUI crashing and
> giving inconsistent results, and have just started scripting it. However,
> all of that "bad experience" does not give me confidence about the tool.
>
> Even though the Altera Reps are starting to say Quartus has VHDL
> support, there're constructs that it doesn't support. So as much
> as I had hoped that I can use a single tool flow, it is not an option
> at the moment.
>
> Synplify--I heard--is a faster tool? Any benchmarks out there?
>
> Precision RTL --I have never used. Would be interested to hear opinions.
>
> Thanks,
> Lis Hu
Article: 54364Hi Jim, > "Quatech's SPP-100 fully supports the IEEE 1284 EPP standard, and functions > exactly like a computer's native parallel port. Thus, unlike the many USB to > parallel converters on the market, Quatech's SPP-100 will work seamlessly > with any hardware or software that requires either an EPP or standard > parallel port for operation or for security dongles." Yep I read that - it should be sufficiently low-level. I've ordered one on that basis, but given those assurances I will have a reasonable case for returning it if it won't work with Impact. > at http://www.quatech.com/catalog/parallel_pcmcia.php. It's not > particularly cheap, though, considering that a parallel port is basically a > few buffers - $129 list. There may be other brands, too. Indeed, although it does need the PCMCIA interface stuff. And it's still 1/3 the price of a Multilinx cable! Thanks for your help. JohnArticle: 54365
Thanks for everyone's response. Our options are somewhat limited by having to use generic solutions since we are prototyping an ASIC chip. Even though DCM is a very attractive solution but it's out of our reach. What I'm always confused by is the I/O constraints. What does "OFFSET IN BEFORE" (and the Synopsys equivalent "set_input_delay") do? Will tools react to different setting of these constraints? I did not observe any changes when using different values for these constraints under Xilinx environment. I always seem to have understood the concept of these constraints when reading about them, but when it comes to applying them in real application, the result is not always what I was expecting. Could someone point me to the right direction for information in this regard? I really appreciate everyone's help. George "Brian Drummond" <brian@shapes.demon.co.uk> wrote in message news:eag59v4opdbgu2robn9raur88q5a3j8tjv@4ax.com... > On Mon, 7 Apr 2003 23:41:10 -0700, "George Fang" <gfang10@cox.net> > wrote: > > >Hi everyone, > > We are doing a project in which a Xilinx FPGA (2v1000-5) interface to a > >high speed chip providing data and clock. The data and the clock arrive at > >the FPGA pins at roughly the same time. The data skew is about 0.7 ns from > >the fastest pins to the slowest pins and the rising edge of the clock comes > >at about the middle of the skew range. The clock cycle is about 13ns. > > > I tried to specify the relationship between the data and the clock using > >"OFFSET IN BEFORE" and "OFFSET IN AFTER" constraints but the post P&R result > >did not indicate this had any expected effect. The rising edge of the clock > >always comes at the middle of the skew range at the register D pins > >resulting in unreliable data locking. > > Can someone explain the correct way of accomplishing this? Can the tools > >automatically take care of inserting delays to meet setup and hold timing? > > Not automatically, but I/O blocks have input delays selectable by user > constraints. Something like this, for each input you want to delay, in > the UCF file. > > NET "mynetname" IOBDELAY=IFD > > - BrianArticle: 54366
If you have the money do a training course preferably using the software tools you wish to use so that you know what you are doing when you get back to the office. You can easily get into bad habits without the proper training and this can cost you dearly in time. One way or another it will cost you in time or money or both so if you spent it spent it wisely. I've spent the most oweful year doing a design for a spartan II with only a week course on VHDL at a local uni but I now wish I had been trained on advanced features of high speed FPGA design. If you find any good value for money courses let me know. There is a world of difference between using CPLD's and FPGA's and I believe you need a good sound design management method to follow when designing for FPGA's, if your going to do it, do it right, whatever that means, Xilinx do there own training courses but I dont know how good they are, has anyone got any unbiased opinions.Article: 54367
What is the board doing that makes you believe its not normal, is it over currenting on any supplies, can you configure the spartan, are the pins tri-state before configuration - i.e. at what point in your testing do things go wrong?Article: 54368
Guys, We just bought Leonardo Spectrum from Mentor before the 31st of March to ensure that we would be eligible for the one off replacement to the new tool set Mentor is offering. Its my understanding but Leonardo Spectrum is no longer going to be continued by Mentor - and you can expect the price to shoot up radically for their offering. Perhaps this is why? We have played with Alteras "fixed" VHDL synthesis on their APEX devices ... it seems to stack up ok with Leonardo ... they have obviously put a lot of work into fixing as it was crap before. Hope it helps! "Kevin Brace" <kev0inbrac1eusen2et@ho3tmail.c4om> wrote in message news:b6lo6t$8kp$2@newsreader.mailgate.org... > Paul, > > When I saw Altera start using a new synthesis tool which they bought it > from Verific Design Automation (http://www.verific.com) since Quartus II > 2.1, I always wondered when Altera will drop the free license for > LeonardoSpectrum. > I don't mean to start an A vs. X argument here, if you don't like what > Altera did to you, why not switch to Xilinx? > Personally, I am fed up with Altera's backend solution because it has a > fatal flaw of renaming the LUT name, which makes the floorplanner > useless (For example, a LUT called ix_8160 gets renamed by the fitter as > ix_8160~0, and floorplan location assigned for ix_8160 will not apply to > the renamed LUT ix_8160~0.). > If someone knows how I can prevent the fitter from renaming the LUT, I > will like to hear, but so far I have tried a lot of things like turning > off various fitter options, and nothing has worked. > Anyhow, going back to the LeonardoSpectrum license issue, I personally > never like that tool because its buggy and hard to use GUI, but at least > it was able to generate an EDIF netlist. > > > Kevin Brace (If someone wants to respond to what I wrote, I prefer if > you will do so within the newsgroup.)Article: 54369
We have been using A mixture.. but an expensive one.. I use Quartus as my front end with Synplify pro and haven't had many problems.. I can't say its any faster or slow than Quartus's built in and I haven't seen it generate anything more 'LTU' efficient. Simulation is done with Model Sim.. worth the money in my view.. a simulation which takes 2 hours in Quartus takes less than a minute in model sim. I haven't found Quartus built in support for model sim very useful.. but as the Quartus is the web version (the budget was for xilinx even though all the designs were altera .. but I wasn't invited to that meeting) We also have some VHDL author tool.. (Author pro?) its very good (so I'm told) at managing VHDL libraries but I find it's not logical to my mind.. I'm used to dealing with projects not libraries. My software skills also tell me its dangerous to share libraries without checking what you are implementing .. also changing a library could cause a different project to fail for no reason.. maybe I'm old fashioned :-) We also have Leonardo but I think that was thrown in with the rest of the software.. I've been told its good as a back up but I haven't noticed any difference between Synplify and Leonardo. Our VHDL 'expert' swears by Synplify.. especially when you want to start going fast.. me he just swears at.. but then again .. I'm still learning this stuff. Simon "Lis Hu" <lishu99@yahoo.com> wrote in message news:4faf3f56.0304071140.2c053d3d@posting.google.com... > Now that Altera has announced discontinuation of LeonardoSpectrum, > I feel even more motivation to explore the alternatives. I plan > to do a signal processing intensive application on a Stratix, > and I wonder if anyone has any advice about the alternatives > to Leonardo. > > Personally, I had a heck of time with the Leonardo GUI crashing and > giving inconsistent results, and have just started scripting it. However, > all of that "bad experience" does not give me confidence about the tool. > > Even though the Altera Reps are starting to say Quartus has VHDL > support, there're constructs that it doesn't support. So as much > as I had hoped that I can use a single tool flow, it is not an option > at the moment. > > Synplify--I heard--is a faster tool? Any benchmarks out there? > > Precision RTL --I have never used. Would be interested to hear opinions. > > Thanks, > Lis HuArticle: 54370
Yes! That was the problem. I set the JTAG off by using the wrong pins in my design. Thanks a lot, Andreas Jennifer Jenkins <jennifer.jenkins@xilinx.com> wrote in message news:<3E932112.6B70FE5F@xilinx.com>... > Hi Andreas, > > The CoolRunner XPLA3 family allows the JTAG pins to multifunction as I/Os > (after configuration). I am guessing that you have programmed the part > that switches the JTAG pins to I/O pins. This would give you a warning > similar to the one you described below. Check out this application note > that describes how to reclaim the JTAG pins (see section "Port Enable > Pin")... > > http://www.xilinx.com/xapp/xapp343.pdf > > Hope this helps, > Jennifer > > Andreas Georgiou wrote: > > > Hello, > > > > I am using a Xilinx Coolrunner CPLD XCR3384. I test the board with > > some simple designs and it was working ok (using webpack 5.2 and > > iMPACT). > > > > Then I tried to load the entire design and it failed halfway while > > programming the CPLD. Since then, the CPLD cannot be detected by the > > software. Instead it says: > > "Communications with the cable could not be establish. Check the cable > > connections and cable power source" > > > > Other CPLDs are detected fine from the same software and same power > > supply. Also, I tired older versions of the webpack without success. > > > > It seems that I somehow "lock" the CPLD or configured it improperly so > > that I can do nothing to it now. If it is that, is there a simple way > > to erase it without taking it off the board? > > > > Thanks, > > > > AndreasArticle: 54371
This is a multi-part message in MIME format. --------------F08197AAF7D49B3C250497A1 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi all, I can in fact inform you that this will card will work with iMPACT. I use one myself on a Dell Latitude C400. You will need to set the following env. variable: XIL_IMPACT_ENV_LPT_BASE_ADDRESS=DFF8 or whatever your machine decides is the address of the PCMCIA card. Dave Jim Kearney wrote: > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message > news:b6vgbe$rmd$2@bunyip.cc.uq.edu.au... > > > There are PCMCIA parallel port cards available that provide 'normal' > > > hardware, like the Quatech SPP-100. > > Interesting idea. Can anyone confirm or deny this? :) > > All I can do is quote their data sheet: > > "Quatech's SPP-100 fully supports the IEEE 1284 EPP standard, and functions > exactly like a computer's native parallel port. Thus, unlike the many USB to > parallel converters on the market, Quatech's SPP-100 will work seamlessly > with any hardware or software that requires either an EPP or standard > parallel port for operation or for security dongles." > > at http://www.quatech.com/catalog/parallel_pcmcia.php. It's not > particularly cheap, though, considering that a parallel port is basically a > few buffers - $129 list. There may be other brands, too.Article: 54372
Hi, Can anyone tellme What will be average difference in max frequencies we get for pre layout(with gate level netlist) and post layout simulation for an asic. thanksArticle: 54373
Subroto, I've had trouble with the alias construct in VHDL. --Lis "Subroto Datta" <sdatta@altera.com> wrote in message news:<arLka.3748$UP3.2161@newssvr19.news.prodigy.com>... > Lis, > > Quartus II 2.2 has very good language coverage for both synthesizable > VHDL and Verilog. Please feel free to email me any questions about language > constructs, and we can verify if there will be a problem or not. > > - Subroto Datta > Altera Corp.Article: 54374
http://www.support.xilinx.com/support/services/education.htm Is a great place to start. As for Peter's comment: we get a number of "shills" or "decoys" that occasionally pop up here on the newsgroup. After some research in examining the URLs in the "view source" mode we find they are infantile attempts to annoy/spread lies/etc. As well, as we have said dozens of times, students are best served by those resources that are expressly there for their support, and to answer their questions. This newsgroup should (in my opinion) be for those folks with the real product problems and questions (all fpga vendors and customers). http://www.support.xilinx.com/univ/index.htm I know that there are many who do not share this view, but really, of what interest is more comments on the 6000 architecture? It died, let it rest in peace. Folks have products to get out, and paychecks to earn. Austin Ray Frost wrote: > If you have the money do a training course preferably using the > software tools you wish to use so that you know what you are doing > when you get back to the office. You can easily get into bad habits > without the proper training and this can cost you dearly in time. One > way or another it will cost you in time or money or both so if you > spent it spent it wisely. I've spent the most oweful year doing a > design for a spartan II with only a week course on VHDL at a local uni > but I now wish I had been trained on advanced features of high speed > FPGA design. If you find any good value for money courses let me know. > > There is a world of difference between using CPLD's and FPGA's and I > believe you need a good sound design management method to follow when > designing for FPGA's, if your going to do it, do it right, whatever > that means, Xilinx do there own training courses but I dont know how > good they are, has anyone got any unbiased opinions.
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