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Svjatoslav Lisin wrote: > Does somebody know any ready hardware systems for raytracing acceleration ? > How much can it cost? Hi, take a look at RenderDrive & PURE on www.artvps.com Best regards, MarkArticle: 54551
ART/PURE Render hardware? "Svjatoslav Lisin" <netbreaker666@mail.ru> wrote in message news:b7bh5l$b1t$1@news.wplus.spb.ru... > Does somebody know any ready hardware systems for raytracing acceleration ? > How much can it cost? > >Article: 54552
Svjatoslav Lisin wrote: > Does somebody know any ready hardware systems for raytracing acceleration ? > How much can it cost? Zip. Nothing. No graphics card can speed up raytracing, period. A graphics card speeds up the display if the program calls its built in primitives. Rendering programs do not call those primitives but rather are CPU intensive calculations of each pixel. -- 2003 March 14: Israel murders eleven Palestinians. -- The Iron Webmaster, 2576Article: 54553
I have an idea to implement all digital logic of my circuit into a CPLD. The only doubt is external UART. I know, additional UART is a big pain, currently I use tl16c750. I think that a price of external uart is the same or greater than an average CPLD chip. All IP cores suggested by google are complex, ie with FIFOs and flow control. I would be satisfied with the 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, RI flags and a hardwired frecuency. Any suggestions.Article: 54554
On Mon, 14 Apr 2003 00:39:50 GMT, Ken <tylereng@pacbell.net> wrote: >Video cards don't support hardware acceleration for raytracing. OpenGL, >movies and simple shading of polygons, yes, raytracing no. But they do support vertex and pixel shaders, which can be used for a lot of funky things, for instance: "Ray Tracing on Programmable Graphics Hardware" http://graphics.stanford.edu/papers/rtongfx/ (if it's down, try http://citeseer.nj.nec.com/purcell02ray.html) - AsbjørnArticle: 54555
Hi There, I am looking for a solution forcing a tristated bus-line to 1 (VCCIO) when it is in highZ state. I made a simple approach using a 330 Ohms pullup resistor to pull the line up to 3,3V when not driven. When the IO cell of my APEX FPGA drives the bus low, it can consume about -10 mA of IOL current. (flowing through my pullup into the FPGA, therefore 330Ohms is maximum pullup value) But in highZ state, it takes much to long until ti reaches VCCIO. Now my question: Is it possible to use an active termination to reach faster pullup functionality? Or would a pullup/pulldown combination be sufficient for that? thanks in advance best regards Chris.Article: 54556
On Mon, 14 Apr 2003 13:51:47 +0200, "Christian" <cw@nikocity.de> wrote: >Hi There, >I am looking for a solution forcing a tristated bus-line to 1 (VCCIO) when >it is in highZ state. >I made a simple approach using a 330 Ohms pullup resistor to pull the line >up to 3,3V when not driven. >When the IO cell of my APEX FPGA drives the bus low, it can consume >about -10 mA of IOL current. (flowing through my pullup into the FPGA, >therefore 330Ohms is maximum pullup value) >But in highZ state, it takes much to long until ti reaches VCCIO. >Now my question: Is it possible to use an active termination to reach faster >pullup functionality? Or would a pullup/pulldown combination be sufficient >for that? Does the bus have to be parked in high state? You might find that a week keeper (that retains the last state) is more effective than a pullup. Another option is to have the driving device drive the bus high for a brief period (perhaps 1/2 or 1 clock cycle) before going to Z. This is an old trick sometimes used on "ready" or "wait" or "dtack" signals on microprocessor peripherals. The pullup resistor is still needed, but it doesn't contribute to the rise time so its value doesn't matter. Allan.Article: 54557
> Does the bus have to be parked in high state? You might find that a > week keeper (that retains the last state) is more effective than a > pullup. > > Another option is to have the driving device drive the bus high for a > brief period (perhaps 1/2 or 1 clock cycle) before going to Z. This > is an old trick sometimes used on "ready" or "wait" or "dtack" signals > on microprocessor peripherals. The pullup resistor is still needed, > but it doesn't contribute to the rise time so its value doesn't > matter. > > Allan. Thank you for your quick and proper assistance, Allan!!! The bus currently is terminated by two clamping diodes and keeping value is not the problem. With my additional 330Ohms pullup, I wanted to create a recessive "1"-State, it is needed for a serial arbitration. Because of that, I don't know whether the trick with driving the bus hi for 1x TCLK will cause my arbitration to fail!? It seems I have to investigate on that.Article: 54558
"Ben Twijnstra" <bentw@SPAM.ME.NOT.chello.nl> writes: > Hi Petter, > > > The SOPC Builder is not officially supported under Linux yet. However, > > I can run the Java files distributed with the Solaris release under > > Linux (IBM jre 2.13). But I get a message saying that SOPC Builder > > requires an open Quartus II project. > > > > Is there a way to launch the SOPC Builder from within Quartus II or > > trick it to communicate with the Quartus II process? > > Not at this point. Even though it _should_ work (after all, it's Java), SOPC > Builder needs to connect to a Quartus server socket to query the current > project. As Quartus under Linux has no such socket open, at the moment I > can't think of a way to do this. It appears that this is possible using the -projectname and -projectpath options. However, the next problems it to specify at path to the local perl interpreter since the default is to use the SPARC version included with SOPC. Maybe it's better to wait for full Linux support. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54559
> A graphics card speeds up the display if the program calls its built in > primitives. Rendering programs do not call those primitives but rather > are CPU intensive calculations of each pixel. I didn't mean video card with 3D-Studio like program as a ready solution. I'm interested in ready system-on-chip which can accelerate the raytracing process. Software part (drivers, program like 3DS and so on) I can write by oneself.Article: 54560
Hello sir, Some doubts in PCI I will be greatful if you can clear it 12.why bus parking done only for AD,C/BE and PAR?why other signal donot need parking 13.Any idea about Prefetching???? for example Master initiate a read (burst read ,prefetech buffer 4 double word) at location 30000000 ,so data from 30000000 to 30000010 is fetched ? IS this true ? next address is whether 30000004 or 30000014? If it is 30000004 then data from 3000004 to 30000014 is fetched?Is this true? IF target side prefetch is disabled?what will happen? only one data is passed to the initiator side?Is this true? 14.what is the role of MAX_LAT in the configuration register? it is said that it specifies how often the device needs to gain access to the PCI Bus ?i didnot understand how often means what? can please give me example? 15.what is use of signal being of sustained tristate type? 16. How is cardbus specification related to PCI specification? 17. What do mean by "PCI device is embedded on the PCI bus "? 18. Why are 4 interrupt lines are provided one is enough whether it is because priority based i mean INTA has highest priority followed by INTB then INTC and INTD? 19. RST is a input in master who win reset the master? 20.what is this specific register-level programming interface in class code part of the configuration register? waiting for ur reply praveenArticle: 54561
> Hi, take a look at RenderDrive & PURE on www.artvps.com Wow, that's really cool and powerful system, but... This is not one chip, this is very huge box with lot of electronics :(Article: 54562
Christopher Fairbairn <ckf13@student.canterbury.ac.nz> wrote: : Hi, : I'm wondering if someone has managed to get the esential parts of Xilinx's : ISE WebPack 5.2i to run under WINE (or some other form of Win32 emulation) : under a Linux host and would be willing to provide advice/tips on doing it. A recent well configured wine with the prerequisited for Installshield 6 installers ( native stdole*.tbl) in the <wine>/windows directory should do the job. Installation will take some time ( wine directory handling in help/usenglish/newroot with it's 5499 files is not optimal) , show some errors and message box stacking may be wrong so that na "OK" buttom is hidden, but the installation should be useable. : A web search seems to suggest people have had success (there is even some : documentation on Xilinx's own website) and my initial attempts looks : promising... I think i've almost achieved my goal, however I'm increasingly : getting stuck. : I'm not particulary interested in the GUI related components (although : having as much of them as possible would be a benifit I suppose). : I'd be happly content with utilsing the command line applications directly, : and that's one of my problems... I don't even know where to start using : them. I've just recently started (i.e. a few months ago) using FPGAs and : have mainly used the GUI tools up until now, and relied upon them calling : the command line orientated ones. : For example using the tools in ISE WebPack, how would I go about getting a : VHDL file (say "XYZ.vhdl") synthesied and end up with an image ready for : use on say an Xilinx Spartan-II XC2S50. First run the GUI, set up a project and run the toolchain. After that, ISE has produced command files you may use in a script like this one for Verilog: export XILINX=l:\\webpack-5.2 /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/xst -quiet -ifn __projnav/pasamain.xst -ofn pasamain.syr /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/ngdbuild -quiet -dd h:\\work\\projekte\\alice\\pasa-astf\\fpga\\pasamain /_ngo -uc xilinx.ucf -aul -a -p xc2s200-pq208-5 pasamain.ngc pasamain.ngd /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/map -quiet -p xc2s200-pq208-5 -cm speed -detail -pr b -k 4 -c 100 -tx of f -o pasamain_map.ncd pasamain.ngd pasamain.pcf /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/par -w -ol 2 -t 1 -detail pasamain_map.ncd pasamain.ncd pasamain.pcf /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/bitgen -f pasamain.ut pasamain.ncd /spare/bon/wine/wine -- /spare/bon/webpack-5.2/bin/nt/impact -batch impact.cmd This script will not stop on arrors. Connecting the commands with "&&" should do that. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54563
Jim, Emile, Leon, Thanks all for your responses and good advice ! -rajeev-Article: 54564
I have some ready solutions for raytracing accelerator and now I'm looking for a project sponsor for finishing and distributing future chip (or ready IP). Future system will be faster and certainly chiper and smaller than the system at www.artvps.com. And theoretically it will be an AGP video card.Article: 54565
On Sat, 12 Apr 2003 07:58:03 -0700, Peter Wallace <pcw@karpy.com> wrote: > > Actually I'm designing such a card now, no microcontroller just a >FTDI USB245B and a 9572XL. Card is USB powered, about 1x3" and should work I must say this thought has crossed my mind a few times as well. I was thinking of using an 8-bit protocol where a state machine in the PLD looks for 'flag' and 'escape' characters similar to PPP to extract control words. It appears you can tap the USB245 oscillator for a 6MHz clock to run the PLD. > The 9572 can be programmed through the USB interface using the 245B's >bit banging mode. I can make PCBs available for a nominal charge if there >is any interest > If you use 3 bits of the USB port for the 9572, that only leaves 5 for the FPGA connection, crimping your style a bit :-) Is it worth it ? I guess so long as you leave the TMS high you can use 7 pins. >Still messing with ideas so any suggestions are welcome... > >PCW > Len ChisholmArticle: 54566
I'm planning to use the MAX8869 1Amp LDO from 3.3V, which I like because it uses ceramic caps and it has a power-good output. It's not available from D/K but I was able to obtain less than full reel direct from Maxim about 18 months ago (for an earlier project that never got built). Can somebody shed light on why power-up waveforms matter ? I mean, one might (naively ?) imagine that things would be OK so long as all the voltages settle down before configuration starts... Regards, -rajeev- ---------------- Eric Smith <eric-no-spam-for-me@brouhaha.com> wrote in message news:<qhel4kcosr.fsf@ruckus.brouhaha.com>... > I'm thinking about using a Linear Technology LTC3406B synchronous buck > regulator for the 2.5V core Vdd for an XC2S150. Has anyone else used > this? It's rated for 600 mA, so it should be able to handle the 500 mA <...>Article: 54567
"valentin tihomirov" <valentin@abelectron.com> ha scritto nel messaggio news:3e9a865c_2@news.estpak.ee... > I have an idea to implement all digital logic of my circuit into a CPLD. The > only doubt is external UART. I know, additional UART is a big pain, > currently I use tl16c750. I think that a price of external uart is the same > or greater than an average CPLD chip. All IP cores suggested by google are > complex, ie with FIFOs and flow control. I would be satisfied with the > 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, > RI flags and a hardwired frecuency. Any suggestions. I think a such non-programmable UART is very simple to implement and very inexpensive in terms of macrocells, likely less than 32.Article: 54568
the smallest device is XC3S50 without BlockRam. the largest device is XC3S5000 with 1,872K bits BlockRam. When will can get them?Article: 54569
Peter Alfke <peter@xilinx.com> wrote: : Jim Granville wrote: :> :> Then we know we have something in gestation..... :> Could it be twins ? :> Which trimester is the mother in ? : Definitely third trimester, and the baby is kicking a lot. Seems to be : really healthy... Congratulation as the birth of the baby is announced! (www.xilinx.com) When can we expect to see the baby in the kindergarten (that mean, when can we buy it at the distributors)? Cheers -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54570
On Mon, 14 Apr 2003 06:40:52 -0700, Len Chisholm wrote: > On Sat, 12 Apr 2003 07:58:03 -0700, Peter Wallace <pcw@karpy.com> wrote: >> >> Actually I'm designing such a card now, no microcontroller just a >>FTDI USB245B and a 9572XL. Card is USB powered, about 1x3" and should >>work > > I must say this thought has crossed my mind a few times as well. I was > thinking of using an 8-bit protocol where a state machine in the PLD > looks for 'flag' and 'escape' characters similar to PPP to extract > control words. It appears you can tap the USB245 oscillator for a 6MHz > clock to run the PLD. I thought of the state machine approach but decided that a simple address /data system would be fast enough and a lot simpler. This may change when I actually start implementing it :-) I didnt trust tapping the oscillator so I have a 24 MHZ oscillator for the CPLD, divided by 4 for the USB245. This also gets me higher shift rates or more finely controlled JTAG timing > >> The 9572 can be programmed through the USB interface using the 245B's >>bit banging mode. I can make PCBs available for a nominal charge if >>there is any interest >> >> > If you use 3 bits of the USB port for the 9572, that only leaves 5 for > the FPGA connection, crimping your style a bit :-) Is it worth it ? I > guess so long as you leave the TMS high you can use 7 pins. I was going to cheat and have a CPLD TMS jumper to allow programming, so that in the normal case (CPLD TMS tied high), all 8 USB bits were available... > >>Still messing with ideas so any suggestions are welcome... >> >>PCW >> >> > Len Chisholm PCWArticle: 54571
Valeria Dal Monte wrote: > "valentin tihomirov" <valentin@abelectron.com> ha scritto nel messaggio > news:3e9a865c_2@news.estpak.ee... > >>I have an idea to implement all digital logic of my circuit into a CPLD. > > The >>only doubt is external UART. I know, additional UART is a big pain, >>currently I use tl16c750. I think that a price of external uart is the > same >>or greater than an average CPLD chip. All IP cores suggested by google are >>complex, ie with FIFOs and flow control. I would be satisfied with the >>8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, > >>RI flags and a hardwired frecuency. Any suggestions. > > I think a such non-programmable UART is very simple to implement > and very inexpensive in terms of macrocells, likely less than 32. This may be impossible. A UART uses oversampling and taking the majority. For 8 databits plus 1 startbit and 1 stopbit at 4 times oversampling the shiftregister is 40 bits long. Add 2 bytes for transmission and 2 bytes for reception and you're at 64 bits. Then add a few macrocells for the logic. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 54572
Svjatoslav Lisin wrote: > Does somebody know any ready hardware systems for raytracing acceleration ? > How much can it cost? You'd need a geometry unit that calculates the traces, with refraction and reflection Then you'd need a scene manager that can sort the objects and find which are to be met by which ray. It appears to be more of a cpu job to me, once the geometry is done. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 54573
Svjatoslav Lisin wrote: > I have some ready solutions for raytracing accelerator and now I'm looking > for a project sponsor for finishing and distributing future chip (or ready > IP). Future system will be faster and certainly chiper and smaller than the > system at www.artvps.com. And theoretically it will be an AGP video card. > Multiposted to quite a number of groups ... That was quick. Just one day spent. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 54574
Check out these two reference designs from the Xilinx CPLD team: XAPP341: http://www.xilinx.com/xapp/xapp341.pdf XAPP345: http://www.xilinx.com/xapp/xapp345.pdf valentin tihomirov wrote: > I have an idea to implement all digital logic of my circuit into a CPLD. The > only doubt is external UART. I know, additional UART is a big pain, > currently I use tl16c750. I think that a price of external uart is the same > or greater than an average CPLD chip. All IP cores suggested by google are > complex, ie with FIFOs and flow control. I would be satisfied with the > 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, > RI flags and a hardwired frecuency. Any suggestions.
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