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rickman <spamgoeshere4@yahoo.com> wrote: : In the meantime, is there any info in the floorplanner for the 3S200, or : 3S400 device? Does the floorplanner show how many IO pins can be used? : I need a part with about 230 or more IOs. The 2S150 will do the job : well with 260 IOs in the FG456. I am looking for something like this. : My supply voltages have changed, so I am going to take a new look at the : Cyclone parts. But they seem to have the same power on surge as the 2S : Uwe. The ../spartan3/data directory doesn't contain package specific BSDL files for the xc3s200/400, so I guess things are not yet public. And I guess public availability is still many month from now for those parts. Bye -- Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54301
Ah, that is the trick... I am not using a single 409.6MHz clock but rather two 204.8MHz clocks with a well defined 180 degree phase shift. These drive two simultaneously enabled counters whose outputs are then summed after the final counts are obtained. It seems to work OK although I am getting some indication that the clock phases are not getting to the counters precisely when I would like them to. (The system has a tendency to generate even numbers slightly more often than odd numbers.) Theron Ray Frost wrote: > Sounds frightening, how will you get the 409.6 onto the global clock > routing resources?Article: 54302
Tan Peng Khiang wrote: > > Hello , recently i did a test on the coolrunner 2 , by having all ones > on the output when rising clock input is one and zeros when falling > clock input , i used the coolrunner2 's dualedge feature. > > The problem : i notice that all the output do not fall at the same time > , some outputs do match , but others don't match. > > Oscilloscope set to 1ns time step > Output as below: > > ----\ > 1 \ > \ > -------------------------- > ----\ > 2 \ > \ -------------------------- > > --------\ > 3->4 \ > \----------------------- > > ----\ > 5->9 \ > \ -------------------------- > > ---------\ > 10->16 \ > \ --------------------- > > It seems there is a difference in ralling time of difference output , is > there any ?? or is it a scope problem. > > Thanks in advance You can easily test if it is a scope problem by swapping probes. You can also check another device. All CPLDs will have different Tpd's for each the Outputs, what is under discussion is by how much. - ie by how many ps or ns. All the vendors promise is they lie inside the Min/MAX bounds, but usually they are much more closely grouped that that. On some tests I did (Atmel CPLD/SPLD), Tpd deltas were in the hundreds of ps to low ns regions. What exact delta is your scope showing ? -jgArticle: 54303
On Mon, 7 Apr 2003 18:49:26 +0000 (UTC), Uwe Bonnes wrote:
>rickman <spamgoeshere4@yahoo.com> wrote:
>
>: Does the floorplanner show how many IO pins can be used?
>: I need a part with about 230 or more IOs. The 2S150 will do the job
>: well with 260 IOs in the FG456.
>
>The ../spartan3/data directory doesn't contain package specific BSDL files
>for the xc3s200/400, so I guess things are not yet public.
There is enough data in that directory to guess pretty well, though.
The xc3s1000_fg456, like the xc3s1000, has 333 user I/O on pads.
For xc3s200 and xc3s400, the counts are both 328. Although, the
comments in those files say "This file is a dummy BSLD file created
by Pushpasheel Tawade on 04/04/02 for xc3s[24]00", and later on in
that file it refers to "entity XC3S50 is" "generic (PHYSICAL_PIN_MAP
: string := "BG575" );".
Does anybody outside of Xilinx know how to read .nph or .grf files?
>And I guess public availability is still many month from now for those
>parts.
I'm not holding my breath. I'm still blue from the Spartan2 delivery
delays. An XC3S400 would be very interesting to me, especially if
supported by the WebPACK, and in-stock at Digi-Key.
- Larry
Article: 54304Now that Altera has announced discontinuation of LeonardoSpectrum, I feel even more motivation to explore the alternatives. I plan to do a signal processing intensive application on a Stratix, and I wonder if anyone has any advice about the alternatives to Leonardo. Personally, I had a heck of time with the Leonardo GUI crashing and giving inconsistent results, and have just started scripting it. However, all of that "bad experience" does not give me confidence about the tool. Even though the Altera Reps are starting to say Quartus has VHDL support, there're constructs that it doesn't support. So as much as I had hoped that I can use a single tool flow, it is not an option at the moment. Synplify--I heard--is a faster tool? Any benchmarks out there? Precision RTL --I have never used. Would be interested to hear opinions. Thanks, Lis HuArticle: 54305
Rick, Spartan IIE on 300 mm has roughly 1/5 the original peak current spike that Virtex E had. and if you don't supply it (and only supply the minimum in the data sheet) it powers on cleanly. Austin rickman wrote: > Ian Young wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote: > > > > >The Webpack does not have a chip editor. > > > > It does have a floorplanner, but I'm not sure how much to trust it in > > this case. If you run a simple design through on the only 5.2i > > WebPACK-supported Spartan-3 device (3S50) you can see a device with a > > Virtex-2 style of CLB layout, but with an apparent complete lack of > > DCMs, BRAMs and multipliers. It does seem to have about 3x the CLBs > > of the 2V40, though, if I'm counting correctly. > > > > I'm not sure I believe that, but as long as we're in rampant > > speculation mode... > > > > Obviously even if the above is true, it doesn't imply the whole family > > will be like this; it may just be the teeniest one that's just "all > > CLBs". > > I have not downloaded the current webpack since it is such a large > download. At one time you could get Insight to send you a CD, but they > don't even anwser their emails at this point. I am finding that when it > comes to doing anything other than giving you a link to click, most > vendors are becoming very lame when it comes to customer support. I > would rant on, but I really am trying to get a little info on these > parts... :) Just don't mention the name Sharp to me, ok? > > I will try to download Webpack tonight and let it crank for the 10 to 15 > hours it will take over this modem link. > > In the meantime, is there any info in the floorplanner for the 3S200, or > 3S400 device? Does the floorplanner show how many IO pins can be used? > I need a part with about 230 or more IOs. The 2S150 will do the job > well with 260 IOs in the FG456. I am looking for something like this. > > My supply voltages have changed, so I am going to take a new look at the > Cyclone parts. But they seem to have the same power on surge as the 2S > parts. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54306
lishu99@yahoo.com (Lis Hu) writes: > Synplify--I heard--is a faster tool? Any benchmarks out there? Some of the license agreements from the EDA vendors prevent you from disclosing benchmark results. However, they usually give you a 30 day evaluation license so you can try for yourself. Just make sure you request the license when you have time to evaluate the tool. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54307
rickman <spamgoeshere4@yahoo.com> wrote: >I will try to download Webpack tonight and let it crank for the 10 to 15 >hours it will take over this modem link. > >In the meantime, is there any info in the floorplanner for the 3S200, or >3S400 device? Does the floorplanner show how many IO pins can be used? The WebPACK only supports the 3S50; so, maybe you don't need to do the big download after all. -- IanArticle: 54308
I think we at Xilinx appreciate the wide interest in Spartan-3, but please hold your speculation until we officially announec the product. The parents should announce the birth of the baby, not somebody who saw the ultra-scan. Peter Alfke > >Article: 54309
Hi , Has anybody in this group used Virtual Computing Corporation(VCC)'s HOT 2 board and development tools. Are there any issues I should look out for in interfacing their board to a SUN Solaris workstation through a PCI bus,or as they claim can I create Hardware Objects ,use them as function calls in C++ code and not worry about any problems with the interface part. Thanks, SriramArticle: 54310
Peter Alfke <peter@xilinx.com> wrote: : I think we at Xilinx appreciate the wide interest in Spartan-3, but : please hold your speculation until we officially announec the product. : The parents should announce the birth of the baby, not somebody who saw : the ultra-scan. But when the parents post the Ultra-scans on the blackboard... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 54311
Uwe Bonnes wrote: > > Peter Alfke <peter@xilinx.com> wrote: > : I think we at Xilinx appreciate the wide interest in Spartan-3, but > : please hold your speculation until we officially announec the product. > : The parents should announce the birth of the baby, not somebody who saw > : the ultra-scan. > > But when the parents post the Ultra-scans on the blackboard... Then we know we have something in gestation..... Could it be twins ? Which trimester is the mother in ? :) jgArticle: 54312
Jim Granville wrote: > > Then we know we have something in gestation..... > Could it be twins ? > Which trimester is the mother in ? Definitely third trimester, and the baby is kicking a lot. Seems to be really healthy... Peter >Article: 54313
Garrett Mace wrote: > "John Williams" <jwilliams@itee.uq.edu.au> wrote in message >>Most miniature laptops these days don't have an LPT port, so I'm >>wondering if anybody knows whether you can use after-market USB->LPT >>adaptors with the Xilinx parallel cable and programming software? >> >>Anybody had success in this regard? Can you tell me which USB->LPT >>adaptor you used? > > Haven't tried them, but I *think* they will work. They should just look like > any other LPT port. It depends how low level the Xilinx parallel drivers are operating. I've found other threads where people have had problems with add-on PCI parallel ports, so I'm not too optimistic about using a USB-LPT converter. Can anyone explain the order of magnitude price difference between the parallel cable and the multilinx cable (US$ 50 vs US $500)? Seems a bit rich to me... > Slightly offtopic, but I'd like a laptop marketed specifically to EE's: [snip] Yeah interesting idea. would be lots of fun to put one together, and you'd probably sell about 10. Perhaps more useful would be a PCMCIA "suite" of EE-specific tools, and a way to chain them together. Cheers, JohnArticle: 54314
Hi everyone,
We are doing a project in which a Xilinx FPGA (2v1000-5) interface to a
high speed chip providing data and clock. The data and the clock arrive at
the FPGA pins at roughly the same time. The data skew is about 0.7 ns from
the fastest pins to the slowest pins and the rising edge of the clock comes
at about the middle of the skew range. The clock cycle is about 13ns.
My questions is how can we reliably lock the data in to the FPGA. An
intuitive answer is to use the falling edge of the clock to lock the data
into registers but I was told by some designer that this does not agree with
the philosophy of "fully synchronous design", that we should stay with the
rising edge but use proper constraints to let tool take care of the delay
matching.
I tried to specify the relationship between the data and the clock using
"OFFSET IN BEFORE" and "OFFSET IN AFTER" constraints but the post P&R result
did not indicate this had any expected effect. The rising edge of the clock
always comes at the middle of the skew range at the register D pins
resulting in unreliable data locking.
Can someone explain the correct way of accomplishing this? Can the tools
automatically take care of inserting delays to meet setup and hold timing?
Would it be different if the data source and the design currently in FPGA
are all in the same ASIC chip?
Thanks in advance for any info.
George
Article: 54315I'm using a 300mA CMOS high performance LDO AAT3236 from Analogic Tech. It has 500mA peak current that is enought for the startup of the spartan II. It works very well and is cheaper. Same component for the 3.3V. The only very wrong thing is that they are only on 3000pc reel :-(((( Bye Giuseppe "Eric Smith" <eric-no-spam-for-me@brouhaha.com> ha scritto nel messaggio news:qhel4kcosr.fsf@ruckus.brouhaha.com... > I'm thinking about using a Linear Technology LTC3406B synchronous buck > regulator for the 2.5V core Vdd for an XC2S150. Has anyone else used > this? It's rated for 600 mA, so it should be able to handle the 500 mA > required current at power-on (and my application will need less than > that when operating), but I'm concerned about whether the ramp will be > too fast, too slow, non-monotonic, or otherwise make the FPGA unhappy. > > It's not too expensive, and requires few external components. Since it > operates at 1.6 MHz, it can use a very small inductor. > > Thanks, > EricArticle: 54316
Hi - Using the falling clock edge may violate the "fully synchronous design" philosophy of using one edge for everything, but it's a lot better than trying to engineer on-chip delays that slide the data relative to the clock. Do a timing analysis to convince yourself that falling edge clocking will work, being sure to take into account the effect of things like non-ideal clock duty cycle. If the numbers look good, use the falling edge. If for some reason the falling edge won't work timing-wise, you could always delay the clock by lengthening its PCB trace. PCB trace delays are pretty stable; if the trace is stripline (i.e., embedded between two planes), the delay is a function of the dielectric constant only, not the trace geometry. But to delay it half a clock cycle would take about a 3 foot trace in FR-4. That doesn't sound terribly appealing to me. If the data source and destination were in the same chip, be it FPGA or ASIC, you'd probably use a low-skew clock tree to distribute clocks to both the driving and receiving registers, instead of using the source-synchronous scheme you've described. Bob Perlman Cambrian Design Works On Mon, 7 Apr 2003 23:41:10 -0700, "George Fang" <gfang10@cox.net> wrote: >Hi everyone, > We are doing a project in which a Xilinx FPGA (2v1000-5) interface to a >high speed chip providing data and clock. The data and the clock arrive at >the FPGA pins at roughly the same time. The data skew is about 0.7 ns from >the fastest pins to the slowest pins and the rising edge of the clock comes >at about the middle of the skew range. The clock cycle is about 13ns. > My questions is how can we reliably lock the data in to the FPGA. An >intuitive answer is to use the falling edge of the clock to lock the data >into registers but I was told by some designer that this does not agree with >the philosophy of "fully synchronous design", that we should stay with the >rising edge but use proper constraints to let tool take care of the delay >matching. > I tried to specify the relationship between the data and the clock using >"OFFSET IN BEFORE" and "OFFSET IN AFTER" constraints but the post P&R result >did not indicate this had any expected effect. The rising edge of the clock >always comes at the middle of the skew range at the register D pins >resulting in unreliable data locking. > Can someone explain the correct way of accomplishing this? Can the tools >automatically take care of inserting delays to meet setup and hold timing? >Would it be different if the data source and the design currently in FPGA >are all in the same ASIC chip? > > Thanks in advance for any info. > >George >Article: 54317
Your problem might be due to U2 dll as it uses clk0_out on clkfb input, clk0 is loaded more than clk180 so this could be a problem, I steer away from this as I had problems when I tried similar. You could try using clkdll and select clk90 & clk270. I take it you are waiting until the dll's are locked before using your generated clocks. How are reset_counter & reset_counter_delayed signals used?Article: 54318
Use chipscope to make sure about the mapping of your dual FFD and your output, Your trouble can be come from a different P&R of your output. Let me know, I am interested in this issue. Laurent Gauch www.amontec.com Tan Peng Khiang wrote: > Hello , recently i did a test on the coolrunner 2 , by having all ones > on the output when rising clock input is one and zeros when falling > clock input , i used the coolrunner2 's dualedge feature. > > The problem : i notice that all the output do not fall at the same time > , some outputs do match , but others don't match. > > Oscilloscope set to 1ns time step > Output as below: > > ----\ > 1 \ > \ > -------------------------- > ----\ > 2 \ > \ -------------------------- > > --------\ > 3->4 \ > \----------------------- > > ----\ > 5->9 \ > \ -------------------------- > > ---------\ > 10->16 \ > \ --------------------- > > It seems there is a difference in ralling time of difference output , is > there any ?? or is it a scope problem. > > Thanks in advanceArticle: 54319
Hello! I am trying to find the Hammond FPGA board from Embedded
Solutions Ltd with Xilinx's XC4028XLA HQ160 FPGA. Does anyone knows where I
can find more information and prices about it? Thank you very much for your
time!
Regards,
Dimitris
Article: 54320Jim Granville wrote: > > Tan Peng Khiang wrote: > > > > Hello , recently i did a test on the coolrunner 2 , by having all ones > > on the output when rising clock input is one and zeros when falling > > clock input , i used the coolrunner2 's dualedge feature. > > > > The problem : i notice that all the output do not fall at the same time > > , some outputs do match , but others don't match. > > > > Oscilloscope set to 1ns time step > > Output as below: > > > > ----\ > > 1 \ > > \ > > -------------------------- > > ----\ > > 2 \ > > \ -------------------------- > > > > --------\ > > 3->4 \ > > \----------------------- > > > > ----\ > > 5->9 \ > > \ -------------------------- > > > > ---------\ > > 10->16 \ > > \ --------------------- > > > > It seems there is a difference in ralling time of difference output , is > > there any ?? or is it a scope problem. > > > > Thanks in advance > > You can easily test if it is a scope problem by swapping probes. > You can also check another device. > > All CPLDs will have different Tpd's for each the Outputs, what is > under discussion is by how much. - ie by how many ps or ns. > > All the vendors promise is they lie inside the Min/MAX bounds, but > usually they are much more closely grouped that that. > > On some tests I did (Atmel CPLD/SPLD), Tpd deltas were in the hundreds > of ps > to low ns regions. > > What exact delta is your scope showing ? > > -jg Hello , jim , thanks for the reply . Currently from the scope i can see something like 1ns , sometimes there can be afew outputs falling in synchronous, when some other pins has 1ns delay. BTW: it does seems that i am not the only one having this effect. Here is another query i have: Since the falling edge of output pins are not in synchronous , if the setup and hold time of the data clocking clock is not violated , things will still work. Is my statement correct ? Thanks in advance.Article: 54321
Laurent Gauch, Amontec wrote: > > Use chipscope to make sure about the mapping of your dual FFD and your > output, Your trouble can be come from a different P&R of your output. > > Let me know, I am interested in this issue. > > Laurent Gauch > www.amontec.com > > Tan Peng Khiang wrote: > > > Hello , recently i did a test on the coolrunner 2 , by having all ones > > on the output when rising clock input is one and zeros when falling > > clock input , i used the coolrunner2 's dualedge feature. > > > > The problem : i notice that all the output do not fall at the same time > > , some outputs do match , but others don't match. > > > > Oscilloscope set to 1ns time step > > Output as below: > > > > ----\ > > 1 \ > > \ > > -------------------------- > > ----\ > > 2 \ > > \ -------------------------- > > > > --------\ > > 3->4 \ > > \----------------------- > > > > ----\ > > 5->9 \ > > \ -------------------------- > > > > ---------\ > > 10->16 \ > > \ --------------------- > > > > It seems there is a difference in ralling time of difference output , is > > there any ?? or is it a scope problem. > > > > Thanks in advance Thanks Laurent , i will try it out and keep you inform. Thanks for reply.Article: 54322
Tan Peng Khiang wrote:
>
> Jim Granville wrote:
> >
> > Tan Peng Khiang wrote:
> > >
> > > Hello , recently i did a test on the coolrunner 2 , by having all ones
> > > on the output when rising clock input is one and zeros when falling
> > > clock input , i used the coolrunner2 's dualedge feature.
> > >
> > > The problem : i notice that all the output do not fall at the same time
> > > , some outputs do match , but others don't match.
> > >
> > > Oscilloscope set to 1ns time step
> > > Output as below:
> > >
> > > ----\
> > > 1 \
> > > \
> > > --------------------------
> > > ----\
> > > 2 \
> > > \ --------------------------
> > >
> > > --------\
> > > 3->4 \
> > > \-----------------------
> > >
> > > ----\
> > > 5->9 \
> > > \ --------------------------
> > >
> > > ---------\
> > > 10->16 \
> > > \ ---------------------
> > >
> > > It seems there is a difference in ralling time of difference output , is
> > > there any ?? or is it a scope problem.
> > >
> > > Thanks in advance
> >
> > You can easily test if it is a scope problem by swapping probes.
> > You can also check another device.
> >
> > All CPLDs will have different Tpd's for each the Outputs, what is
> > under discussion is by how much. - ie by how many ps or ns.
> >
> > All the vendors promise is they lie inside the Min/MAX bounds, but
> > usually they are much more closely grouped that that.
> >
> > On some tests I did (Atmel CPLD/SPLD), Tpd deltas were in the hundreds
> > of ps
> > to low ns regions.
> >
> > What exact delta is your scope showing ?
> >
> > -jg
> Hello , jim , thanks for the reply .
>
> Currently from the scope i can see something like 1ns , sometimes there
> can be afew outputs falling in synchronous, when some other pins has 1ns
> delay.
>
> BTW: it does seems that i am not the only one having this effect.
>
> Here is another query i have:
>
> Since the falling edge of output pins are not in synchronous , if the
> setup and hold time of the data clocking clock is not violated , things
> will still work. Is my statement correct ?
>
> Thanks in advance.
Here is the simple program used for testing
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity delay_test is
Port ( CLK_IN : in std_logic;
CLK_OUT : out std_logic_vector(15 downto 0));
end delay_test;
architecture Behavioral of delay_test is
begin
process(CLK_IN)
begin
if CLK_IN = '1' then
CLK_OUT <= "1111111111111111";
else
CLK_OUT <= "0000000000000000";
end if;
end process;
end Behavioral;
Thanks
Have a nice day
Article: 54323On Mon, 7 Apr 2003 23:41:10 -0700, "George Fang" <gfang10@cox.net> wrote: >Hi everyone, > We are doing a project in which a Xilinx FPGA (2v1000-5) interface to a >high speed chip providing data and clock. The data and the clock arrive at >the FPGA pins at roughly the same time. The data skew is about 0.7 ns from >the fastest pins to the slowest pins and the rising edge of the clock comes >at about the middle of the skew range. The clock cycle is about 13ns. > I tried to specify the relationship between the data and the clock using >"OFFSET IN BEFORE" and "OFFSET IN AFTER" constraints but the post P&R result >did not indicate this had any expected effect. The rising edge of the clock >always comes at the middle of the skew range at the register D pins >resulting in unreliable data locking. > Can someone explain the correct way of accomplishing this? Can the tools >automatically take care of inserting delays to meet setup and hold timing? Not automatically, but I/O blocks have input delays selectable by user constraints. Something like this, for each input you want to delay, in the UCF file. NET "mynetname" IOBDELAY=IFD - BrianArticle: 54324
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:b6qmgt$jfn$1@bunyip.cc.uq.edu.au... > Hi folks, > > I'm looking into getting a laptop primarily for admin stuff, but it > would be nice to be able to use it for demos etc, which means using the > Xilinx parallel cable to program my boards etc. > > Most miniature laptops these days don't have an LPT port, so I'm > wondering if anybody knows whether you can use after-market USB->LPT > adaptors with the Xilinx parallel cable and programming software? > > Anybody had success in this regard? Can you tell me which USB->LPT > adaptor you used? > > Thanks, > > John Between about 4 people none of us has managed to get a usb to parallel port adaptor working as advertised. Work for printers but that is about it. Can't even program a pic through the ones I've tried. Haven't tried a xilinx cable. Laptops I'm a big fan of the Compaq EVO 400C. Had one for a year. Bit limited for graphics but can't beat the weight. 1.58 kg Current model is 410C http://h50025.www5.hp.com/hpcom/au_en/11_28_62.html http://h50025.www5.hp.com/hpcom/au_en/11_28_62_261_272.html Usually cheaper to buy from a reseller than direct from Compaq. In Sydney(Australia) cworld.com.au is usually one of the cheapest. They don't have a Brisbane store yet. (Your at the Brisbane Campus ?) If you can wait a month or more until the new Intel chip(Banias) starts coming out should be some decent price cuts. Alex
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