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> It's only a matter of time before you write an AutoLISP application that
> lets you *generate code* by drawing various *lines and shapes* in some
> alien-looking structure. Like a circle becomes a loop, and objects
> intersecting the circle take on different functions, it would be like
> generating LOGO code from watching the turtle...I'd best not give you
ideas
> that can waste considerable amounts of your time.
Funny you should say that ... I've done just that in the past for other (non
programming) applications where a symbolic description gets to the point
quickly. AutoCAD/AutoLISP is quite powerful in that regard. When I get
some time I'm going to learn ObjectARX which takes it one step farther.
Another thought I had was that of ASCII (or text) based programming being an
outmoded modality. Back in college I was fortunate enough to have a Physics
professor who was hell-bent for a language called APL. He made a deal with
the CS department to allow students to take an APL class he concocted
instead of FORTRAN77 and get equivalent credit. I was one of those
students.
Many describe APL as hieroglyphics because it uses various symbols to
represent functions and concepts. Ken Iverson created APL back in the early
60's at IBM to describe the IBM360's hardware ... interestingly enough. So,
I've often wondered if the APL approach could be taken for a
"next-generation" HDL. I really think symbols are incredibly powerful ...
think of mathematics, if you had to use the word "integral" in place of the
stretch "S" shape, for example. I've seen some threads complaining about
such things as the "begin" and "end" tokens in Verilog and asking if they
could be replaced with the C-style "{ }" braces.
Extending the use of something like Excel to generate code could be an
interesting interim apprach. Geometric (limited to rows and columns, of
course) relationships could be exploited to denote parallelism,etc.
Just thinking out loud.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian
To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_" = "martineu"
Article: 54126"Stan Lackey" wrote > Have a look at verilog-mode for emacs. I have it running both on my PC at > home and on the 'nix machine in the office. Its capabilities overlap some > of what you're doing but it has a long list of other capabilities. Do a > search for "emacs verilog mode". -Stan I'll look into it. Thanks. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 54127
ad.rast.7@nwnotlink.NOSPAM.com (Alex Rast) wrote in message news:<93499217Eadrastnwnotlinkcom@216.168.3.44>... > http://www02.so-net.ne.jp/~morioka/cqpic.htm > > Supposedly a PIC16F84 implementation in VHDL. Version 1.00b appears to be > downloadable on the site. But when I click the link, I get the following: > > "Forbidden > You don't have permission to access /fb3/morioka/pic100a/cqpic100b.exe on > this server." > > i.e. the standard no-access message. Are others running into this? If so, > is there some other location from which I can download? Or is it somehow > something in my environment that I need to change in order to download > successfully? There are various PIC cores available for free download from www.opencores.org Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 54128
Hi to everyone. Has anybody ever seen a CoolRunner freezing? I mean, theXCR128 I am using on a StrongARM board, every time and again after a board reset goes in a state which is nor un-programmed neither functional (I/Os at random output values, internal circuitry not responding).1 I cannot blame the internal design, because the circuitry is simply a battery of registers and some combinatorial functions; no clock is used. Successive resets don't recover the situation; if the power is unplugged till all capacitors and backup battery are discharged, the CPLD restores its functionality, no need to reprogram. I was thinking about the device entering in some JTAG internal state machine, but with the oscilloscope I couldn't see strange sequences on the JTAG inputs; moreover, these inputs are pull-upped as suggested by data-sheets. The Italian technical support suggested power voltage drops, but I couldn't see them either. Any suggestion? Thank you all.Article: 54129
Mike Treseler <tres@fluke.com> writes: > Petter Gustad wrote: > > > Is there a variable set by cmp start which I can vwait on? > > It's not hard to make one. > > For an example, make an exception to your rule and bring up GUI: > > File, New, Other, Tcl Script, OK > Edit, Insert Template, QuartusII tcl, Compile. This results in the same code as given in AN195. If you are command line mode it will be a tight loop around a FlushEventQueue (which is what I'm doing currently). I want to avoid such loops. If cmp start changed some variable one could maybe do something like: cmp start compile vwait formagicvariablesetbycmpstart Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 54130
khimbittle@cliftonREMOVEsystems.com (Khim Bittle) wrote in message news:<3e87b820.8088935@news.compuserve.com>... > hello folks ... while tooling around the arrow site this evening > doing some price comparisons ... I noticed that altera has million > gate plus FPGA's that are priced in the $2000-4000 range , holly geeze > !! , yes I know a "good price or volume price " is certainly lower ... > but does anyone outside of perhaps the military actually buy and build > product with FPGA's that cost a couple of grand ?? just curious ... > my designs are always under such cost pressure that part prices much > over 100 bucks is difficult to use ... thanks for the enlightenment .. > KB Don't mean to beat a dead dog ... there are certainly lots of good reasons to use the big and expensive FPGAs, time to market probably being the strongest argument for them. However, all the arguments for low volume devices, should take a look at Multi Project Waver (MPW) runs (sometimes also called Shuttle runs). These processes will give you low volume devices (ASICSs) at a fraction of the full NRE. There is no easy way to universally tell what would be more economical, as many, many different factors influence the final device cost on a MPW run. But it's sure worth a look. Best Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 54131
Hi, Does anyone have experience with VHDL tool suppport for bit vectors (or vectors of other types) that have lots of elements? I'm thinking of using one for a generic or a constant (not a signal) to hold the initialisation value for a Xilinx block ram (18432 bits). I'm interested in both simulation and synthesis. Thanks, Allan.Article: 54132
On Thu, 03 Apr 2003 17:33:33 +1000, Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote: >Hi, > >Does anyone have experience with VHDL tool suppport for bit vectors >(or vectors of other types) that have lots of elements? > >I'm thinking of using one for a generic or a constant (not a signal) >to hold the initialisation value for a Xilinx block ram (18432 bits). > >I'm interested in both simulation and synthesis. Oops. I forgot to say that I have arrays of block rams, and the vector will need to have up to several hundred thousand bits. Thanks, Allan.Article: 54133
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3E887532.31FE90B4@xilinx.com>... ... > > Now we are talking about even less money for 1M+ gates in 90 nm. > > ASICs are all but dead except for those really big jobs that can afford the > $80M++ price tag to develop them. Or those jobs where low current is required > (ie cell-phones). Wait a minute ! This absolute nonsense ! You can not generalize that is costs $80M++ to develop an ASIC. This absolutely not true. I would believe an isolated case for some very special mixed signal ASIC to may be really, really expensive to develop and produce, but $80M is a really far out ! Certainly comparing the development of an 90nm ASIC to an FPGA is quite unrealistic. The performance, power consumption and size I get from a 90 nm custom ASIC will be far better than that from a FPGA, even though it was produced in a 90nm process. > Even televisions don't sell enough to afford some of the new ASIC pricetags. > Think about it. An "appliance" doesn't sell in large enough volume to have > its own ASIC. Of course - it is a price driven market, if a of the shelf part will do the job and the price is right, why not ? Many chip makers target these areas and offer solutions that integrate very well. However, I am not aware of an TV in production using FPGAs. > The recent EETimes article on IP at these geometries was especially telling. > Integration of IP at 130 nm and 90nm is a hightmare......etc. etc. etc. The > 80M$ figure above was from that article. > > So 'cheap' ASICs are stuck at 180nm (and above). But with 90nm FPGAs we are > three or more techology steps ahead (.15, .13, .09), and that makes us a > better deal. Yes, IP for smaller geometries are expensive. I'm not sure how FPGAs can cure that problem. Many IPs are not available for FPGAs, specifically analog or high speed IP cores like PHYs and ADCs. Many IPs are also becoming freely available, both for ASICs and FPGAs. Check out out web site for example. > Austin Quite honestly I doubt the ASIC market is as depressed as FPGA vendors would like it to be. It is certainly far from being dead (or dying). Sure, it is expensive to manufacture ASICs and the currently depressed overall economy makes it even tougher for ASIC designers. However, I don't see any less work in the front-end design cycle between FPGAs and ASICs. I actually do find ASIC tools to be much more developed and advanced compared to FPGA tools. Just take a look at Xilinx own synthesis and P&R software ... Best Regards, rudi ------------------------------------------------ www.asics.ws - Solutions for your ASIC needs - FREE IP Cores --> http://www.asics.ws/ <--- ----- ALL SPAM forwarded to: UCE@FTC.GOV -----Article: 54134
Hello folks, I am working on a legacy design for a Spartan xcs10vq100-3. We have the old bitstreams (there are two devices and the bitstreams get combined into one then downloaded together via some sort of daisy-chain arrangement) and they work just fine. Problem is, a modification is required for one of the bitstreams - and all the people that were involved in the original project have left.... :-) I have the original VHDL and the idea was to get this to work via the Xilinx ISE 4.1 tools and then make the modification to the VHDL and all will be good! However, the UCF file I have only contains clock period specifications - no OFFSET specs. to define the input and output timings. When I run the VHDL through the tools, there are no errors and the clock period specs. are met by the whole design (some parts actually run much slower than the 38MHz master clock). The resulting bitstream gives errors once in operation - something is happening but the signals are not quite right. The Spartans are on a board and are interfacing with other chips/devices. The VHDL has not been modified and I am fairly sure it is all correct. Do you think this could be down to no OFFSET timing constraints? How important are they - are they always required or is it possible to interface an fpga with other chips on a board without specifying OFFSET constraints if the design runs at the right rate? Thanks for your time, KenArticle: 54135
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:JMGia.1$xs3.12763300@newssvr14.news.prodigy.com... [me] > > Any special reason for choosing the async write? I know it's > > conceptually easier, but I've always found it was less pain > > in the long run to stay synchronous where possible (and you > > clearly *can* stay synchronous in this case). [Martin] > Well. Yes, but, in retrospect, none firm enough not to consider a > synchronous solution. I just wanted to mimic the way a typical > microprocessor interfaceable chip works (something like an 8255 PIO or 2691 > UART). Most of these appear to have a non-synchronous interface to the uP > and probably synch internaly upon utilization of the register data. Others have thrown their weight behind a synchronous solution, but perhaps I can just point out that both the peripheral parts you mention are 25+ year old designs... the world has moved on a tad. Synthesis and FPGAs both encourage synchronous design techniques, and there's little tool support for asynchronous methodologies. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 54136
Look at the supply voltages across the device pins during power-up. If you have anything but a smooth monotonic rise, expect problems ! Dave "Iode" <d_demaio@hotmail.com> wrote in message news:b6gm3b$600$1@fata.cs.interbusiness.it... > > Hi to everyone. > > Has anybody ever seen a CoolRunner freezing? I mean, theXCR128 I am using on > a StrongARM board, every time and again after a board reset goes in a state > which is nor un-programmed neither functional (I/Os at random output values, > internal circuitry not responding).1 I cannot blame the internal design, > because the circuitry is simply a battery of registers and some > combinatorial functions; no clock is used. > > Successive resets don't recover the situation; if the power is unplugged > till all capacitors and backup battery are discharged, the CPLD restores its > functionality, no need to reprogram. > > > > I was thinking about the device entering in some JTAG internal state > machine, but with the oscilloscope I couldn't see strange sequences on the > JTAG inputs; moreover, these inputs are pull-upped as suggested by > data-sheets. > > The Italian technical support suggested power voltage drops, but I couldn't > see them either. > > > > Any suggestion? > > > > Thank you all. > > >Article: 54137
Jonathan Bromley wrote: > [Martin] > > Well. Yes, but, in retrospect, none firm enough not to consider a > > synchronous solution. I just wanted to mimic the way a typical > > microprocessor interfaceable chip works (something like an 8255 PIO or > 2691 > > UART). Most of these appear to have a non-synchronous interface to the uP > > and probably synch internaly upon utilization of the register data. > > Others have thrown their weight behind a synchronous solution, but > perhaps I can just point out that both the peripheral parts you > mention are 25+ year old designs... the world has moved on a tad. > Synthesis and FPGAs both encourage synchronous design techniques, > and there's little tool support for asynchronous methodologies. That's one heck of a way to date myself isn't it!!! At least nobody (yet) suggested a Carbon-14 age test! :-) Thanks, ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Martin Euredjian To send private email: 0_0_0_0_@pacbell.net where "0_0_0_0_" = "martineu"Article: 54138
Hi does anyone have any opinions or comments on the Xilinx MicroBlaze soft processor core and the Embedded Development Kit (EDK) associated with it? -- Cheers! MikeArticle: 54139
Hello sirs/friends, I didnot understand how will i pipeline parity checker. Can please tell in detail. how will i find parity, whether xor all 36 bits in one shot or is there any efficient way of finding the parity? should i have parity generator and parity generator as separate module. what is function of dataflow logic in PCI core? waiting for your reply praveenArticle: 54140
Hi > I am using Simulink to model a divider. My input is two integers of size 31 > bits for the numerator and 24 bits for the denominator. For the precision I > require, the result requires 43 bits consisting of 37 fractional bits and 6 > bits for the magnitude. I see that Xilinx has a pipelined divider core > (v2.0), but will this give me the resolution I need? If not, does anyone > know of any other cores that I can use for a Xilinx Virtex II part? I implemented that core, and it works very good but my data was integer: 32bits/24bits = 8bits. But You need to simulate precise couse, I noticed differences between datasheet and realworld :) (length of pipelining). Jerzy GburArticle: 54141
"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message news:9CTia.448$5k3.33562682@newssvr21.news.prodigy.com... > That's one heck of a way to date myself isn't it!!! At least nobody (yet) > suggested a Carbon-14 age test! :-) And how do you think I recognise the part numbers ? :-) The first semiconductor component I ever bought, as a nervous youngster, was an OC71. It cost me three weeks' pocket money. My middle-aged mentors in the local amateur radio society told me it was "the fastest fuse on three legs". But once I'd figured out that the HT supply should only be 9V, and that it should be negative, there was no holding me back. It's just that I'm still having a helluva time working out how to connect the filament supply to these new FPGA doohickeys. Just a passing thought: The fiftieth anniversary of the invention of the transistor came and went in December 1997 with hardly a murmur in the British media. Did it raise any more enthusiasm anywhere else? -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 54142
Hello Sirs/Friends I have some doubt in PCI specification 1.why bus parking done only for AD,C/BE and PAR?why other signal donot need parking 2.Any idea about Prefetching???? for example Master initiate a read (burst read ,prefetech buffer 4 double word) at location 30000000 ,so data from 30000000 to 30000010 is fetched ? IS this true ? next address is whether 30000004 or 30000014? If it is 30000004 then data from 3000004 to 30000014 is fetched?Is this true? IF target side prefetch is disabled?what will happen? only one data is passed to the initiator side?Is this true? 3.what is the role of MAX_LAT in the configuration register? 4.what is use of signal being of sustained tristate type? waiting for reply praveenArticle: 54143
hi all, when people say there design is around 50k gates. Which is the basic gate in which they say the count. is it Nand gate?? thanks LIjoArticle: 54144
Hi guys, I usually use the ISE Foundation v5.1 for my VHDL projects and I've got a really interesting problem. The thing is that when I synthezise the project, the compiler changes the name of my internal signals or nets. How can I avoid this? It's really a laborious task to look for the signals you want to include in your "ucf" in the "FPGA Editor". Thanks. Arkaitz.Article: 54145
"Jonathan Bromley" <jonathan.bromley@doulos.co.uk> wrote: >"Martin Euredjian" <0_0_0_0_@pacbell.net> wrote in message >news:9CTia.448$5k3.33562682@newssvr21.news.prodigy.com... >> That's one heck of a way to date myself isn't it!!! At least nobody (yet) >> suggested a Carbon-14 age test! :-) > >And how do you think I recognise the part numbers ? :-) > >The first semiconductor component I ever bought, as a >nervous youngster, was an OC71. It cost me three weeks' >pocket money. Just checked my old transistor draw and found an OC71, OC45s, and an AC128. Heh, remember the sorrow when having used it in so many breadboard circuits a leg broke off :(Article: 54146
Hi all, I decided to have a go at writing a small fft for learning purposes. (32 pts). I seem to be having problems with the fixed lengths for the data. The twiddle factors are 16 bits. Initially, for butterfly stage 1, I read in 16 bit input data (it has already been position reversed), do the multiplication by the twiddle factor (I know you don't need to multiply by the twiddle factor in the first stage as it is 1, but just to keep it consistant).This brings the results for the real and imaginary outputs to 32 bits. I truncate the 32 bits to the most significant 24 bits and feed it to next butterfly stage, where I mult again by the 16 bit twiddle factor, as well doing the addition. Now I have 40 bit results for the real and imaginary outputs from this butterfly stage. Again I truncate to the 24 MS bits before next stage. The outputs from each butterfly stage are not the results I would expect, so I am wondering have I made an error in my quantization strategy. Anybody care to shed some light on what is a good method for passing the outputs from one butterfly stage to the next butterfly stage. I have made sure the input data is small enough, so that I don't get overflow. Thanks Bob CarterArticle: 54147
In article <20540d3a.0304030624.123cca37@posting.google.com>,
stenasc@yahoo.com (Bob) writes:
|> Hi all,
|>
|> I decided to have a go at writing a small fft for learning purposes.
|> (32 pts). I seem to be having problems with the fixed lengths for the
|> data.
|>
|> The twiddle factors are 16 bits. Initially, for butterfly stage 1, I
|> read in 16 bit input data (it has already been position reversed), do
|> the multiplication by the twiddle factor (I know you don't need to
|> multiply by the twiddle factor in the first stage as it is 1, but just
|> to keep it consistant).This brings the results for the real and
|> imaginary outputs to 32 bits. I truncate the 32 bits to the most
A multiplication of two signed values with 16bit give a 31bit signed value. You
have only one sign bit in the output, but two in the input data ;-)
Can that be the problem?
--
Georg Acher, acher@in.tum.de
http://wwwbode.in.tum.de/~acher
"Oh no, not again !" The bowl of petunias
Article: 54148On Thu, 3 Apr 2003 19:19:05 +0530, "LIJO" <lijo_eceNOSPAM@hotmail.com> wrote: >hi all, > when people say there design is around 50k gates. Which is the basic >gate in which they say the count. is it Nand gate?? > >thanks >LIjo > If you want to be more precise, it's usually x1 strength, 2 input nand gate. Muzaffer Kal http://www.dspia.com ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 54149
> I would like to thank all for their good ideas and help. > > I've tested some of the suggested ideas and wrote a little summary with some > osci plots. You can find them at: > http://www.jopdesign.com/cyclone/powerup.jsp > I've added plots for the darlington regulator circuit. Martin Schoeberl
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