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Hi,
I recently start to use ModelSim for debugging.
But I found that I can't see the internal signals unless I
add them to wave window before simulation. If I use "add wave -r /*",
then I will see thousands of signals on the wave window.
Selecting two signals out of thousand signals is also time consuming.
Is it possible that the Modelsim retain all the waveform of every internal
signals but only appear on the wave window when I select it?
Thanks!
James
Article: 55076
Yep, we do that quite a bit. All of our filters, for example, use SRL16's
instead of LUTs to permit reloading the coefficients. We have several designs
that have over 70% of the LUTs configured as SRL16's. This is why I am
disappointed with Xilinx's decision to can half the SRL16's in the SpartanIII
architecture. Problem is, the average user is not all that aware of the power
of SRL16's so Xilinx claims less than 5% of LUTs are used as SRL16/s
Robert Finch wrote:
> > > > I am wondering if you know any available FPGA devices which are
> dynamically
> > > > reconfigurable. I am doing a project in the area of evolvable hardware
> and I
> > > > am looking to buy a board with dynamic reconfigurable FPGAs.
> > >
>
> You can get kind of a dynamic reconfigurability out of SpartanII device.
> I've never tried this, but I think it should work. The SRL16 feature can be
> used to reload LUT ram contents, acting effectively as a second write port
> to the LUT. Since the LUT ram can be reloaded it can change the logic
> function of the LUT. By wiring up LUT's appropriately it should be possible
> to get some facsimile of a dynamically reconfigurable part.
>
> Rob
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55077Powermos, The intial startup current peak occurs before configuration is even started to be read in. Nothing you can program, no pin, no bit, affects the power on spike. Austin Powermos wrote: > Can you give me major information about this? > > I'm currently working with Spartan device, throught the compiler option I > can configure the device in fast or slow mode. > Current consuption must be less into slow mode, it's right? > > Best regards > Powermos > > -- > ---------------------------------------------------- > Ama il tuo mestiere con passione > E' il significato della tua vita > Auguste Rodin (1840-1917) > "Austin Lesea" <Austin.Lesea@xilinx.com> ha scritto nel messaggio > news:3EA4165D.7D31410B@xilinx.com... > > Lost, > > > > All FPGAs don't have this problem. For example, Virtex II, Virtex II Pro, > > and Spartan III don't have this problem. > > > > "This problem" was something that had to be fixed by IC design, and > > avoided. So it is not a natural result of an SRAM based FPGA. > > > > Austin > > > > LostSignal wrote: > > > > > > Does Altera officially recognize the Power On Surge problem ? > > > > I didn't find any references to this problem in Altera's datasheets or > > > > App. notes. Their datasheets don't specify start up current as well. > > > > One of our designs sometimes has strange power-up problems at the low > > > > temperature. We never attributed this problems to the FPGA. Actually I > > > > didn't hear about this problem before (thank you, Martin). Now I'm > > > > starting to suspect that the problem is related to FPGA. The design is > > > > based on ACEX 1K100 device. Where can I find Power On Current profile > > > > for this device ? > > > > > > Apparently ALL SRAM based FPGAs experience this problem to some > > > degree. At the startup the configuration SRAM is in unknown state and > > > that causes large current surge that must be satisfied in order for > > > FPGA to configure properly. AFAIK the differences between Xilinx and > > > Altera in this regard are: > > > 1. Xilinx publicly acknowleged this problem some time ago has several > > > articles on it. I have not seen much from Altera (correct me if I am > > > wrong). > > > 2. The rumor is Altera has a somewhat smaller surge and people have > > > less trouble with it. Dunno how true it is though. I've heard from an > > > Altera guy that a really large Altera part can draw 2.5 A. The maximum > > > current specified for Xilinx is 2 A at low temperature. Go figure.. > > > > > > Lost Signal > >Article: 55078
eric - Mtl wrote: > > Well, I don't have a boss. I have customers, and my customers are for now > way more comfortable with a schematic diagram of the functions they want > because everyone there can figure out what it's doing. This might change, > but for now, that's what they like. They would certainly take VHDL code, > if I make them a nice schematic diagram that explains what it does ... I think this will be my last post on this since I have said pretty much every thing I can add, but... A schematic without written documentation is no more useful than an HDL file without documentation. I produce descriptions and block diagrams in *both* cases. My current board design started with a block diagram and is the first page of my schematic drawing. So I think the issue of documentation is a red herring for going with schematic vs. HDL. > The whole point of this thread was that tool quality severely lags behind > silicon quality and capabilities, and that should be a concern for "X" & "A" > as well as for all users, no matter if they code using schematics, VHDL, > Verilog or whatever ... Yes, but you can get benefit from going with HDL vs. schematic. I am sure Xilinx wants to sell chips and will do so no matter which tool you demand. But as the number of users converting away from schematic increases, you have to face the fact that the level of support for that tool will be reduced. I don't like it either, since there are always some designs that are easier with schematic, but that is the fact. I advise that you try a project with HDL (with a positive expectation). I was a diehard schematic person until I used it enough to get over the "hump". Now I don't expect to go back even for those few designs where schematic would be easy. HDL has some advantages that are valid for *any* project (like version control with differences). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55079
Aldec has a really nice Verilog training tool on their website: www.aldec.com Knowing both is the only way to do it that I can think of. "shyweij" <shyweij@nyc.rr.com> wrote in message news:g2Tpa.24913$J17.15240@twister.nyc.rr.com... > Hello all. > > Does anyone know a good online source that can teach me how to manually > convert Verilog to VHDL. I don't know much verilog but do know VHDL. Any > help would be greatly appreciated. > > > thanks.Article: 55080
Ray Andraka wrote: > > Yep, we do that quite a bit. All of our filters, for example, use SRL16's > instead of LUTs to permit reloading the coefficients. We have several designs > that have over 70% of the LUTs configured as SRL16's. This is why I am > disappointed with Xilinx's decision to can half the SRL16's in the SpartanIII > architecture. Problem is, the average user is not all that aware of the power > of SRL16's so Xilinx claims less than 5% of LUTs are used as SRL16/s I may have made this point before, so please ignore my post if so. I expect you will still see a benefit from the Spartan 3 parts even with half the number of SRLs as LUTs. You also need to consider the cost savings of this family of parts. Try not thinking of it as a part with *half* the number of SRLs, think of it as having *twice* the number of LUTs. So it is very likely that you can get the same number of SRLs, twice the number of LUTs and still come in with a lower power, cheaper part than either a Virtex II or a Spartan II part, no? I only wish they were going to have the parts available before next year... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55081
shyweij <shyweij@nyc.rr.com> wrote in message news:<g2Tpa.24913$J17.15240@twister.nyc.rr.com>... > Hello all. > > Does anyone know a good online source that can teach me how to manually > convert Verilog to VHDL. I don't know much verilog but do know VHDL. Any > help would be greatly appreciated. > > > thanks. <Aldec has a really nice Verilog training tool on their website: www.aldec.com Knowing both is the only way to do it that I can think of.> FYI, my book Real Chip Design and Verification Using Verilog and VHDL explains the subtle nuances between the 2 HDLs, and provides lots of examples in both HDLs. See TOC at my site Ben --------------------------------------------------------------------------- Ben Cohen Publisher, Trainer, Consultant (310) 721-4830 http://www.vhdlcohen.com/ vhdlcohen@aol.com Author of following textbooks: * Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8 * Component Design by Example ", 2001 isbn 0-9705394-0-1 * VHDL Coding Styles and Methodologies, 2nd Edition, 1999 isbn 0-7923-8474-1 * VHDL Answers to Frequently Asked Questions, 2nd Edition, isbn 0-7923-8115 ------------------------------------------------------------------------------Article: 55082
Hi. I am having problems with my Altera Flex 8K FPGA. I am programming the device via Linux using the ByteBlaster MV hardware as this is what is specified for my final year project, and the device seems to be correctly configured. However, once I turn the power supply off and back on again, the FPGA seems to lose its configuration. I was wondering whether someone could tell me what I am doing wrong or what my circuit lacks in order to hold the configuration, or whether the Flex 8K is not able to hold its configuration without the aide of external boot chip, although I don't believe this is the case. It would be very much appreciated if someone could provide a solution to this problem as soon as possible, as the deadline is drawing near. Thank you very much, Karl.Article: 55083
"Karl" <karlharmer@hotmail.com> wrote in message news:e1263d08.0304251338.6bbf29ba@posting.google.com... > I am having problems with my Altera Flex 8K FPGA. I am programming the > device via Linux using the ByteBlaster MV hardware as this is what is > specified for my final year project, and the device seems to be > correctly configured. However, once I turn the power supply off and > back on again, the FPGA seems to lose its configuration Unless I remember wrong, 8K is a RAM based device, and yes, will lose configuration on power down. The normal way is to supply an on-board EPROM to load from. An alternate method is to supply a battery to keep the configuration when the system is powered down. I know Xilinx has that ability, sometimes used for security purposes. -- glenArticle: 55084
Hello, I am confused on how to compute the maximum frequency that a blockRAM can run on?. is it dependent only on TCKO?. usually what is the maximum speed achieved in Virtex-E and Virtex-II thanks -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 55085
littlebean wrote: > Is it possible that the Modelsim retain all the waveform of every internal > signals but only appear on the wave window when I select it? log -r /* -- Mike TreselerArticle: 55086
littlebean wrote: > Hi, > I recently start to use ModelSim for debugging. > But I found that I can't see the internal signals unless I > add them to wave window before simulation. If I use "add wave -r /*", > then I will see thousands of signals on the wave window. > Selecting two signals out of thousand signals is also time consuming. > Is it possible that the Modelsim retain all the waveform of every internal > signals but only appear on the wave window when I select it? > > Thanks! > James Hi James, Before you start the simulation, use the log -r * command to have Modelsim record all the internal nodes. Adding a signal to the waveform window later on will show you the full trace. Best regards, BenArticle: 55087
The Altera 8k devices like most "FPGAs" are volatile - as opposed to "CPLDs" which are mostly non-volatile - meaning that they won't power cycle back to where they left off. You must either 1) use the byteblaster to reconfigure your part every time you power up or 2) use an external method of configuring on bootup, commonly through the use of a serial PROM available from Altera. The 8k data sheet goes to pains to explain the multiple methods of configuring the device. This operation must be done every power-up of the chip. (Some of) the serial PROMs can be configured by the ByteBlaster and the serial PROMs can then configure the Altera chip on every power up. Back when I worked with the 8ks, I recall going through quite a few of the little 8-pin one-time-programmable devices during development. Ahhh, for the days when dip sockets ruled. If the final year project was using a specific development board, the prof should expect the byte-blaster need or expect the use of a yet to be discovered reprogrammable boot device already on the development board. Good luck with the presentation! "Karl" <karlharmer@hotmail.com> wrote in message news:e1263d08.0304251338.6bbf29ba@posting.google.com... > Hi. > > I am having problems with my Altera Flex 8K FPGA. I am programming the > device via Linux using the ByteBlaster MV hardware as this is what is > specified for my final year project, and the device seems to be > correctly configured. However, once I turn the power supply off and > back on again, the FPGA seems to lose its configuration. I was > wondering whether someone could tell me what I am doing wrong or what > my circuit lacks in order to hold the configuration, or whether the > Flex 8K is not able to hold its configuration without the aide of > external boot chip, although I don't believe this is the case. > > It would be very much appreciated if someone could provide a solution > to this problem as soon as possible, as the deadline is drawing near. > > Thank you very much, > > Karl.Article: 55088
Stephen Williams <icarus-hates-spam@icarus.com> writes: >>This question has been asked a lot. Someone should put together a ready- >>to-run WINE configuration (including config files and pre-installed disk >>image) that works. >> >>At least for WebPACK. Marius Vollmer wrote: > Yes, that would be nice. Does Xilinx allow redistribution of the > WebPACK files? If someone made up such a package, complete and ready to go, and presented it to Xilinx, or at least the right Xilinx people who can work the issue from the inside, I bet something positive would come of it. There are already several APP notes that attempt to get users pasted together with wine under Linux, so they've clearly had to deal with this issue. They are also in the embarrassing position of being maybe the only FPGA tools supplier to not (yet) support Linux. Allowing a convenient (emphasis on "convenient") wine packaging of old tools can't hurt their image:-) And finally, since they have claimed that certain combinations of WINE and ISE are *supported*, having it prepackaged surely would ease the burden on their support system. So I say, if someone has the time to make such a package they should go for it. The WINE experts lurking herin could save the rest of us a lot of trouble:-) -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 55089
The Virtex and Virtex-II BlockRAMs behave like a flip-flop with very short set-up time (0.3 ns) and relatively long clock-to-out time ( 3ns). Clock perid should be >4 ns. (For more precise numbers see the data sheet or the speeds files in the Xilinx software.) With reasonably fast routing around the BlockRAM you will have no problem at 200 MHz. There are clever ways to use the two ports on opposite clock phases and alternate between them, thus achieving "double data rate" performance., well above 500 Megaops per second, effectively using the BlockRAM as a single-port RAM. Peter Alfke ================= Hristo Stevic wrote: > > Hello, > I am confused on how to compute the maximum frequency that a blockRAM > can run on?. is it dependent only on TCKO?. > > usually what is the maximum speed achieved in Virtex-E and Virtex-II > > thanks > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 55090
There are two distict levels to this. First is the DSP angle, in which you need
to understand the math behind the filter in order to select a filter type and
coefficients appropriate to your project. Second, there is the digital hardware
level, which describes the filter structure in terms of gates. One fiter
structure that works well with FPGAs is an FIR filter constructed using
distributed arithmetic. I recommend first going to a DSP book to learn about
filters (Marv Frerking's book has a good chapter on filtering, see the bookstore
on my website). Then after you understand the filter theory, then learn about
techniques for realizing it in the FPGA. I have a short tutorial on distributed
arithmetic on my website as well.
Powermos wrote:
> Hi,
>
> I'm new into this ng.
>
> I've interest into digital filter, my present work is with FPGA like Spartan
> and XC5202 family. Can you give me an example of digital filter
> implementation?
> I've no material about this, only knowledge is about my control theory
> course and is about digitizing the analog filter throught the Z-transform
> technique. I'm very gratefully if you can help me.
>
> Thanks in advance and best regards
>
> Fabio Filippa
>
> --
> ----------------------------------------------------
> Ama il tuo mestiere con passione
> E' il significato della tua vita
> Auguste Rodin (1840-1917)
> "Philippe Molson" <philippe_molson@yahoo.com> ha scritto nel messaggio
> news:e1558d23.0304171903.5a14ad71@posting.google.com...
> > Hi,
> >
> > Some band-pass IIR filters require large precision. The Fixed-point
> > analysis depends heavely on the IIR characteristics.
> >
> > Altera has developed several tools to help you to design fixed-point
> > IIR filters.
> >
> > You can probably start by downloading the Altera IIR-Compiler
> > http://www.altera.com/products/ip/dsp/filtering/m-alt-iircompiler.html
> >
> > This is an IP. With the evaluation version, you start from the
> > floating-point IIR coefficients and use the built-in floating to
> > fixed-point conversion analysis tools. This help you to determine
> > which bit can be truncated in both feedback and feedforward data-path.
> > The IIR-compiler is interactif and displays dynamically the filter
> > response in the zero-pole or frequency or time domain, based on
> > parameters such as bit-width selection/truncation (among others)
> >
> > In addition, in this tool you can evaluate various IIR structures,
> > such as direct form II, biquad cascaded or biquad parallel. You
> > probably will find out that the fixed-point maths vary from one
> > structure to another. You can also trade-off FPGA multiplier/adder
> > style (parallel distributed arithmetic, MAC based).
> >
> > If you are familiar with Matlab Simulink, another option consists of
> > using the DSP Builder, which is a Simulink plug-in and can be
> > downloaded from :
> >
> >
> http://www.altera.com/products/software/system/products/dsp/dsp-builder.html
> >
> > From the Simulink cockpit , you can use the IIR compiler, or build the
> > IIR structure with the DSP Builder primitives (Multiply, Add, LUT ...)
> > optimized for Cyclone or Stratix. The DSP Builder-Simulink flow gives
> > you enhanced sink and source block for system analysis, and this could
> > be very usefull in this case when you need to analyze complex aspects
> > of fixed-point IIR design such as stability.
> >
> > Building the filter with DSP Builder primitive may take longer than
> > using the IIR-Compiler, however it may allow you to explore FPGA
> > architectures implementation which are not yet present in the
> > IIR-Compiler such as multi-bit serial.
> >
> > I hope that this will help you to build efficient IIR filters for
> > Cyclone device.
> >
> >
> > Philippe Molson
> > Altera Corporation
> >
> >
> > "gallenm" <gallenm@ic24.net> wrote in message
> news:<v9tmpdn101mb60@corp.supernews.com>...
> > > Hi,
> > > Just adding a plug for ONEoverT digital filter designer. It will
> > > automatically produce
> > > synthesizable VHDL for IIRs and FIRs. Very cheap, the demo can be
> downloaded
> > > from
> > > the website
> > > www.tyder.com
> > >
> > > If you download the case study, it will show you the implemention of an
> IIR
> > > onto a Spartan
> > > FPGA.
> > >
> > > Yours
> > > Alan Mc Kitterick
> > > www.tyder.com
> > >
> > > "Pramod" <pramod@procsys.com> wrote in message
> > > news:a7c0720d.0304152101.581c85be@posting.google.com...
> > > > Hi All,
> > > > I am new to this group and also to the field of FPGA based design.
> > > > I have some doubts and issues which I feel will be easy for you guys
> > > > to answer.
> > > > 1. For a 4 pole IIR Filter in FPGA (targeted device EP1C6), I have a
> > > > spec of 24 bit wide data input and
> > > > 32 bit wide coeff (dynamic) inputs. So, the multiplied results should
> > > > ideally have
> > > > 56 bits width. Are these widths practically relevant for a 4 pole
> > > > filter
> > > > or can we get an affordable precision with rounding to lower sizes?
> > > > If so, can anyone suggest a standard procedure for
> > > > rounding the results with lowest error and without causing the output
> > > > to become unstable?
> > > > 2. Another thing I would like to get some advice is, if I go with the
> > > > 24 X 36 busses,
> > > > since I have to implement a number of such filters in a single device,
> > > > the bit-parallel implementation will take up huge resources.
> > > > The digit serial approach using (either small multiplier or LUT
> > > > method)
> > > > also will end up in huge resources due to big number of partial
> > > > products and sums involved.
> > > > If anyone can suggest any alternate method it will be of great help to
> > > > me.
> > > > 3. On another front, in a timing simulation scenario I am using
> > > > Quartus II .vo output and ModelSIM PE. My code has
> > > > a ROM (ALTSYNCRAM megafunction used to generate this). I found some
> > > > differences in the
> > > > readout data during timing simulation between using .MIF format file
> > > > and .HEX format file for initializing ROM
> > > > eventhough the QII displayed same contents in the memory editor.
> > > > Has anyone ever faced any such issues?
> > > > Hoping to get some valuable leads on these..
> > > > Thanks in advance,
> > > > Pramod
> >
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55091
Possibly. Many of my customers aren't even moving to SpartanIIe's because of
interface issues. I've got a number of designs that use a SpartanII as the glue to
the rest of the system in order to be able to interface other logic.
rickman wrote:
> Ray Andraka wrote:
> >
> > Yep, we do that quite a bit. All of our filters, for example, use SRL16's
> > instead of LUTs to permit reloading the coefficients. We have several designs
> > that have over 70% of the LUTs configured as SRL16's. This is why I am
> > disappointed with Xilinx's decision to can half the SRL16's in the SpartanIII
> > architecture. Problem is, the average user is not all that aware of the power
> > of SRL16's so Xilinx claims less than 5% of LUTs are used as SRL16/s
>
> I may have made this point before, so please ignore my post if so. I
> expect you will still see a benefit from the Spartan 3 parts even with
> half the number of SRLs as LUTs. You also need to consider the cost
> savings of this family of parts. Try not thinking of it as a part with
> *half* the number of SRLs, think of it as having *twice* the number of
> LUTs.
>
> So it is very likely that you can get the same number of SRLs, twice the
> number of LUTs and still come in with a lower power, cheaper part than
> either a Virtex II or a Spartan II part, no?
>
> I only wish they were going to have the parts available before next
> year...
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55092On Thu, 24 Apr 2003 11:37:25 -0400, Pat Ford wrote: > Hi All; > Has anyone had luck getting ise4.2 to work under wine using a stock > RH7.3 > system? I've gone throught the steps outlined in the xilinx faqs but no > luck. > Pat Here is a link to the HOWTO http://www.polybus.com/xilinx_on_linux.htmlArticle: 55093
Marius Vollmer <marius.vollmer@uni-dortmund.de> writes: > Stephen Williams <icarus-hates-spam@icarus.com> writes: > > > This question has been asked a lot. Someone should put together a ready- > > to-run WINE configuration (including config files and pre-installed disk > > image) that works. > > > > At least for WebPACK. > > Yes, that would be nice. Does Xilinx allow redistribution of the > WebPACK files? As long as Xilinx keeps the URL for the WebPack constant one could use wget in the installation script to fetch it. Petter -- ________________________________________________________________________ Petter Gustad 8'h2B | ~8'h2B http://www.gustad.com/petterArticle: 55094
How does a Virtex implement a shift register in the same LUT? An LUT is basically a RAM with an address bus and a single bit read/write data bus. Are there special routes inside the LUT that write back the most significant n-1 ( n= size of the SR) bits alongwith the newest bit back into the same LUT? How are the bits physically moved inside the RAM? regards, Nachiket Kapre. Paxonet Communications Inc.Article: 55095
Ray Andraka <ray@andraka.com> wrote: : Possibly. Many of my customers aren't even moving to SpartanIIe's because of : interface issues. I've got a number of designs that use a SpartanII as the glue to : the rest of the system in order to be able to interface other logic. Yes, simple 5 V tolerance is a nice feature... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55096
Thanks for your info! Pow -- ---------------------------------------------------- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917) "Austin Lesea" <Austin.Lesea@xilinx.com> ha scritto nel messaggio news:3EA99B6A.132044DF@xilinx.com... > Powermos, > > The intial startup current peak occurs before configuration is even started to > be read in. > > Nothing you can program, no pin, no bit, affects the power on spike. > > Austin > > Powermos wrote: > > > Can you give me major information about this? > > > > I'm currently working with Spartan device, throught the compiler option I > > can configure the device in fast or slow mode. > > Current consuption must be less into slow mode, it's right? > > > > Best regards > > Powermos > > > > -- > > ---------------------------------------------------- > > Ama il tuo mestiere con passione > > E' il significato della tua vita > > Auguste Rodin (1840-1917) > > "Austin Lesea" <Austin.Lesea@xilinx.com> ha scritto nel messaggio > > news:3EA4165D.7D31410B@xilinx.com... > > > Lost, > > > > > > All FPGAs don't have this problem. For example, Virtex II, Virtex II Pro, > > > and Spartan III don't have this problem. > > > > > > "This problem" was something that had to be fixed by IC design, and > > > avoided. So it is not a natural result of an SRAM based FPGA. > > > > > > Austin > > > > > > LostSignal wrote: > > > > > > > > Does Altera officially recognize the Power On Surge problem ? > > > > > I didn't find any references to this problem in Altera's datasheets or > > > > > App. notes. Their datasheets don't specify start up current as well. > > > > > One of our designs sometimes has strange power-up problems at the low > > > > > temperature. We never attributed this problems to the FPGA. Actually I > > > > > didn't hear about this problem before (thank you, Martin). Now I'm > > > > > starting to suspect that the problem is related to FPGA. The design is > > > > > based on ACEX 1K100 device. Where can I find Power On Current profile > > > > > for this device ? > > > > > > > > Apparently ALL SRAM based FPGAs experience this problem to some > > > > degree. At the startup the configuration SRAM is in unknown state and > > > > that causes large current surge that must be satisfied in order for > > > > FPGA to configure properly. AFAIK the differences between Xilinx and > > > > Altera in this regard are: > > > > 1. Xilinx publicly acknowleged this problem some time ago has several > > > > articles on it. I have not seen much from Altera (correct me if I am > > > > wrong). > > > > 2. The rumor is Altera has a somewhat smaller surge and people have > > > > less trouble with it. Dunno how true it is though. I've heard from an > > > > Altera guy that a really large Altera part can draw 2.5 A. The maximum > > > > current specified for Xilinx is 2 A at low temperature. Go figure.. > > > > > > > > Lost Signal > > > >Article: 55097
Thanks, from your point of wiev, direct syntesis from Z-transform of Laplace filter function can be adequate for a first simple design? Best regards Fabio -- ---------------------------------------------------- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917) "Ray Andraka" <ray@andraka.com> ha scritto nel messaggio news:3EA9F7DF.662228BD@andraka.com... > There are two distict levels to this. First is the DSP angle, in which you need > to understand the math behind the filter in order to select a filter type and > coefficients appropriate to your project. Second, there is the digital hardware > level, which describes the filter structure in terms of gates. One fiter > structure that works well with FPGAs is an FIR filter constructed using > distributed arithmetic. I recommend first going to a DSP book to learn about > filters (Marv Frerking's book has a good chapter on filtering, see the bookstore > on my website). Then after you understand the filter theory, then learn about > techniques for realizing it in the FPGA. I have a short tutorial on distributed > arithmetic on my website as well. > > Powermos wrote: > > > Hi, > > > > I'm new into this ng. > > > > I've interest into digital filter, my present work is with FPGA like Spartan > > and XC5202 family. Can you give me an example of digital filter > > implementation? > > I've no material about this, only knowledge is about my control theory > > course and is about digitizing the analog filter throught the Z-transform > > technique. I'm very gratefully if you can help me. > > > > Thanks in advance and best regards > > > > Fabio Filippa > > > > -- > > ---------------------------------------------------- > > Ama il tuo mestiere con passione > > E' il significato della tua vita > > Auguste Rodin (1840-1917) > > "Philippe Molson" <philippe_molson@yahoo.com> ha scritto nel messaggio > > news:e1558d23.0304171903.5a14ad71@posting.google.com... > > > Hi, > > > > > > Some band-pass IIR filters require large precision. The Fixed-point > > > analysis depends heavely on the IIR characteristics. > > > > > > Altera has developed several tools to help you to design fixed-point > > > IIR filters. > > > > > > You can probably start by downloading the Altera IIR-Compiler > > > http://www.altera.com/products/ip/dsp/filtering/m-alt-iircompiler.html > > > > > > This is an IP. With the evaluation version, you start from the > > > floating-point IIR coefficients and use the built-in floating to > > > fixed-point conversion analysis tools. This help you to determine > > > which bit can be truncated in both feedback and feedforward data-path. > > > The IIR-compiler is interactif and displays dynamically the filter > > > response in the zero-pole or frequency or time domain, based on > > > parameters such as bit-width selection/truncation (among others) > > > > > > In addition, in this tool you can evaluate various IIR structures, > > > such as direct form II, biquad cascaded or biquad parallel. You > > > probably will find out that the fixed-point maths vary from one > > > structure to another. You can also trade-off FPGA multiplier/adder > > > style (parallel distributed arithmetic, MAC based). > > > > > > If you are familiar with Matlab Simulink, another option consists of > > > using the DSP Builder, which is a Simulink plug-in and can be > > > downloaded from : > > > > > > > > http://www.altera.com/products/software/system/products/dsp/dsp-builder.html > > > > > > From the Simulink cockpit , you can use the IIR compiler, or build the > > > IIR structure with the DSP Builder primitives (Multiply, Add, LUT ...) > > > optimized for Cyclone or Stratix. The DSP Builder-Simulink flow gives > > > you enhanced sink and source block for system analysis, and this could > > > be very usefull in this case when you need to analyze complex aspects > > > of fixed-point IIR design such as stability. > > > > > > Building the filter with DSP Builder primitive may take longer than > > > using the IIR-Compiler, however it may allow you to explore FPGA > > > architectures implementation which are not yet present in the > > > IIR-Compiler such as multi-bit serial. > > > > > > I hope that this will help you to build efficient IIR filters for > > > Cyclone device. > > > > > > > > > Philippe Molson > > > Altera Corporation > > > > > > > > > "gallenm" <gallenm@ic24.net> wrote in message > > news:<v9tmpdn101mb60@corp.supernews.com>... > > > > Hi, > > > > Just adding a plug for ONEoverT digital filter designer. It will > > > > automatically produce > > > > synthesizable VHDL for IIRs and FIRs. Very cheap, the demo can be > > downloaded > > > > from > > > > the website > > > > www.tyder.com > > > > > > > > If you download the case study, it will show you the implemention of an > > IIR > > > > onto a Spartan > > > > FPGA. > > > > > > > > Yours > > > > Alan Mc Kitterick > > > > www.tyder.com > > > > > > > > "Pramod" <pramod@procsys.com> wrote in message > > > > news:a7c0720d.0304152101.581c85be@posting.google.com... > > > > > Hi All, > > > > > I am new to this group and also to the field of FPGA based design. > > > > > I have some doubts and issues which I feel will be easy for you guys > > > > > to answer. > > > > > 1. For a 4 pole IIR Filter in FPGA (targeted device EP1C6), I have a > > > > > spec of 24 bit wide data input and > > > > > 32 bit wide coeff (dynamic) inputs. So, the multiplied results should > > > > > ideally have > > > > > 56 bits width. Are these widths practically relevant for a 4 pole > > > > > filter > > > > > or can we get an affordable precision with rounding to lower sizes? > > > > > If so, can anyone suggest a standard procedure for > > > > > rounding the results with lowest error and without causing the output > > > > > to become unstable? > > > > > 2. Another thing I would like to get some advice is, if I go with the > > > > > 24 X 36 busses, > > > > > since I have to implement a number of such filters in a single device, > > > > > the bit-parallel implementation will take up huge resources. > > > > > The digit serial approach using (either small multiplier or LUT > > > > > method) > > > > > also will end up in huge resources due to big number of partial > > > > > products and sums involved. > > > > > If anyone can suggest any alternate method it will be of great help to > > > > > me. > > > > > 3. On another front, in a timing simulation scenario I am using > > > > > Quartus II .vo output and ModelSIM PE. My code has > > > > > a ROM (ALTSYNCRAM megafunction used to generate this). I found some > > > > > differences in the > > > > > readout data during timing simulation between using .MIF format file > > > > > and .HEX format file for initializing ROM > > > > > eventhough the QII displayed same contents in the memory editor. > > > > > Has anyone ever faced any such issues? > > > > > Hoping to get some valuable leads on these.. > > > > > Thanks in advance, > > > > > Pramod > > > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 55098
Hy, in this day i've received a ISE 5.2i evaluation pack. At this time I'm successfully working with Foundation 3.1i, during installation of ISE 5.2i the programm stop into the second form and not show the license agreement, hence I can't continue during installation step. Some help please.................I'm desperate I'd like to evaluate ISE 5.2 but I'm not able to install it!!!! My SO is Windows ME from Xilinx web site seems only Windows 2000 or XP is supported it's right? Thanks for your help!!! Powermos -- ---------------------------------------------------- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917)
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