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Joona, On Cyclone, the way to change the PLL configuration is to reconfigure the entire part. So for your particular application, what you could do is store 8 possible configurations, and choose which one configures the part depending on the user input. Since the user is going to select the multiplication factor, it is probably not changing very often. A way to do this would be to store the configurations in a parallel Flash memory and use a MAX device (CPLD) to select which configuration is used. The Enhanced PLLs on the Stratix devices do support real-time reconfiguration without the need to reconfigure the entire device. For example, logic within the device can change the multiplication and division factors to meet your needs. This process is documented in AN282: http://www.altera.com/literature/an/an282.pdf For your final question on the jitter: The relationship of input jitter to output jitter on a PLL is somewhat complicated. It is not the case that multiplying the frequency by 5 (as in your example) will multiply the jitter by 5. In general, a PLL will pass through low-frequency jitter, but reduce high-frequency jitter. A high-level explanation is that the PLL actually regenerates the clock and does not simply pass it through with some delay, so depending on its characteristics it will not pass through all high-frequency variation of the clock period. Therefore high-frequency jitter is attenuated. On the other hand, a slow variation of the clock period (low-frequency jitter) will be tracked by the PLL oscillator and so will be passed through to the output. The documentation for the various devices shows what the output jitter will be, and this is specified for any multiplication factor. In some cases there is a different spec depending on what multiplication factor is used. For more details on the Stratix PLL and how it implements frequency division/multiplication please consult: http://www.altera.com/literature/hb/stx/ch_1_vol_2.pdf For more details on the Cyclone PLL please consult: http://www.altera.com/literature/an/an251.pdf Sincerely, Greg Steinke gregs@altera.com jonesky1@hotmail.com (Joona R) wrote in message news:<2f3990c3.0304261139.3be78e8c@posting.google.com>... > Hello! > > Can I change Cyclone PLL's divisor and multiply counter values on the > fly? I will use Quartus, after license has arrived. > I want that user can change clock frequency of device by pressing a > button. Needed frequencys are between 30MHz and 100MHz. Frequencys may > be for example 10MHz distances (30, 40, 50, 60, 70, 80, 90 and > 100MHz). > > I was thinking, if input frequency will be 20MHz. Then it is divided > by two and then multiplyed with user's wanted value (3 to 10). Is this > reasonable way? How is input frequency's jitter effecting to output > freq? If fIn is 20MHz with 50ppm, is fOut then 100MHz with 250ppm? > (M=10, N=2) > > Is this possible or is there some better way to do this? Good ideas > are welcome! =) > > Best Regards, > JoonaArticle: 55151
Jonathan Kirwan wrote: > > On Mon, 28 Apr 2003 11:04:57 -0400, rickman > <spamgoeshere4@yahoo.com> wrote: > > >Jonathan Kirwan wrote: > >> > >> On Thu, 24 Apr 2003 22:04:31 -0400, rickman > >> <spamgoeshere4@yahoo.com> wrote: > >> > >> ><snip> > >> >This circuit needs to operate in temps of -40 to 125C. > >> > >> I know someone currently using the TI MSP430F149's at elevated > >> temperatures, in production. They are used in an environment > >> which operates at an ambient in the 150 C to 175 C temp range. > >> (The tougher part, I'm told, was finding batteries to operate > >> well, in that range.) Just a data point. > >> > >> Jon > > > >Yes, I am aware of the battery problem. But I am working on that. I > >have found a primary cell that will work in that range. I just don't > >know if it has the right mounting tabs or if I can buy it in small > >quantities (100's). > > If I recall, he's found a battery which will operate at over 225 > C. I think he told me it was originally for military use. But > is available commercially. I don't recall who makes it, but I > could always ask. He's using small quantities, as well. You can never be too rich, too thin or have to much battery info. Please ask him... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55152
Hi everyone, I am trying to make Modelsim SE 5.7c (platform independent, floating license) work with ISE 5.1i: license checking is correct, vcom works, vsim works, but droping signals to wave window (or entering "log -r *" or "add wave *") crashes everything and shutdowns all windows. BTW, the box is a PC with WinXP. Any suggestions are welcome. Thanks in advance. ----------------------------------------------------------------------- Javier Garrigos Guerrero Departamento de Electronica, Tecnologia de Computadoras y Proyectos E.T.S. de Ingenieros Industriales - Univ. Politecnica de Cartagena Antiguo Hospital de Marina, C/Dr. Fleming s/n, 30202 CARTAGENA -SPAIN- E-mail: yerby@ono-remove.com -----------------------------------------------------------------------Article: 55153
yerbby wrote: > > Hi everyone, > > I am trying to make Modelsim SE 5.7c (platform independent, floating > license) work with ISE 5.1i: > > license checking is correct, vcom works, vsim works, but droping signals to > wave window (or entering "log -r *" or "add wave *") crashes everything and > shutdowns all windows. > > BTW, the box is a PC with WinXP. > > Any suggestions are welcome. Thanks in advance. This works fine for me with ModelSim 5.7c and ISE 5.2 and Windows 2000. There is no reason that I can see for there to be any interaction between your synthesis tool and your simulation tool. Other than your ASCII source files, they should have nothing in common, unless you are doing a gate-level sim with back-annotated delays. Are you possibly trying to use the pre-compiled libraries for the Xilinx version of ModelSim? This will definitely cause problems since the Xilinx version and the "real" version are at different rev levels. You must compile the libraries yourself and they must be compiled with the current "number" version of ModelSim (i.e. at least version 5.7 when using 5.7c). Check your ModelSim release notes for more details. Otherwise, sounds like a problem for ModelSim tech support. -- Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.comArticle: 55154
Under Synthesize in Project Navigator you will find a "View RTL Schematic" item. Use it to show the schematic view you are asking about. "Powermos" <flatiron@libero.it> wrote in message news:HBzqa.69574$DT4.2075004@twister1.libero.it... > For Rosen, > > another question for you, I'm studing the VHDL with Douglal Perry 3 edtn > book, with ISE is possible to show > a schematic view of VHDL code, this can be helpful to check if my > interpretation is correct or not. > > Thanks in advance > Powermos > > -- > ---------------------------------------------------- > Ama il tuo mestiere con passione > E' il significato della tua vita > Auguste Rodin (1840-1917) > "B. Joshua Rosen" <bjrosen@polybus.com> ha scritto nel messaggio > news:pan.2003.04.26.16.42.30.976665.16831@polybus.com... > > On Sat, 26 Apr 2003 12:14:50 -0400, Powermos wrote: > > > > > Hy, > > > > > > in this day i've received a ISE 5.2i evaluation pack. At this time I'm > > > successfully working with Foundation 3.1i, during installation of ISE > > > 5.2i the > > > programm stop into the second form and not show the license agreement, > > > hence I can't continue during > > > installation step. > > > > > > Some help please.................I'm desperate I'd like to evaluate ISE > > > 5.2 but I'm not able to install it!!!! > > > > > > My SO is Windows ME from Xilinx web site seems only Windows 2000 or XP > > > is supported it's right? > > > > > > Thanks for your help!!! > > > > > > Powermos > > > > > > -- > > > ---------------------------------------------------- Ama il tuo mestiere > > > con passione > > > E' il significato della tua vita > > > Auguste Rodin (1840-1917) > > > > 5.2 is Win2K or XP only. It also works fine on Linux using Wine. None of > > the Win9x OSs are supported including WinME. You are going to have to > > upgrade your OS if you want to use 5.2. > >Article: 55155
Respected sir, want to design a circuit which gives the output of '1' for duration of 0.5us when an input transit from '0' to '1'. i want an synthesisable code for this . so can you please mail me in this regard.Article: 55156
[trying to avoid accidently writing to Flash chip] [external jumper] >The idea is that, as long as the WEn pin is not pulled to 0V, it's >impossible to write into the Flash. This has to be done externally, as there >is no other way you can 100% guarantee that your design will not happen to >accidentally pull the signal low, attempt to write to the magic addresses >etc, etc otherwise. Is there a separate pin on the FPGA that connects to the WEn on the Flash? (as compared to a shared WEn that goes to Flash and RAM) If so, then you are safe if you don't connect any logic to that pin. You are also reasonably safe if you just hack the logic in the design so that writes to Flash address space get trapped or ignored. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55157
Hello Anup. You cannot synthesize time delay in VHDL. What you need to do is use a counter that will perform the necessary delay. The counter will count a number of clock cycles that is equivalent to 0.5 us. The number of cycles depends on the frequency of your clock. (Example: for a 20 Mhz clock, you need to count 10 cycles). Gilad.Article: 55158
well.. actually its a sot23 5 pin package and costs 67c on the web site.. and a digital output so it wouldn't be hard to fit :-) considering it would shut down a standard temp micro, the micro cost saving would satisfy the extra cost of a $1 FET and a 67c thermal switch. Or better.. use a regulator with an on/off switch and just turn it on / off via the thermal switch.. it can be fed from 2.7V to 5.5V after all. Is not that silly if you add the pros and cons. Unless as you say the space will kill ya.. but I've yet to see a board I couldn't squeeze the last square mm out of (have been doing CAD for many a year) Simon "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3EAD47AC.4EB694C2@yahoo.com... > Simon wrote: > > > > Why bother getting the micro to save the rest ?? > > > > Why not use a Maxim temperature switch & a FET which will simply shut off > > the power at the critical moment ?? MAX6501/2 comes to mind. It could > > either just shut down to power to the whole board and repower it again when > > the temperature drops, a second device at a lower temperature could warm the > > processor or it could measure the temp with a ADC input. This way nothing > > but the temp sensor and the on/off FET is powered at high temp. > > > > Simon > > That is an easy question to answer. The space is limited (as well as > the cost). Due to the issues of testing mainly, I can get a single MCU > to do all the tasks I need rather than to use one or two temp sensors > along with an ADC along with random logic to shutdown the board and hold > the processors in reset, etc... > > Once I have a temperature measurement along with the various voltage > measurements and the intelligence of a micro, I can make the board do > anything I want and even have different modes using the MCU EEPROM > rather than jumpers! NO JUMPERS!!! Isn't that great? > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55159
> The method is to just declare the actual signal, and tell Quartus that it > uses LVDS as the I/O standard (use the Assignment Organizer for this). > Quartus will then automatically pick two adjacent pins to implement the > signal. > Yes, it operates, thanks a lot. Sometimes its easier than thought at first :-) But in this case a have an other question. When i define some pins of e.g. bank 1 as lvds i/o (2,5V). All unused pins i can`t use for other i/o`s which use an other voltage, e.g. 3,3V, isn`t it? Best regardsArticle: 55160
Gilad Cohen <gilad_coh@walla.co.il> wrote: >>> html snarked by archive manager Please don't use HTML formatting in newsgroups. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 55161
Hallo, i have to design a logical circuit with different clocks. Some will connect throught the FPGA, some will be used in FPGA. Can I use every pin as clock input or output or is it critical? When I use the PLL there are defined inputs, i know, but what`s about the others? Best regardsArticle: 55162
Hi Jens, If you go to the Altera web site (www.altera.com), look at the Cyclone data sheet and go to the section entitled "Global Clock Network & Phase-Locked Loops". On the next page is a diagram showing the pins that can directly drive the clock network. There are a total of 12 such pins. 4 are dedicated "CLK" pins that can feed the PLL or clock network (and I think can be used as general inputs, but not outputs, if not used for clocking). 8 pins are "DPCLK" pins that connect to the clock network, or can be used as general I/Os. Some of the DPCLK pins can be passed through a programmable delay chain to generate DQS signals for DDR. It is possible to use a general I/O to drive the clock network of the chip, though there are only 8 GCLKs in the device so you're always better off using a clock pin. If you don't mind having a locally routed clock, then you can use a normal I/O as a clock without consuming a GCLK. However, you open yourself up to hold-time issues, and you will have skew between multiple destinations. Also, I *think* you may need to mark that net as being non-global in Quartus in order for it to be routed on local routing. Same goes for clock outputs -- you can pull a clock out of any I/O, either from the clock network or through local routing. But it depends on the quality and phase relationship you want between this signal and other signals on your chip. Can you give more information on what you are trying to do? Regards, Paul Leventis Altera Corp. "Jens Nowack" <its.me@uni.de> wrote in message news:b8lo26$bbkjo$1@ID-192450.news.dfncis.de... > Hallo, > > i have to design a logical circuit with different clocks. Some will connect > throught the FPGA, some will be used in FPGA. Can I use every pin as clock > input or output or is it critical? When I use the PLL there are defined > inputs, i know, but what`s about the others? > > Best regards > >Article: 55163
Excellent idea! I can slip in an OR gate between the NIOS CPU Flash WEn signal and the the output pin which connects to a port on the CPU. Then software can enable/disable the WEn signal to lock RAM. I wish I would have thought of that. Any idea where my original post went? This thread seems to have vanished down to your posting... hmurray@suespammers.org (Hal Murray) wrote in message news:<vasgfpf2nlq99e@corp.supernews.com>... > [trying to avoid accidently writing to Flash chip] > [external jumper] > > >The idea is that, as long as the WEn pin is not pulled to 0V, it's > >impossible to write into the Flash. This has to be done externally, as there > >is no other way you can 100% guarantee that your design will not happen to > >accidentally pull the signal low, attempt to write to the magic addresses > >etc, etc otherwise. > > Is there a separate pin on the FPGA that connects to the WEn on the Flash? > (as compared to a shared WEn that goes to Flash and RAM) If so, then > you are safe if you don't connect any logic to that pin. > > You are also reasonably safe if you just hack the logic in the design > so that writes to Flash address space get trapped or ignored.Article: 55164
hi, i have gone through some recent papers on "DIAGNOSIS AND FAULT TOLERACNE FOR FPGA". But i couldnt find any standard method to provide complete online fault tolerance techniques. the very fact that ther are different fpga architectures makes it difficult to standardise the techniques. most of them are very much biased towards xilinx based FPGA's. i will appreciate if anyone can give me any importance suggesitons or notes on this. thanx in advance naveenArticle: 55165
Hi Javier, I had exactly the same problem with an earlier version (license checking correct, vsim and vcom work, and dropping signals to wave crashes everything). I don't remember what I changed but to fix the problem, I just modified the license file and after that everything worked fine. So call modelsim tech support or try to remove some weird, redundant, unused stuff from your license file. good luck fe "yerbby" <yerbby@mixmail.com> wrote in message news:XMira.4429$FN3.452889@news.ono.com... > Hi everyone, > > I am trying to make Modelsim SE 5.7c (platform independent, floating > license) work with ISE 5.1i: > > license checking is correct, vcom works, vsim works, but droping signals to > wave window (or entering "log -r *" or "add wave *") crashes everything and > shutdowns all windows. > > BTW, the box is a PC with WinXP. > > Any suggestions are welcome. Thanks in advance. > ----------------------------------------------------------------------- > Javier Garrigos Guerrero > Departamento de Electronica, Tecnologia de Computadoras y Proyectos > E.T.S. de Ingenieros Industriales - Univ. Politecnica de Cartagena > Antiguo Hospital de Marina, C/Dr. Fleming s/n, 30202 CARTAGENA -SPAIN- > E-mail: yerby@ono-remove.com > ----------------------------------------------------------------------- > >Article: 55166
Hello folks, We are looking at buying a pair of RF transmitters/receivers to use in conjunction with two Xilinx Xtreme DSP Kits (http://www.xilinx.com/ipcenter/dsp/development_kit.htm). The transmission distance will be across a table/room at the most I would think so high frequency/power gear is not required. We just want to amplitude modulate a baseband/IF signal from the xilinx kit's DAC to some carrier frequency, receive it at the other side, demodulate and send it to the ADC of the other board. Has anyone done anything like this with these boards? Could anyone recommend any bits of RF kit that might do the job? All comments/"questions to fill in any inadvertant blanks of mine" much appreciated. Thanks for your time, KenArticle: 55167
Simon wrote: > > well.. actually its a sot23 5 pin package and costs 67c on the web site.. > and a digital output so it wouldn't be hard to fit :-) > considering it would shut down a standard temp micro, the micro cost saving > would satisfy the extra cost of a $1 FET and a 67c thermal switch. Or > better.. use a regulator with an on/off switch and just turn it on / off via > the thermal switch.. it can be fed from 2.7V to 5.5V after all. Is not that > silly if you add the pros and cons. Unless as you say the space will kill > ya.. but I've yet to see a board I couldn't squeeze the last square mm out > of (have been doing CAD for many a year) If you are really that good, maybe you can give me a price on doing my board. It is only 3.5" x 3.8" and most of the parts are on one side. But it is very dense. I have several BGAs the rest are tssops. I am hoping to keep the board to just 6 layers, but it may well need to be 8. I don't expect any three pin device will cause a 6 layer layout to fail, but I would rather focus on adding value to the board while keeping the layout as simple as possible. My main aversion to uses a thermal switch like you are suggesting is that it has a fixed cut off. The board I am designing is not for a single purpose. It is for a variety of applications. Using a micro will not cost more and will give me a lot more flexibility to tailor the board for special requests. EEPROM is a wonderful thing! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55168
Hi. I'm looking for a low-cost FPGA development board with an ADC & DAC for DSP applications. Could anyone recommend a REALLY low-cost one? :-) Thanks in advance, -- Brendan Lynskey Comodo Research Lab Click on www.comodogroup.com/secure-email to keep your emails confidential with a complementary FREE personal Secure Email CertificateArticle: 55169
I would like to use the DCM frequency synthesizer feature to multiply a input signal which frequency is less then 20MHz with 4. I do not need to deskew the signal (i.e. no fedback is needed). No other clock output will be used. How should I instantiate the DCM in my VHDL code? Which attributes should I apply? and where? (I use synplify for synthesis) Thanks! -- Patrik Eriksson | patrik.eriksson@netinsight.net Net Insight AB | phone: +46 8 685 04 89 Västberga Allé 9 | fax: +46 8 685 04 20 SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 55170
Peter Seng <p.seng@seng.de> wrote:
> look for dokumentation of "Parallel cable III" or "DLC5" download cable
> schematic at Xilinx. With this hardware and free available iMPACT software
> (included in ISE, can run under command line) You can program xc95xx easily.
"Where a programming device will not be available".
However, looking through application notes, I find that it's relatively
easy to do through the JDEC port.
I don't know why I diddn't find that on my first look at the website.
Thanks.
--
http://inquisitor.i.am/ | mailto:inquisitor@i.am | Ian Stirling.
---------------------------+-------------------------+--------------------------
"Melchett : Unhappily Blackadder, the Lord High Executioner is dead
Blackadder : Oh woe! Murdered of course.
Melchett : No, oddly enough no. They usually are but this one just got
careless one night and signed his name on the wrong dotted line.
They came for him while he slept." - Blackadder II
Article: 55171A few clbs in xilinx part, I guess. In old day I used to build those counters from FFs & gates. Implement a counter in virtex and open FPGA editor to see yourself, regard,Article: 55172
Patrick,
Provided you are using 5.1i or greater, you can use the Architecture Wizard
to generate the HDL code.
You can access it from ISE (Project-> New Source) or use it stand alone
(command: arwz).
Below I pasted an example of generated code (intended for Synplicity). The
wizard also calculates jitter for the CLKFX output.
Frederic Rivoallon.
-- Module dcm_example
-- Generated by Xilinx Architecture Wizard
-- VHDL
-- Written for synthesis tool: Synplicity
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-- synopsys translate_off
Library UNISIM;
use UNISIM.Vcomponents.all;
-- synopsys translate_on
entity dcm_example is
port (
RST_IN : in std_logic;
CLKIN_IN : in std_logic;
LOCKED_OUT : out std_logic;
CLKFX_OUT : out std_logic);
end dcm_example;
architecture STRUCT of dcm_example is
signal CLKIN_IBUFG : std_logic;
signal CLKFX_BUF : std_logic;
signal GND : std_logic;
component DCM
generic(
DFS_FREQUENCY_MODE : string := "LOW";
DLL_FREQUENCY_MODE : string := "LOW";
DUTY_CYCLE_CORRECTION : boolean := TRUE;
CLKIN_DIVIDE_BY_2 : boolean := FALSE;
CLK_FEEDBACK : string := "1X";
CLKOUT_PHASE_SHIFT : string := "NONE";
DSS_MODE : string := "NONE";
FACTORY_JF : bit_vector := X"C080";
STARTUP_WAIT : boolean := false;
PHASE_SHIFT : integer := 0;
CLKFX_MULTIPLY : integer := 4;
CLKFX_DIVIDE : integer := 1;
CLKDV_DIVIDE : real := 2.0;
CLKIN_PERIOD : real := 0.0;
DESKEW_ADJUST : string := "SYSTEM_SYNCHRONOUS"
);
port (
CLKIN : in std_logic;
CLKFB : in std_logic;
RST : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSCLK : in std_logic;
DSSEN : in std_logic;
CLK0 : out std_logic;
CLK90 : out std_logic;
CLK180 : out std_logic;
CLK270 : out std_logic;
CLKDV : out std_logic;
CLK2X : out std_logic;
CLK2X180 : out std_logic;
CLKFX : out std_logic;
CLKFX180 : out std_logic;
STATUS : out std_logic_vector (7 downto 0);
LOCKED : out std_logic;
PSDONE : out std_logic
);
end component;
component IBUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
component BUFG
port (
I : in std_logic;
O : out std_logic
);
end component;
begin
DCM_INST : DCM
Generic map (
CLK_FEEDBACK => "NONE",
CLKDV_DIVIDE => 2.0,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 50.0,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "LOW",
DLL_FREQUENCY_MODE => "LOW",
DUTY_CYCLE_CORRECTION => TRUE,
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLKIN => CLKIN_IBUFG,
CLKFB => GND,
RST => RST_IN,
PSEN => GND,
PSINCDEC => GND,
PSCLK => GND,
DSSEN => GND,
CLKFX => CLKFX_BUF,
LOCKED => LOCKED_OUT);
CLKIN_IBUFG_INST : IBUFG
port map (
I => CLKIN_IN,
O => CLKIN_IBUFG);
CLKFX_BUFG_INST : BUFG
port map (
I => CLKFX_BUF,
O => CLKFX_OUT);
GND <= '0';
end STRUCT;
Patrik Eriksson wrote:
> I would like to use the DCM frequency synthesizer feature to multiply a
> input signal which frequency is less then 20MHz with 4. I do not need to
> deskew the signal (i.e. no fedback is needed). No other clock output
> will be used. How should I instantiate the DCM in my VHDL code? Which
> attributes should I apply? and where? (I use synplify for synthesis)
>
> Thanks!
>
> --
> Patrik Eriksson | patrik.eriksson@netinsight.net
> Net Insight AB | phone: +46 8 685 04 89
> Västberga Allé 9 | fax: +46 8 685 04 20
> SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net
Article: 55173pramod@procsys.com (Pramod) wrote in message news:<a7c0720d.0304152101.581c85be@posting.google.com>... > Hi All, > I am new to this group and also to the field of FPGA based design. > I have some doubts and issues which I feel will be easy for you guys > to answer. > 1. For a 4 pole IIR Filter in FPGA (targeted device EP1C6), I have a > spec of 24 bit wide data input and > 32 bit wide coeff (dynamic) inputs. So, the multiplied results should > ideally have > 56 bits width. Are these widths practically relevant for a 4 pole > filter > or can we get an affordable precision with rounding to lower sizes? > If so, can anyone suggest a standard procedure for > rounding the results with lowest error and without causing the output > to become unstable? Pramod, You may want to check out the Confluence State Space Processor on OpenCores: http://www.opencores.org/projects/cf_ssp/ We built the core specifically for linear operations including: FIR filters, IIR filters, and general multi-variable state space calculations; all of which are common in DSP and control applications. The core is a processor with a very simple instruction set -- only 8 instructions -- for addition, shifting, sign-extending, limiting, and loading constant coefficients. Multiplication is performed by sign-extending the data, then performing a series of shifts and conditional adds on an accumulator. The processor is designed for simplicity and takes up very little area. Because the processor runs a program every sample period, it works well for applications where the clock rate is significantly faster that the sample rate of the discrete function. The architecture gives you 16 registers for I/O, intermediate calculation, and state variables. Constants are stored in an external memory with an 8-bit address giving you a possible total of 256 different coefficients. The State Space Processor core is generated from Confluence with configuration parameters of data width and instruction address width. If you don't see the configuration you need, let me know and I'll generate a custom processor for you. Regards, Tom -- Tom Hawkins Launchbird Design Systems, Inc. 952-200-3790 tom1@launchbird.com http://www.launchbird.com/Article: 55174
rickman wrote: > <snip> > If you are really that good, maybe you can give me a price on doing my > board. It is only 3.5" x 3.8" and most of the parts are on one side. > But it is very dense. I have several BGAs the rest are tssops. If it has this density, you will need to be more carefull with thermal budgets. It is not uncommon to get 20'C slopes on PCBs, and that can take your TA of 85'C down to 65'C. Seal it in a plastic box, and 40'C internal temp delta is not uncommon. Also on the Ta/Tj issues, and temp slopes - an example : If you take any device with Ta of 85'C, it will actually be running at a Tj (significantly) above that 10,20 or even 40'C higher. If you can find from the supplier what thermal load they rate for ( and that's often missing in the data), you can get thermal ceiling 'for free' by working under that load. eg suppose Cygnal allow a Tj-Ta of 20'C when applying their TaMAX of 85'C, Tj is really 105'C, and you can safely run to 105'C, if you can engineer a decrease in the thermal load from the die. You can buy a little more margin by tightening the Vcc specs, as they rate TaMAX as 'worst corner' operation. -jg
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