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yes .. the "Tex" is as a pattern generator. -----Original Message----- From: eric@ruckus.brouhaha.com [mailto:eric@ruckus.brouhaha.com]On Behalf Of Eric Smith Posted At: Wednesday, April 23, 2003 9:16 AM Posted To: fpga Conversation: Virtex2 and Logic Analyzer Subject: Re: Virtex2 and Logic Analyzer "Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> writes: > I have Xilinx virtex2-1000 and Textronix Logic Analyzer. The problem > is the TTL output level from my logic analyzer is 3.8 volt and the > maximum volatge to my Virtex2 is 3.3 volt. Are you using the Tek as a pattern generator or something? Normally a logic analyzer has *inputs*, not outputs.Article: 54951
Well... consider that if you use a single pair for bi-directional communication then you need a more complex protocol to change the direction of communication. Are you going to have additional side-band signals for clocking and control? Or, are you thinking that all clocking and control is embedded in the data? Is your application a single master and a single target, or multiple masters and multiple targets? TC "Joona R" <jonesky1@hotmail.com> wrote in message news:2f3990c3.0304212252.12923025@posting.google.com... > Hello! > > Hmm, I belive this is the same idea what I suggested by myself. Maybe > it's better to design PCB so that this way and using SSTL-2 (what Ben > told) are both possible to get in use. Then I could test which one > works better. > > Yours, > Joona R > > > "TC" <noone@noplace.com> wrote in message news:<b7vj5f$1gq$1@slb6.atl.mindspring.net>... > > Why not a dedicated pair of wires for transmitt, and a dedicated pair of > > wires for receive? > > > > TX in node A to RX in node B, TX in node B to RX in node A. A full-duplex > > connection. > > > > TC > > > > "Joona R" <jonesky1@hotmail.com> wrote in message > > news:2f3990c3.0304200441.5626b7b7@posting.google.com... > > > Hello! > > > > > > Can I use bidirectional mode with differential LVDS? Target device > > > will be Altera Cyclone. > > > I know there are two kinds of resistor connection for transmiter and > > > receiver (Altera application note 254, figure 3 on page 5 > > > http://www.altera.com/literature/an/an254.pdf ). > > > But I need a transreceiver. Should I use same connection as with > > > transmitter or something else? Or is only way to have transmitter and > > > receiver pins & resistors and then connect them to together? > > > > > > Thank you for your help! > > > > > > - JRArticle: 54952
I don't think I saw the original post... so sorry if I my comments/questions are repetitive. TC "Joona R" <jonesky1@hotmail.com> wrote in message news:2f3990c3.0304212252.12923025@posting.google.com... > Hello! > > Hmm, I belive this is the same idea what I suggested by myself. Maybe > it's better to design PCB so that this way and using SSTL-2 (what Ben > told) are both possible to get in use. Then I could test which one > works better. > > Yours, > Joona R > > > "TC" <noone@noplace.com> wrote in message news:<b7vj5f$1gq$1@slb6.atl.mindspring.net>... > > Why not a dedicated pair of wires for transmitt, and a dedicated pair of > > wires for receive? > > > > TX in node A to RX in node B, TX in node B to RX in node A. A full-duplex > > connection. > > > > TC > > > > "Joona R" <jonesky1@hotmail.com> wrote in message > > news:2f3990c3.0304200441.5626b7b7@posting.google.com... > > > Hello! > > > > > > Can I use bidirectional mode with differential LVDS? Target device > > > will be Altera Cyclone. > > > I know there are two kinds of resistor connection for transmiter and > > > receiver (Altera application note 254, figure 3 on page 5 > > > http://www.altera.com/literature/an/an254.pdf ). > > > But I need a transreceiver. Should I use same connection as with > > > transmitter or something else? Or is only way to have transmitter and > > > receiver pins & resistors and then connect them to together? > > > > > > Thank you for your help! > > > > > > - JRArticle: 54953
Xilinx is producing a version that will run on Linux, soon. That being said, I have no idea why anyone would want to run a business application on a home operating system. Go figure. "Loi Tran" <leotran@att.net> wrote in message news:NW_oa.72385$ja4.4813800@bgtnsc05-news.ops.worldnet.att.net... > > >Before you give up on installing Xilinx, did you find viewing the > >"agreement" would let you install the software? I can't imagine that > >Xilinx would *block* you from using this under another OS. > > I would if I could, but the policy isn't even displayed. > > >My suggestion: get over being ticked at Xilinx and find a way to upgrade > >your OS to Win2000 or even XP. Or maybe this is the nudge you need to > >switch to Linux! Before I will switch to XP, I will give Linux a > >serious go. Win2000 will be my last Microsoft OS. > > The reason why I'm still using Windows 98 is because I swore I would never buy > anything from M$ or M$ related again. You can stop groaning now (and thinking > I'm a cheapskate). I would pay for anything that's proven itself. The only > thing that Microsoft has proven is that it produces an inferior product and > claim superiority. I stop counting the number of times I've cursed and > sworn at a computer running Microsoft product (at work and at home). But > Webpack is the one thing I'd like to use and it isn't supported under Linux > except with WINE (which I don't want to USE). > > LT > >Article: 54954
Matt wrote: > Xilinx is producing a version that will run on Linux, soon. That being said, > I have no idea why anyone would want to run a business application on a home > operating system. Go figure. Most pieces of crap are created by 9-5ers. Just about anything M$, and most third-party apps i've come across. Linux is designed for technical superiority, with no commercial constraints. Business apps are nothing in comparison to the complexity and taxing of hardware of most modern games. Your precious business apps on windoze are running on hardware driven by an industry of games, internet porn, piracy, and criminal monopolies.Article: 54955
Matt wrote: > > Xilinx is producing a version that will run on Linux, soon. That being said, > I have no idea why anyone would want to run a business application on a home > operating system. Go figure. What exactly does that mean? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54956
Hi TC! What do you mean by complex protocol if single pair bidirectional? Complex to know when transmitting or receiving? In design there is one signal, which indicates direction so it is no problem. But if you mean complex to set LVDS to bidirectional because Quartus don't support it as Ben said in earlyer message, it may be then too complex. But Ben also suggested using SSTL-2 instead of normal differential pair. In my case, all clocking and control are embedded in data and there is only one master and one slave. Or should I say two slaves, I'm a slave too... This is part of my final year project and I get no money of this.. =) =) - Joona "TC" <noone@noplace.com> wrote in message news:<b84s49$blk$1@slb2.atl.mindspring.net>... > Well... consider that if you use a single pair for bi-directional > communication then you need a more complex protocol to change the direction > of communication. Are you going to have additional side-band signals for > clocking and control? Or, are you thinking that all clocking and control is > embedded in the data? Is your application a single master and a single > target, or multiple masters and multiple targets? > > TC > > > "Joona R" <jonesky1@hotmail.com> wrote in message > news:2f3990c3.0304212252.12923025@posting.google.com... > > Hello! > > > > Hmm, I belive this is the same idea what I suggested by myself. Maybe > > it's better to design PCB so that this way and using SSTL-2 (what Ben > > told) are both possible to get in use. Then I could test which one > > works better. > > > > Yours, > > Joona R > > > > > > "TC" <noone@noplace.com> wrote in message > news:<b7vj5f$1gq$1@slb6.atl.mindspring.net>... > > > Why not a dedicated pair of wires for transmitt, and a dedicated pair of > > > wires for receive? > > > > > > TX in node A to RX in node B, TX in node B to RX in node A. A > full-duplex > > > connection. > > > > > > TC > > > > > > "Joona R" <jonesky1@hotmail.com> wrote in message > > > news:2f3990c3.0304200441.5626b7b7@posting.google.com... > > > > Hello! > > > > > > > > Can I use bidirectional mode with differential LVDS? Target device > > > > will be Altera Cyclone. > > > > I know there are two kinds of resistor connection for transmiter and > > > > receiver (Altera application note 254, figure 3 on page 5 > > > > http://www.altera.com/literature/an/an254.pdf ). > > > > But I need a transreceiver. Should I use same connection as with > > > > transmitter or something else? Or is only way to have transmitter and > > > > receiver pins & resistors and then connect them to together? > > > > > > > > Thank you for your help! > > > > > > > > - JRArticle: 54957
I think I did understand your message wrong, sorrys are mine! I though you talk about same thing when I was said this: "Or is only way to have transmitter and receiver pins & resistors and then connect them to together?" But now I belive I know what you mean, that there is really two differential pairs to have bidirectional transfer. It is a good idea, but it is not possible. The device which I design is handling a custom made ASIC and it has only bidirectional differential pairs already, so it is hard to change this anymore. - Joona "TC" <noone@noplace.com> wrote in message news:<b84s69$5jq$1@slb6.atl.mindspring.net>... > I don't think I saw the original post... so sorry if I my comments/questions > are repetitive. > > TC > > "Joona R" <jonesky1@hotmail.com> wrote in message > news:2f3990c3.0304212252.12923025@posting.google.com... > > Hello! > > > > Hmm, I belive this is the same idea what I suggested by myself. Maybe > > it's better to design PCB so that this way and using SSTL-2 (what Ben > > told) are both possible to get in use. Then I could test which one > > works better. > > > > Yours, > > Joona R > > > > > > "TC" <noone@noplace.com> wrote in message > news:<b7vj5f$1gq$1@slb6.atl.mindspring.net>... > > > Why not a dedicated pair of wires for transmitt, and a dedicated pair of > > > wires for receive? > > > > > > TX in node A to RX in node B, TX in node B to RX in node A. A > full-duplex > > > connection. > > > > > > TC > > > > > > "Joona R" <jonesky1@hotmail.com> wrote in message > > > news:2f3990c3.0304200441.5626b7b7@posting.google.com... > > > > Hello! > > > > > > > > Can I use bidirectional mode with differential LVDS? Target device > > > > will be Altera Cyclone. > > > > I know there are two kinds of resistor connection for transmiter and > > > > receiver (Altera application note 254, figure 3 on page 5 > > > > http://www.altera.com/literature/an/an254.pdf ). > > > > But I need a transreceiver. Should I use same connection as with > > > > transmitter or something else? Or is only way to have transmitter and > > > > receiver pins & resistors and then connect them to together? > > > > > > > > Thank you for your help! > > > > > > > > - JRArticle: 54958
What is the bandwidth and access latency you need?
In PC system, PCI interface and USB2.0 interface can support you get high
speed data access.
Serial port and Parallel port can support your application with low speed
data access.
And to implement different interface protocol need different logic elements,
from 100LEs to 3000LEs.
Best Regards,
Joshua Yin
2003.04.23
"Mansoor Naseer" <mansoor@su.sabanciuniv.edu> wrote in message
news:e78a6df0.0304120940.38226fb1@posting.google.com...
> > Hello,
> >
> > I have implemented an algorithm on a FPGA (Xilinx XC4010). Now the
> > problem is with the development board. Though it is convenient when it
> > comes to downloading the bit stream from the computer, the problem is
> > it is too bulky. The development board has additional LED, some more
> > ports etc which I dont need. The only things I need and use is the
> > FPGA, a parallel printer port for dumping information onto FPGA and
> > memory. Therefore, I want to transfer the FPGA onto a PCB alongwith
> > some memory (~10MB). The memory should be loadable from the computer
> > directly, otherwise the FPGA should be able to read the memory and
> > should be able to write to it.
> >
> > Since I am totally new to this area, I can only reckon a guess that I
> > would require a micro controller which gets programmed from flash
> > memory each time the device is activated, which will contain all the
> > handshaking protocols. But what components are there which can do this
> > job with least effort expended? Any ideas on this? Any pointers in
> > general to put me on a track would be appreciated.
Article: 54959Hi, I want to start my first application for the EPXA1 development board using the GNUPro Toolchain. Unfortunalty I have some troubles with the linking sequence. It would be nice, if someone could give me a hint. I studied the "hello" example from the getting started demo and found, that the way the project is build differs from the way described in Application Note 244 (Using Run-From-Flash Mode with Excalibur Bootloader). In the getting stared demo the user code is linked to a relocatable .elf file, conferted to .hex and this file is used as input file to makeprofile > C:\quartus/bin/makeprogfile -m memory -q -b Release/hello_bootdata.o hello.sbd hello.sbi Release/hello.hex The AN244 shows an example where the makeprogfile is called whith the .sbi and .sbi file, omitting the .hex. Linking user code with boot code is done later. I like the way described in the AN244 because makeprogfile runs under Windows, while the rest of our development is done under Linux. Thus I prevere a fixed boot file. However I have no idea where to place the ___altera_user_start and what this -entry=___altera_entry stuff means. It seems, that if makeprogfile is called without a .hex file it produce code which needs an ___altera_user_start symbol, otherwise it does it implicit. Could someone explain me that "magic" build process in more detail or provide me with a very simple "hello world" example which is build the AN244 way? Best regards, Franz E-Mail: hollerer@decomsys.comArticle: 54960
Pliers!
HaHa!
Good joke!
In fact, CPLD's mini package is UBGA49, 7mm*7mm.
CPLD, such as EPM3032ALC44, is very cheap(less than $1) now and can be
configured by JTAG.
A master logic engineer can finish such a low density HDL design in several
minutes.
Do you really need a microcontroller?
Altera, Xilinx also supply free design tools on the website.
--
Best Regards,
Joshua Yin
2003.04.23
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:3EA38EBA.DBCADBE9@yahoo.com...
> Falk Brunner wrote:
> >
> > "Ian Hickey" <ihickey@ieee.org> schrieb im Newsbeitrag
> > news:3ea276da$1@clear.net.nz...
> > > Does any manufacturer make a very small programmable logic device
(with
> > > FLASH storage) is say a SOIC-8 or similar.
> > >
> > > It's for a small home project that only has one output and only one
input
> > > (plus CLK)
> >
> > AFAIK no. The smallest pincount for CPLDs/FPGAs is somewhere at 44 pins.
If
> > you need such a small logic device, and the speed requirements are not
too
> > high, you may use a microcontroller. They are available in such small
> > packages, e.g. ATMEL offers them (AVR devices)
>
> I know a way to convert a 44 pin QFP into a much lower pin count
> device. You will still need the power, ground and config signals, but I
> can cut the IO down to the two the OP needs.... where are my pliers?
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
Article: 54961valentin tihomirov wrote: > I have an idea to implement all digital logic of my circuit into a CPLD. The > only doubt is external UART. I know, additional UART is a big pain, > currently I use tl16c750. I think that a price of external uart is the same > or greater than an average CPLD chip. All IP cores suggested by google are > complex, ie with FIFOs and flow control. I would be satisfied with the > 8051-compatible UART. That means an interrupt, 8bit SIN, SOUT registers, TI, > RI flags and a hardwired frecuency. Any suggestions. > > > We have implemented such an UART some time ago in a XC9500XL CPLD to program a parallel Flash device which is used to boot a VitexE FPGA. It works fine for us at fixed 115.2k , 8N1, full duplex communication. With a matching clock frequency (i.e. 1.834 MHz) it takes 43 registered Macrocells, for a higher input frequency you have to add some FFs for a clock divider. Mail me privately if you are interested in the sources. JensArticle: 54962
Generate an LPM_RAM (or one of its variants) using the MegaWizard. It will prompt you for the name of a .mif file which will contain the initial contents of the RAM block. -Peter Stein Kjølstad wrote: > > Hi, > > I would like to know if there is a way to put initial values to > internal RAM defined in VHDL. I'm not using technological primitives. > I'm using Quartus 2 as synthesis tool. > > Thanks > Stein K -- Peter April VPixx Technologies Inc. Phone: 450-922-1635 Fax: 450-922-5173 Email: peter@vpixx.com Web: http://www.vpixx.comArticle: 54963
I suggest you select HEX file to fill the content.
Most of EDA tool can support HEX file better.
--
Best Regards,
Joshua Yin
2003.04.23
"Peter April" <vpixx@videotron.ca> wrote in message
news:3EA65AB6.E3EB3EBC@videotron.ca...
>
> Generate an LPM_RAM (or one of its variants) using the MegaWizard. It
> will prompt you for the name of a .mif file which will contain the
> initial contents of the RAM block.
>
> -Peter
>
> Stein Kjølstad wrote:
> >
> > Hi,
> >
> > I would like to know if there is a way to put initial values to
> > internal RAM defined in VHDL. I'm not using technological primitives.
> > I'm using Quartus 2 as synthesis tool.
> >
> > Thanks
> > Stein K
>
> --
>
> Peter April
> VPixx Technologies Inc.
> Phone: 450-922-1635
> Fax: 450-922-5173
> Email: peter@vpixx.com
> Web: http://www.vpixx.com
Article: 54964On Wed, 23 Apr 2003 16:57:29 +0800, "Joshua Yin" <joshuayin@cytecht.com> wrote: >Pliers! >HaHa! >Good joke! > >In fact, CPLD's mini package is UBGA49, 7mm*7mm. >CPLD, such as EPM3032ALC44, is very cheap(less than $1) now and can be >configured by JTAG. >configured by JTAG. >A master logic engineer can finish such a low density HDL design in several >minutes. ..and a decent programmer could also do a suitably simple design in comparable time. >Do you really need a microcontroller? I think the fact that we don't see low pin-count PLDs is that for the vast majority of applications that might use one, a micro is a better solution, in terms of cost, flexibility, functionality and power consumption. In most cases the argument would be 'do you really need a PLD?' Micros are infinitely more flexible and powerful, usually take a lot less power, and the only reason to use a PLD is that a micro isn't fast enough.Article: 54965
Hi, When calculating an FFT, how does the inclusion of the DC value affect things i.e. I have seen some examples of FFT code where the DC is removed and some where it left. Is the best strategy to remove the DC or leave it. For example in a COFDM system, will its removal or inclusion have any effect? I am thinking of its implementation in an ASIC, where DC removal adds overhead and I'm wondering if it really necessary to remove it. How will adding removing the DC level affect the ifft? Thank you BobArticle: 54966
I hope that somebody can help me with this ? I have a small design which uses instantiated SRL16 primitves. The design simulates fine with webpack 4.2 and the 'matching' modelsim simulator, but generates loads of timing errors with the latest set of tools. The timing errors all seem to be caused by the SRL16 primitives. Has anybody come across this and can tell me why this happens and how to fix it ? Thanks for your help in advance, - Frank PS: to send no-spam email, replace "xxx" with "eng" and "yyy" with "cam". ================================================== Frank Hoffmann Laboratory for Communication Engineering (LCE) University of Cambridge - Dept. of Engineering William Gates Building, JJ Thomson Avenue, Cambridge, CB3 0FD, UK phone : +44 1223 767031 fax : +44 1223 767010 ==================================================Article: 54967
hi all, I am presently working on hardware implementation of viterbi decoder with constraint length K=7 with soft decision width = 3. It would be very helpful to me if the knowledgable persons can answer my doubts regarding the issues: 1. The ACS modules (64 in number in my case) are taking most of the area. Some documents mention of modified ACS units. But i couldnot get those documents as they were preveliged for ieee members. 2. To avoid the overflowing of partial path metric values, i am doing normalisation i.e., subtracting the lowest value from all the partial path metric values. Some documents mention about "localised normalisation". How does that work. 3. After survival data equal to trace back deapth has been stored, we start trace back. If we are to start the traceback with lowest partial path metric, how do we determine that state if we do "localised normalisation" 4. What are the different techniques for trace back operation ? Since i am implementing it on hardware, functionality, area and timing all are very important. expecting reply, regards, VikasArticle: 54968
The error message prints in hex huh? Well that's probably worth knowing. That explains IRQ 17 and 19 (timer and lan respectively) Is it possible to receive a spurious interrupt for an IRQ not assigned in SOPC Builder. I recall having a spurious IRQ #1, although I may have been mistaken. You mention that IRQs 16-64 are for user exceptions. What about IRQs 1-15 ? kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0304221410.52a9616@posting.google.com>... > Actually 3.01 is the latest release (includes example designs for both > Cyclone and Stratix dev. boards). Nios 3.0 is nearly identical, but > without the example designs for the Cyclone dev. boards. > > On the spurious interrupts: A spurious interrupt occurs when > interrupts are enabled, IRQ is asserted, and the interrupt source (IRQ > number) does *not* have a proper entry in the vector table... in > short, the interrupt hasn't been initialized in software, and there is > nowhere for the CPU to jump to. The spurious interrupt handler > provides a default piece of code to execute in this case (prints out > "Spurious interrupt number <#>" over stdout). > > One potentially confusing 'gotcha' is that in the SOPC Builder > peripheral table where you assign an IRQ number (16-64 for user > exceptions), the assignment is decimal. The spurious interrupt message > is printed in hex. Thus, 11 would be 17 in your list of peripherals, > and 13 would be 19.... I bet each of these has a peripheral associated > with it! > > One other note is that if one of these is an ethernet adapter - have > you based your design on one of the examples? If not, check on the > top-level schematic and note our "spurious interrupt" prevention > circuit, basically an SR flop which prevents interrupts from an > external Ethernet MAC until the software has written out to the chip. > You can apply this to other off-chip components which may be giving > you spurious interrupts as well. > > Jesse Kempa > Altera Corp. > jkempa @ altera dot com > > > > > "Stefaan Vanheesbeke" <stefaan.vanheesbeke@pandora.be> wrote in message news:<uoepa.57094$t_2.5131@afrodite.telenet-ops.be>... > > Is Nios 3.0 already available? > > > > I thought 2.2 was the latest version. > > > > Normally, if you have a sputiuos interrupt in Nios, it says soehting like > > "spurious interrupts", but you can disable this in the SOPC builder. > > > > The source for this must be found in the lib directory. I suppose it will be > > in an assembly file (*.s). If I'm back at my office, I will take a look > > where it is. > > > > > > "Jim M." <jim006@att.net> schreef in bericht > > news:6f3fc0f8.0304211607.3f68f848@posting.google.com... > > > Here's a tough one: > > > > > > Where can I find the source of NIOS CPU interrupts not assigned in > > > SOPC Builder? > > > > > > If I trap interrupts, I tend to capture #1, #11, and #13 during LAN > > > traffic. These are bad enough to create an infinite reset loop > > > (probably because the interrupt source has not been cleared). > > > > > > Examination of my SOPC Builder NIOS design shows that IRQ #'s are > > > assigned to my components starting at 16 and increasing from there. > > > > > > Also, if I disable "capture spurious interrupts" in the NIOS CPU, am I > > > preventing the interrupts from occurring or are they eating CPU cycles > > > and I just can't see it? > > > > > > I haven't been able track down this information using the Altera > > > Knowledge Base. Looking for some help on this one. > > > > > > Thanks! > > > > > > JimArticle: 54969
The clock to Y timing of the SRL16 is not very impressive. You make things
work much better if you feed the output of the SRL16 directly to the
flip-flop in the same slice before using it. It adds one more clock delay,
but eliminates the extra routing and FF set up.
Frank Hoffmann wrote:
> I hope that somebody can help me with this ?
>
> I have a small design which uses instantiated SRL16 primitves.
>
> The design simulates fine with webpack 4.2 and the 'matching' modelsim
> simulator, but generates loads of timing errors with the latest set of
> tools. The timing errors all seem to be caused by the SRL16 primitives.
>
> Has anybody come across this and can tell me why this happens and how to
> fix it ?
>
> Thanks for your help in advance,
>
> - Frank
>
> PS:
> to send no-spam email, replace "xxx" with "eng" and "yyy" with "cam".
>
> ==================================================
> Frank Hoffmann
>
> Laboratory for Communication Engineering (LCE)
> University of Cambridge - Dept. of Engineering
> William Gates Building, JJ Thomson Avenue,
> Cambridge, CB3 0FD, UK
>
> phone : +44 1223 767031 fax : +44 1223 767010
> ==================================================
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54970
Weifeng Xu <wxu@ecs.umass.edu> wrote in message news:<3EA426B0.619DFBCD@ecs.umass.edu>...
> .bit or .hex are both configuration files, .hex is a format transferred
> from .bit.
> Good Luck!
>
> Weifeng
Excuse me, Is there any documentation about the bitstream file format?
I am wondering in this. thanks.
Fan.
>
> >
> > THANX IN ADVANCE
> > NAVEEN
Article: 54971Hi- thanks for that tip. I'll investigate it, but I wonder whether this is the reason for the unexplained errors I'm getting ? Mind you, the identical design was simulating without any errors in the older version of tools ? - Frank Ray Andraka wrote: > The clock to Y timing of the SRL16 is not very impressive. You make things > work much better if you feed the output of the SRL16 directly to the > flip-flop in the same slice before using it. It adds one more clock delay, > but eliminates the extra routing and FF set up. > > Frank Hoffmann wrote: > > >>I hope that somebody can help me with this ? >> >>I have a small design which uses instantiated SRL16 primitves. >> >>The design simulates fine with webpack 4.2 and the 'matching' modelsim >>simulator, but generates loads of timing errors with the latest set of >>tools. The timing errors all seem to be caused by the SRL16 primitives. >> >>Has anybody come across this and can tell me why this happens and how to >>fix it ? >> >>Thanks for your help in advance, >> >>- Frank >> >>PS: >>to send no-spam email, replace "xxx" with "eng" and "yyy" with "cam". >> >>================================================== >>Frank Hoffmann >> >>Laboratory for Communication Engineering (LCE) >>University of Cambridge - Dept. of Engineering >>William Gates Building, JJ Thomson Avenue, >>Cambridge, CB3 0FD, UK >> >>phone : +44 1223 767031 fax : +44 1223 767010 >>================================================== > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 54972
It was so close: 1.2V core voltage. In my current design I'm going to use processor with 1.26V core voltage;) It would be nice to have one regulator less... -- Robert PudlikArticle: 54973
Robert, The abs max limit for Vccint is 1.32V, and the recommended top Vccint is 1.26 volts. I see no reason why you couldn't use one supply as long as you are careful to be sure the regulation is good enough to stay within the bounds above. If it were me, I would use something like 1.24v for both and be sure I was less than +/- .3V for overall regulation/variation in the power supply.... Of course, at these voltages, if you are pulling any real current, the actual voltage will be less at the part due to IR drop on the pcb. That would be too tricky to design, but might add to your margins. Austin Robert wrote: > It was so close: 1.2V core voltage. > In my current design I'm going to use processor with 1.26V core > voltage;) It would be nice to have one regulator less... > > -- > Robert PudlikArticle: 54974
Matt wrote: > Xilinx is producing a version that will run on Linux, soon. That being said, > I have no idea why anyone would want to run a business application on a home > operating system. Go figure. You are correct, you don't have any idea...
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