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Loi Tran wrote: > > >Before you give up on installing Xilinx, did you find viewing the > >"agreement" would let you install the software? I can't imagine that > >Xilinx would *block* you from using this under another OS. > > I would if I could, but the policy isn't even displayed. I am certain that you are looking at a problem *other* than the software being locked out of being installed on Win98. This may in fact be a problem that comes from incompatibility with Win98. Just to see if it *will* install, try it on a different PC. > >My suggestion: get over being ticked at Xilinx and find a way to upgrade > >your OS to Win2000 or even XP. Or maybe this is the nudge you need to > >switch to Linux! Before I will switch to XP, I will give Linux a > >serious go. Win2000 will be my last Microsoft OS. > > The reason why I'm still using Windows 98 is because I swore I would never buy > anything from M$ or M$ related again. You can stop groaning now (and thinking > I'm a cheapskate). I would pay for anything that's proven itself. The only > thing that Microsoft has proven is that it produces an inferior product and > claim superiority. I stop counting the number of times I've cursed and > sworn at a computer running Microsoft product (at work and at home). But > Webpack is the one thing I'd like to use and it isn't supported under Linux > except with WINE (which I don't want to USE). I understand how you feel. But the bottom line is do *you* benefit from using WebPack under Win2000? Also, I don't think *any* of the Xilinx tools are supported to run *native* under Linix. They are supported to run under WINE. I assume that they don't provide this level of support for Webpack because it is just too small a splinter group to support with a free tool. Heck, I am happy to have a free tool available to allow my customers to roll their own designs without a major tool purchase. I am looking at using a combined MCU/FPGA part from Atmel and they want $500 for the *eval* kit! I have to say I don't get that! The fact that the Xilinx Webpack only runs under Windows 2000 or XP is a small sacrafice to pay for free tools (as in beer). -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54926
I've worked with various tools since FPGA's first appeared. You can't beat the price and performance of the software provided by Xilinx or Altera. Their software may have bugs, but you can usually work around them. If the vendor put as much effort to make the perfect software product you wanted. You wouldn't be able to afford it. Has it stands, the high end software tools cost $10,000 to $20,000+. Altera and Xilinx provide these tools as a low cost alternative, to help promote their sales. If you can't deal with it, put up the big bucks and buy the good software. Don't ruin a good thing for the rest of us. billh40@aol.com (Bill Hanna) wrote in news:97d137ce.0304171001.5ec5461d@posting.google.com: > I have been designing a Digital Signal Processor using the XC2V4000 > chip. > Software errors in ISE 4.2 and 5.1 have caused long hours of delay in > developing the design: > > Software bugs in SystemAce causes erase problems in the MPM. > Deleting signal wires in ECS causes Fatal errors that crash the > system. > A large design exceeds the 2GB memory limit and generates a fatal > memory error. > > I have designed Altera chips for over 6 years and never had a > problem. > > All digital designers should stop designing new projects with > Xilinx ICs until Xilinx corrects all software problems with ISE. > > Bill HannaArticle: 54927
DUBOSSE Thierry wrote: > > Hi, > > "B. Joshua Rosen" a écrit : > > > Why should Xilinx support a broken OS like Win98 when Microsoft no longer > > supports it? If you feel compelled to use a Microsoft OS then use a > > current version like XP or 2K. > > Are you sure that Microsoft is no longer supporting Win98 ? > Please visit : > http://www.microsoft.com/windows98/ > > Very interresting !!! ;*D I think someone made a mistake. It is Win95 that MS dropped support on. I know that is what I was using. :( Actually I am glad to be rid of that POS. I don't know how many bugs the OS had, but apps under it would take it down in a heartbeat. Win2000 is much, much more reliable. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54928
rAinStorms wrote: > > I am saying that as a volume manufacturer we have not yet seen Xilinx "come > to the table" on the new volume price breaks avaiable. I am sure they will > ... if the they live up to their press in the near future. > > You cant relate low volume un negotiated pricing to those of high volume > manufacture. You cannot also guage any reasonable comparison as there are so > many factors you cant account for. The table presented did that it seemed. I agree. That was my point also. The discounted prices are a function of costs of manufacturing and business models. The list prices are just marketing. Since Cyclone is the new chip, the list prices are designed to pit a better Cyclone part against a smaller XC2S part on equal price or to show a lower price on equal performance. But many of us don't get the big breaks that high volume users get. So the list prices are a good comparison even if they are not exactly what we will pay. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54929
Go to Xilinx site, click on support so you reach xilinx.support.com! There type 10235 into the search box(under Answer Database) to look for Answer Record #10235. It refers to a similar problem as yours. In short this error is generated when NGDBuild cannot find the netlist of the core you generated in your code ( it seems to me that you generated mac_fir as a core and something is wrong with this core ). Regards, Dan Radut paraagv@hotmail.com (paraag) wrote in message news:<39fdcd07.0304210834.5932a99c@posting.google.com>... > when i Translate my top level code i get this type of an error > > > ERROR:NgdBuild:604 - logical block 'filtercore' with type 'mac_fir' could not be > resolved. A pin name misspelling can cause this, a missing edif or ngc file, > or the misspelling of a type name. Symbol 'mac_fir' is not supported in > target 'virtex'. > > > can anyone tell me what it is???/ > > thanks paraagArticle: 54930
Luiz Carlos wrote: > > Hi Steven. > > If, as you said, > > At the low end of the density range, packaging and test costs dominate > > the end-user price. > Then: > Why there is no some block RAM/multipliers and DCMs in the XC3S50? > Why did Xilinx make the Spartan-3 "ugly duck"? > > I work for a design house (hardware and firmware), and in almost all > our designs we use FPGAs and need memory blocks. > > Yes, I live in Brazil, and I know BP&M, but I´d like to talk to the > child´s parents! Functions like multipliers and block rams have to be tested. I expect they add a noticable time to the test cycle. I was touring the Atmel plant once and was shown the automated test equipment they use on some of their very small parts. The machine was spending only a few seconds on each part. But because of the cost of the machine, that was a buck or so of time considering the lifetime of the machine and the initital cost. Guess what, the chips sold for a buck or so in large quantities! In essence when you buy small parts in large quantities you are renting test time on their machines!!! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54931
Hi Stein, > I would like to know if there is a way to put initial values to > internal RAM defined in VHDL. I'm not using technological primitives. > I'm using Quartus 2 as synthesis tool. Perhaps you should treat your RAM like a register (i.e. D-FlipFlop). That is, you initialize the array during reset with your desired initial values. However, be aware that the synthesis results are far from optimal. I doubt that the synthesis tool will map your RAM into a RAM-block (if one is available). Rather each RAM cell will end up as D-FlipFlop. Regards, MarioArticle: 54932
Is Nios 3.0 already available? I thought 2.2 was the latest version. Normally, if you have a sputiuos interrupt in Nios, it says soehting like "spurious interrupts", but you can disable this in the SOPC builder. The source for this must be found in the lib directory. I suppose it will be in an assembly file (*.s). If I'm back at my office, I will take a look where it is. "Jim M." <jim006@att.net> schreef in bericht news:6f3fc0f8.0304211607.3f68f848@posting.google.com... > Here's a tough one: > > Where can I find the source of NIOS CPU interrupts not assigned in > SOPC Builder? > > If I trap interrupts, I tend to capture #1, #11, and #13 during LAN > traffic. These are bad enough to create an infinite reset loop > (probably because the interrupt source has not been cleared). > > Examination of my SOPC Builder NIOS design shows that IRQ #'s are > assigned to my components starting at 16 and increasing from there. > > Also, if I disable "capture spurious interrupts" in the NIOS CPU, am I > preventing the interrupts from occurring or are they eating CPU cycles > and I just can't see it? > > I haven't been able track down this information using the Altera > Knowledge Base. Looking for some help on this one. > > Thanks! > > JimArticle: 54933
On Mon, 21 Apr 2003 18:57:11 -0400, Dave wrote: > B. Joshua Rosen wrote: >> >> Why should Xilinx support a broken OS like Win98 when Microsoft no >> longer supports it? If you feel compelled to use a Microsoft OS then >> use a current version like XP or 2K. > > If they don't support it, how is it that I can go to any local computer > retailer and pick up a copy of 98SE--at the same price as XP on the > shelf next to it? > > > -=Dave=- I did a little looking and Microsoft, which planned to kill 98 last year, has extended the date to June of this year. There may be some support for security patches on a case by case basis until Jan 2004, then that's it. The fact remains that Win9X is a miserably excuse for an operating system. It has a mean time between crashes of about 6 minutes and Windows in general, including the semi stable versions like Win2K and WinXP, is a lousy environment for doing any serious engineering work. Xilinx can't go on supporting obsolete operating systems forever, they did the right thing by dropping Win98.Article: 54934
Well, I've finished up a couple NIOS designs and here's the Fmax values I obtained for a couple configurations: SETUP 1 -- 90 MHz (1S10-C6ES), slack +500ps 32-bit NIOS CPU without instruction/data cache and with button input, led output, lcd output, sram, flash, ethernet, 1 uart, 1 dma, and some custom logic interfaces. This design had a positive slack time of nearly 500 ps suggesting that 95 MHz is probably possible. I tried 100 MHz and had a negative slack time of nearly 500 ps. SETUP 2 -- 90 MHz (1S10-C6ES), slack +50ps Same as #1 with addition of SDRAM controller. No LogicLock regions used in design. In addition, I still experience a repeated fast fit during compilation in Quartus. I'm not sure why this happens, but it occurs after any change to the design. The first compile after a change results in a database build, logic synthesis (using previous fitter results from database), then a repeated fast-fit. I let one of these fast-fit sessions run itself out and it took about 11 hours. It built up 100-200 entries in the database. I received some pretty nice results due to the 11 hour build. Now when I see the repeated fast-fit occurring, I stop the build after the first fit then re-build. The rebuild skips the database builder and logic synthesizer (since smart compile is enabled) and performs a final fit (not fast-fit). I thought I'd post my final results. jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0304141222.15bf1ca8@posting.google.com>... > I recently purchased a NIOS Stratix 1S10 Development Kit from Altera > and have mixed feelings about Quartus, SOPC Builder, and the NIOS > Core. (For those poor souls interested, I've included some comments > at the end of this post... feel free to provide feedback.) > > However, here's my question: > > What's the maximum clock frequency anyone has achieved using the NIOS > 3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM, > Ethernet, PIO, UART, etc. as in the Reference Design provided by > Altera)? > > I've tried isolating the various components into LogicLock regions. > I've tried different fitter/netlist optimizations. The maximum Fmax I > have achieved to date is 80 MHz. This is after letting Quartus "fit" > for 10 hours... it actually didn't stop, I had to abort the fitting > and refit to finially get an interim result (see other misc comments > below). > > Altera advertises 125 MHz for the Stratix Device and NIOS 3.0... > However a reference design that builds at that clock rate is not > provided. It appears that Altera gives you just enough to get your > feet wet... anything above and beyond that is Intellectual Property > that you need to buy. > > Other Observations/Comments: > > 1. The Quartus II SP1 software is extremely flakey. I've generated > numerous faults when deleting/modifying child LogicLock Regions. It > also takes forever to fit my Stratix design which is only 6000 LEs. > If I select the "limit fitting attempts to 1" option, Quartus > sometimes fits many times (like forever...) why?!?!? Also, after a > design is finished building, the software sits around for up to 5 > minutes before it generates a "finished" dialog box. I'm not sure > what's going on between the Quartus Application thread and the Quartus > Compiler thread, but it's fustrating enough just waiting for the > design to build, let alone waiting for Quartus to figure out the build > is done. I could go on and on, and that's only the result of 4 weeks > of effort with a small design. I feel sorry for those folks working > on a 100,000+ gate design. I guess modularity is the key there. > > 2. I can't simulate designs with virtual pins. I get warning during > the analysis of the simulation and then receive results with all input > pins a zero and output pins undefined. In addition, I can generate > hold time warnings during simulation for a design that didn't compile > with any hold time warnings. I'm not talking about hold time warnings > on my input signals, I'm talking about hold time warnings on internal > registers in my verilog code. Registers that I've taken care to hold > for 1 or more clock cycles before using in other parts of the design. > Again, the compilation of the design did not generate hold time > warnings... only the simulation of the design. > > 3. PLLs generate different timing analysis results. THIS IS VERY > ANNOYING! When I build up a "black-bock" design with virtual pins I > obtain a Fmax calculation from the timing analysis routine. I then > LogicLock the design and export it. When I import the design into a > new project and clock it using a PLL it generates negative slack time > warnings! If I remove the PLL and replace it with a clock pin, I get > the Fmax result that I obtained during the "black box" design. I beat > myself up for a week trying to debug a design that wasn't broken > because of this goofy behavior in Quartus. I'm still not sure if the > slack time warning it legit and wether I should be concerned about it. > > 4. SOPC Builder will lock itself up if you double-click components > before selecting them. Give it a try... double click a component line > in your NIOS design before selecting the line item. After a couple > times the SOPC builder application creeps to a halt. > > 5. Documentation on the various megafunctions is lacking. A good > example is the altsyncram megafunction. It doesn't state any timing > requirements on the input registers, enable, and clock signals. Do I > hold the data 1 cycle before flipping the write enable? How about > holding the write enable before de-activating it? Why is the > addressing based upon the data bit-width? Trying to tie a 32-bit > altsyncram block to a NIOS CPU is difficult because you need to > specify the address space of the peripheral and the address space of > the altsyncram block is based upon the bit width (not the number of > bytes). > > 6. I have yet to get a Leonaro-Spectrum synthesized Verilog file to > build in Quartus. I can used Spectrum generated .edf files but not > verilog. I get LCELL parameter errors. Unfortunately, Altera can't > seem to duplicate this... anyone else see this behavior? I'm not sure > if Spectrum synthesizes Verilog better that Quartus, but it definitely > does it faster. > > Feedback is welcome... even if it's the "you're an idiot and here's > why" variety...Article: 54935
"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag news:3EA553E3.BDF0A41@yahoo.com... > In essence when you buy small parts in large quantities you are renting > test time on their machines!!! So whats the alternative? Buy untested chips for half the price? ;-)) SCNR. -- MfG FalkArticle: 54936
If you specify your simulation step, I could answer your question better. Here is my thought. As you may already explain, Xpower reads two inputs (ncd and vcd). Have you generated the vcd file based on the post-place&route simulation? If you can not see the output in the PPRS, you will likely have all zero power for outputs. Seonil "Vivek" <viven@mailcity.com> wrote in message news:e74370e9.0304211731.6a5011b1@posting.google.com... > Hi, > I am using Xilinx ISE 4.2i and using XPower for power calculation. > > I need to know if i am doing something wrong here. > > After bringing up XPower from within Project Navigator i load the > simulation file (.VCD) > i have kept all other options (load)at default value > But after having done this i am not getting output power, isn't it > supposed to calculate the output and input power after having a look > at the .vcd file? > > the last message that i can see is: > > " Found definitions for xxxx signals in VCD file, beginning to process > value changes ... > > > Regards, > > Vivek VenkatramanArticle: 54937
On Tue, 22 Apr 2003 10:22:50 -0400, rickman <spamgoeshere4@yahoo.com> wrote: >Loi Tran wrote: >> >> >Before you give up on installing Xilinx, did you find viewing the >> >"agreement" would let you install the software? I can't imagine that >> >Xilinx would *block* you from using this under another OS. >> >> I would if I could, but the policy isn't even displayed. > >I am certain that you are looking at a problem *other* than the software >being locked out of being installed on Win98. This may in fact be a >problem that comes from incompatibility with Win98. Just to see if it >*will* install, try it on a different PC. For the record, I tried installing ISE on a Win98SE machine too... the install finishes normally but once the program is installed, none of the tools will start. I was a little pissed that the install didn't check the OS version and stop me from wasting half an hour installing ISE just to see it not work.Article: 54938
Tickofdcm is, indeed, the maximum under any (legal) combination of process, temperature and voltage. The only derating that you need to do is related to the jitter of your input clock; Tickofdcm includes the jitter added by the DCM itself, but does not include the jitter from the source clock. Exactly HOW to derate the jitter is a tricky issue - to be completely pessimistic, add the worst case cycle-cycle jitter from the source clock to Tickofdcm. This is a bit pessimistic since the "worst case" cycle-cycle jitter on the source input is a random jitter source, and is measured probabilistically, as is some component of the DCM jitter. Adding these linearly (i.e. summing them) is pessimistic. Also, don't forget that Tickofdcm needs to be adjusted based on the I/O standard you are using. Like all other I/O information, it is valid for LVTTL; other I/O standards need to be adjusted using the "Output Delay Adjustment" given in Table 17 of the most current datasheet (rev2.4). Avrum "BobW" <bwalance@ixiacom.com> wrote in message news:3ea57efd$1@la-news-01.... > > If the Tickofdcm number is 'maximum' then it's good news for us. The data > sheet doesn't indicate that it is 'maximum' as they do for the Tiockp values > (although I assUme it is). > > I'd better contact Xilinx, directly. > > Thanks, Avrum. > > Bob > > > > "Avrum" <avrum@REMOVEsympatico.ca> wrote in message > news:wx1pa.1446$Zj2.274347@news20.bellglobal.com... > > The Tpsdcm/Tphdcm and Tickofdcm include ALL the effects of clock > > distribution network using a DCM. You are correct that the data valid > window > > of the flop is widened by the jitter of the DCM, as well as things like > > uncertainty of the clock distribution tree. However, the DCM does more > than > > just add jitter... > > > > In the "standard" configuration (a DCM with no phase shift, and the CLK0 > > connected to CLKFB via a BUFG), the DCM actually overcompensates - making > > the effective delay through the clock network (from the input of the IBUFG > > to the clock port of an arbitrary IOB flop) slightly negative. In other > > words, the clock arrival at the clock pin of the IOB flop occurs slightly > > BEFORE the rising edge of the clock at the IBUFG, resulting in the smaller > > Tickofdcm. > > > > More importantly, the Tpsdcm/Tphdcm and Tickofdcm are extensively > > characterized, and are known to be very accurate. It isn't necessarily > > easy/meaningful to try and correlate these to the sum of individual delays > > of the internal components within the device. For example, if you tried to > > "derive" Tpsdcm/Tphdcm from the characteristics of the > IBUFG/DCM/BUFG/clock > > tree/IOB flop (assuming you had all this information, which you don't), > you > > would end up with a much more pessimistic range, and it wouldn't even > > necessarily be in an overlapping range with Tpsdcm/Tphdcm. > > > > In short, trust Tpsdcm/Tphdcm and Tickofdcm (or the new, source > synchronous > > timing information). > > > > Avrum > > > > "BobW" <bwalance@ixiacom.com> wrote in message > > news:3ea467af$1@la-news-01.... > > > Greetings, > > > > > > The Xilinx Virtex-II datasheet shows two different ways of specifying > IOB > > > setup/hold and clock-to-out times -- one with respect to the IOB clock > > > input, and another with respect to a DCM-deskewed global clock input > pad. > > > > > > The numbers below are for a XC2V1000-4FG456C > > > > > > In the "IOB Input Switching Characteristics" section, Tiopick/Tioickp is > > > 1.06/-0.45ns min. In the "Global Clock Setup and Hold for LVTTL > Standard, > > > with DCM" section the Tpsdcm/Tphdcm times are 1.84/-0.76ns. This > indicates > > > that if you're using a global clock input, and are using the DCM to > deskew > > > to the BUFG output, then you need more valid data time at an input pad. > > This > > > makes sense since the DCM jitter is being taken into account. > > > > > > So far, so good. > > > > > > In the "IOB Output Switching Characteristics" section, Tiockp is 3.44ns > > max > > > (assuming LVTTL 12mA fast). In the "Global Clock Input to Output Delay > for > > > LVTTL, 12mA, Fast Slew Rate, with DCM" section, Tickofdcm is 2.76ns. > This > > > doesn't make sense to me. Wouldn't the DCM's jitter increase the IOB's > > > clock-to-out time, not decrease it? > > > > > > Any help would be greatly appreciated. > > > > > > Thanks, > > > Bob > > > > > > > > > > > >Article: 54939
Stein Kjølstad wrote: > I would like to know if there is a way to put initial values to > internal RAM defined in VHDL. I'm not using technological primitives. > I'm using Quartus 2 as synthesis tool. Consider inferring a rom for the constants and a RAM for scratchpad. For examples see: http://www.altera.com/literature/an/an225.pdf page 15,16 -- Mike TreselerArticle: 54940
The problem is that there are no third party place and route tools. The
place and route tools are where the worst bugs (features) are. The one that
is particularly debilitating is the laziness of the router in versions 4.x
and 5.x that makes all paths in a design become critical paths.
Evan wrote:
> I've worked with various tools since FPGA's first appeared. You can't
> beat the price and performance of the software provided by Xilinx or
> Altera. Their software may have bugs, but you can usually work around
> them. If the vendor put as much effort to make the perfect software
> product you wanted. You wouldn't be able to afford it. Has it stands,
> the high end software tools cost $10,000 to $20,000+. Altera and Xilinx
> provide these tools as a low cost alternative, to help promote their
> sales. If you can't deal with it, put up the big bucks and buy the good
> software. Don't ruin a good thing for the rest of us.
>
> billh40@aol.com (Bill Hanna) wrote in
> news:97d137ce.0304171001.5ec5461d@posting.google.com:
>
> > I have been designing a Digital Signal Processor using the XC2V4000
> > chip.
> > Software errors in ISE 4.2 and 5.1 have caused long hours of delay in
> > developing the design:
> >
> > Software bugs in SystemAce causes erase problems in the MPM.
> > Deleting signal wires in ECS causes Fatal errors that crash the
> > system.
> > A large design exceeds the 2GB memory limit and generates a fatal
> > memory error.
> >
> > I have designed Altera chips for over 6 years and never had a
> > problem.
> >
> > All digital designers should stop designing new projects with
> > Xilinx ICs until Xilinx corrects all software problems with ISE.
> >
> > Bill Hanna
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 54941Hi Jim, > Well, I've finished up a couple NIOS designs and here's the Fmax > values I obtained for a couple configurations: > > SETUP 1 -- 90 MHz (1S10-C6ES), slack +500ps > 32-bit NIOS CPU without instruction/data cache and with button input, > led output, lcd output, sram, flash, ethernet, 1 uart, 1 dma, and some > custom logic interfaces. This design had a positive slack time of > nearly 500 ps suggesting that 95 MHz is probably possible. I tried > 100 MHz and had a negative slack time of nearly 500 ps. > > SETUP 2 -- 90 MHz (1S10-C6ES), slack +50ps > Same as #1 with addition of SDRAM controller. > > No LogicLock regions used in design. Sounds pretty reasonable to me. Note that the Altera timing model is based on some pretty horrible environmental factors. I once met a guy who was prototyping all sorts of video manipulation algorithms. If for some reason he didn't meet Fmax by more than 15 % he'd simply program the device, turn on the video stream and sprayed some coolant onto the device, thus stabilizing the picture... As to your repeated fast-fits, I'm not entirely sure what is happening because I haven't seen it happening yet, but I know that the Stratix router is pretty picky and may simply refuse a particular placement solution based on potential routing congestion. Best regards, BenArticle: 54942
Falk Brunner wrote: > > "rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag > news:3EA553E3.BDF0A41@yahoo.com... > > > In essence when you buy small parts in large quantities you are renting > > test time on their machines!!! > > So whats the alternative? Buy untested chips for half the price? > > ;-)) > SCNR. Isn't that what they sell as "untested die"? Do it yourself packaging! -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 54943
> Sounds pretty reasonable to me. Note that the Altera timing model is based > on some pretty horrible environmental factors. It's based on some _standard_ (but pretty horrible ;-)) environmental factors. For Stratix, this is 1.42 V and 85 degrees C, for a worst-case device in that will ever be binned. Since any given chip you are working with may be operating at higher voltage, lower temperature, and may very well have faster transistors, the fmax supplied by Quartus will often be worse than what you will observe on bench test of a couple devices. It's just like people who overclock their CPUs -- Intel/AMD have to rate speed based on high-temperature and poor voltage control. Also, they may sometimes yield more fast chips than slow chips and have to down-bin chips to meet demand/supply that they want to achieve. > I once met a guy who was prototyping all sorts of video manipulation > algorithms. If for some reason he didn't meet Fmax by more than 15 % he'd > simply program the device, turn on the video stream and sprayed some > coolant onto the device, thus stabilizing the picture... This is not a recommended technique ;-) > As to your repeated fast-fits, I'm not entirely sure what is happening > because I haven't seen it happening yet, but I know that the Stratix router > is pretty picky and may simply refuse a particular placement solution based > on potential routing congestion. The router for Stratix is excellent. It will try very hard to find a successful resolution to congestion before kicking back to the placer for another try -- it doesn't give up at the first whiff of trouble as your above paragraph implies :-) I'm not sure what's causing Jim's repeated fast-fitting, but we'll figure it out. Regards, PaulArticle: 54944
Petter Gustad wrote: >> still have to use kind of special shell or can you use your standard >> shell ? Under Windows, the shell is special because it is a port of the UNIX Bourne-again shell (bash), which is normally available on both Solaris and Linux without having to ask for it. > Under solaris you use a standard shell. I would assume you do the same > under Linux. > >> Do you know if Quartus 2.2 works with Mandrake 9.1 ? >> If it's not ready to use, what could be done to make it work ? > > I don't know. I use Red Hat 7.1 (what Altera has qualified) and > Slackware 7.1. I would be surprised if it does not work under > Mandrake. I succesfully ran Quartus on both RedHat 7.3 and Suse Linux 8.0, and I easily got Quartus II 2.2 to work on Gentoo Linux 1.4 as well. The only thing I had to do for the latter was to create a symlink from libstdc++-1.2 to libstdc++-1.3.something and then everything worked. I have heard of GUI problems in RedHat 8, and downright crashes with RedHat 9, but Red Hat has (1) hacked into both the Gnome and the KDE window managers and (2) changed the Linux kernel threading model to the newfangled NPTL (New Posix Threading Library or so) with Red Hat 9, so I'm not surprised to hear this at all. The GUI problems under Red Hat are being addressed, according to Altera. I'm not sure what is going to happen with the NPTL support. If I were them I'd build some compatibility, as the NPTL will be the de-facto standard for Linux 2.6. Best regards, BenArticle: 54945
Once you modified the UCF constraints, it's required to run through NGDBUILD(Translate), MAP, and PAR. UCF are taken in by NGDBUILD and passed on; therefore you'll not be able to skip that. If you're modifying constraints such as period, you'll be able to modify them in the PCF file and just simply run the par ncd and pcf in timing analyzer. Note that PCF constraint format are a little different. Check the Xilinx software manual's constraints guide section for more info. http://support.xilinx.com/support/sw_manuals/xilinx5/index.htm Regards, Wei Vlsi Champ wrote: > Hello, > > In the ISE tool with version 5.1i, is there any incremental tming > reporting? > I mean, once RUN the Implement Design, it performs the TRANSLATE, MAP > & PAR operations. Now after PAR, > suppose I am getting few violated paths, for which I m defining them > as either false or multi-cycle paths in the UCF file & I want the > corresponding timing report. > After this, do I have to do the PAR again? Or do I have to do MAP > again? Or do I have to start from TRANLATE? Or without doing any of > these, can I simply get the timing report corresponding to the changed > UCF (constraint file)? > > REgards, > > VLSI CHAMP....Article: 54946
Hi Stein, > Hi, > > I would like to know if there is a way to put initial values to > internal RAM defined in VHDL. I'm not using technological primitives. > I'm using Quartus 2 as synthesis tool. > > Thanks > Stein K You can generate a .mif or a .hex file to preload RAM in Altera devices (except the Stratix MegaRAM blocks). The best way to do this is to use the MegaWizard Plugin manager. Best regards, BenArticle: 54947
Actually 3.01 is the latest release (includes example designs for both Cyclone and Stratix dev. boards). Nios 3.0 is nearly identical, but without the example designs for the Cyclone dev. boards. On the spurious interrupts: A spurious interrupt occurs when interrupts are enabled, IRQ is asserted, and the interrupt source (IRQ number) does *not* have a proper entry in the vector table... in short, the interrupt hasn't been initialized in software, and there is nowhere for the CPU to jump to. The spurious interrupt handler provides a default piece of code to execute in this case (prints out "Spurious interrupt number <#>" over stdout). One potentially confusing 'gotcha' is that in the SOPC Builder peripheral table where you assign an IRQ number (16-64 for user exceptions), the assignment is decimal. The spurious interrupt message is printed in hex. Thus, 11 would be 17 in your list of peripherals, and 13 would be 19.... I bet each of these has a peripheral associated with it! One other note is that if one of these is an ethernet adapter - have you based your design on one of the examples? If not, check on the top-level schematic and note our "spurious interrupt" prevention circuit, basically an SR flop which prevents interrupts from an external Ethernet MAC until the software has written out to the chip. You can apply this to other off-chip components which may be giving you spurious interrupts as well. Jesse Kempa Altera Corp. jkempa @ altera dot com "Stefaan Vanheesbeke" <stefaan.vanheesbeke@pandora.be> wrote in message news:<uoepa.57094$t_2.5131@afrodite.telenet-ops.be>... > Is Nios 3.0 already available? > > I thought 2.2 was the latest version. > > Normally, if you have a sputiuos interrupt in Nios, it says soehting like > "spurious interrupts", but you can disable this in the SOPC builder. > > The source for this must be found in the lib directory. I suppose it will be > in an assembly file (*.s). If I'm back at my office, I will take a look > where it is. > > > "Jim M." <jim006@att.net> schreef in bericht > news:6f3fc0f8.0304211607.3f68f848@posting.google.com... > > Here's a tough one: > > > > Where can I find the source of NIOS CPU interrupts not assigned in > > SOPC Builder? > > > > If I trap interrupts, I tend to capture #1, #11, and #13 during LAN > > traffic. These are bad enough to create an infinite reset loop > > (probably because the interrupt source has not been cleared). > > > > Examination of my SOPC Builder NIOS design shows that IRQ #'s are > > assigned to my components starting at 16 and increasing from there. > > > > Also, if I disable "capture spurious interrupts" in the NIOS CPU, am I > > preventing the interrupts from occurring or are they eating CPU cycles > > and I just can't see it? > > > > I haven't been able track down this information using the Altera > > Knowledge Base. Looking for some help on this one. > > > > Thanks! > > > > JimArticle: 54948
"Basuki Endah Priyanto" <EBEPriyanto@ntu.edu.sg> writes: > I have Xilinx virtex2-1000 and Textronix Logic Analyzer. The problem > is the TTL output level from my logic analyzer is 3.8 volt and the > maximum volatge to my Virtex2 is 3.3 volt. Are you using the Tek as a pattern generator or something? Normally a logic analyzer has *inputs*, not outputs.Article: 54949
Hi Jim, I tried to create something similar using MicroBlaze and V2Pro The design has - MicroBlaze - 8Kb of onchip memory - Two External memories like flash and sram - lcd, led and button interface - One Uart - Two 32-bit timers - One Ethernet MAC My computer is a P3-900 Mhz with 512 MB of memory. The target device is a xc2vp4, package fg256, speed -6 I put a constraint on the clock for 120 MHz. It took the place and route tool (par) 8 min to get to that speed. Since MicroBlaze has 32-bit instructions (NIOS has 16-bit) and can therefore do more for each instruction, the actual performance should be higher even if the clock frequency is the same. Göran "Jim M." wrote: > Well, I've finished up a couple NIOS designs and here's the Fmax > values I obtained for a couple configurations: > > SETUP 1 -- 90 MHz (1S10-C6ES), slack +500ps > 32-bit NIOS CPU without instruction/data cache and with button input, > led output, lcd output, sram, flash, ethernet, 1 uart, 1 dma, and some > custom logic interfaces. This design had a positive slack time of > nearly 500 ps suggesting that 95 MHz is probably possible. I tried > 100 MHz and had a negative slack time of nearly 500 ps. > > SETUP 2 -- 90 MHz (1S10-C6ES), slack +50ps > Same as #1 with addition of SDRAM controller. > > No LogicLock regions used in design. > > In addition, I still experience a repeated fast fit during compilation > in Quartus. I'm not sure why this happens, but it occurs after any > change to the design. The first compile after a change results in a > database build, logic synthesis (using previous fitter results from > database), then a repeated fast-fit. I let one of these fast-fit > sessions run itself out and it took about 11 hours. It built up > 100-200 entries in the database. I received some pretty nice results > due to the 11 hour build. > > Now when I see the repeated fast-fit occurring, I stop the build after > the first fit then re-build. The rebuild skips the database builder > and logic synthesizer (since smart compile is enabled) and performs a > final fit (not fast-fit). > > I thought I'd post my final results. > > jim006@att.net (Jim M.) wrote in message news:<6f3fc0f8.0304141222.15bf1ca8@posting.google.com>... > > I recently purchased a NIOS Stratix 1S10 Development Kit from Altera > > and have mixed feelings about Quartus, SOPC Builder, and the NIOS > > Core. (For those poor souls interested, I've included some comments > > at the end of this post... feel free to provide feedback.) > > > > However, here's my question: > > > > What's the maximum clock frequency anyone has achieved using the NIOS > > 3.0 CPU in 32bit mode with the standard peripherals (SRAM, SDRAM, > > Ethernet, PIO, UART, etc. as in the Reference Design provided by > > Altera)? > > > > I've tried isolating the various components into LogicLock regions. > > I've tried different fitter/netlist optimizations. The maximum Fmax I > > have achieved to date is 80 MHz. This is after letting Quartus "fit" > > for 10 hours... it actually didn't stop, I had to abort the fitting > > and refit to finially get an interim result (see other misc comments > > below). > > > > Altera advertises 125 MHz for the Stratix Device and NIOS 3.0... > > However a reference design that builds at that clock rate is not > > provided. It appears that Altera gives you just enough to get your > > feet wet... anything above and beyond that is Intellectual Property > > that you need to buy. > > > > Other Observations/Comments: > > > > 1. The Quartus II SP1 software is extremely flakey. I've generated > > numerous faults when deleting/modifying child LogicLock Regions. It > > also takes forever to fit my Stratix design which is only 6000 LEs. > > If I select the "limit fitting attempts to 1" option, Quartus > > sometimes fits many times (like forever...) why?!?!? Also, after a > > design is finished building, the software sits around for up to 5 > > minutes before it generates a "finished" dialog box. I'm not sure > > what's going on between the Quartus Application thread and the Quartus > > Compiler thread, but it's fustrating enough just waiting for the > > design to build, let alone waiting for Quartus to figure out the build > > is done. I could go on and on, and that's only the result of 4 weeks > > of effort with a small design. I feel sorry for those folks working > > on a 100,000+ gate design. I guess modularity is the key there. > > > > 2. I can't simulate designs with virtual pins. I get warning during > > the analysis of the simulation and then receive results with all input > > pins a zero and output pins undefined. In addition, I can generate > > hold time warnings during simulation for a design that didn't compile > > with any hold time warnings. I'm not talking about hold time warnings > > on my input signals, I'm talking about hold time warnings on internal > > registers in my verilog code. Registers that I've taken care to hold > > for 1 or more clock cycles before using in other parts of the design. > > Again, the compilation of the design did not generate hold time > > warnings... only the simulation of the design. > > > > 3. PLLs generate different timing analysis results. THIS IS VERY > > ANNOYING! When I build up a "black-bock" design with virtual pins I > > obtain a Fmax calculation from the timing analysis routine. I then > > LogicLock the design and export it. When I import the design into a > > new project and clock it using a PLL it generates negative slack time > > warnings! If I remove the PLL and replace it with a clock pin, I get > > the Fmax result that I obtained during the "black box" design. I beat > > myself up for a week trying to debug a design that wasn't broken > > because of this goofy behavior in Quartus. I'm still not sure if the > > slack time warning it legit and wether I should be concerned about it. > > > > 4. SOPC Builder will lock itself up if you double-click components > > before selecting them. Give it a try... double click a component line > > in your NIOS design before selecting the line item. After a couple > > times the SOPC builder application creeps to a halt. > > > > 5. Documentation on the various megafunctions is lacking. A good > > example is the altsyncram megafunction. It doesn't state any timing > > requirements on the input registers, enable, and clock signals. Do I > > hold the data 1 cycle before flipping the write enable? How about > > holding the write enable before de-activating it? Why is the > > addressing based upon the data bit-width? Trying to tie a 32-bit > > altsyncram block to a NIOS CPU is difficult because you need to > > specify the address space of the peripheral and the address space of > > the altsyncram block is based upon the bit width (not the number of > > bytes). > > > > 6. I have yet to get a Leonaro-Spectrum synthesized Verilog file to > > build in Quartus. I can used Spectrum generated .edf files but not > > verilog. I get LCELL parameter errors. Unfortunately, Altera can't > > seem to duplicate this... anyone else see this behavior? I'm not sure > > if Spectrum synthesizes Verilog better that Quartus, but it definitely > > does it faster. > > > > Feedback is welcome... even if it's the "you're an idiot and here's > > why" variety...
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