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Hi there! I recently got hold of some older Xilinx XC3064 FPGA's. As I understand it, these are only supported by the old Xilinx XAct tools. Anyone knows where to obtain a copy of these tools nowadays? Best regards, Mads Kristoffersen Aarhus, DenmarkArticle: 55176
I have a full set of documentation for XACT6, but at this point I don't know
where the key and the disks are. If you find a copy, you'll also have to
install windows3.1. None of the graphical tools ran under win9x. IIRC, you
could still do command line from a win95 dos shell. Not sure if it would work
on a more recent system.
Mads Ulrik Kristoffersen wrote:
> Hi there!
>
> I recently got hold of some older Xilinx XC3064 FPGA's. As I understand it,
> these are only supported by the old Xilinx XAct tools. Anyone knows where to
> obtain a copy of these tools nowadays?
>
> Best regards,
> Mads Kristoffersen
> Aarhus, Denmark
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55177
What are the required specs for the ADC and DAC? If the sample rate is low,
you might be able to use a run of the mill board and use delta-sigma techniques
for the converter. I believe xilinx has app notes available on that. If you
need more than audio rates, then the number of candidate boards is narrowed
considerably. You might start by looking at the links to 3rd party boards on
the Xilinx website.
Brendan Lynskey wrote:
> Hi.
>
> I'm looking for a low-cost FPGA development board with an ADC & DAC for DSP
> applications.
>
> Could anyone recommend a REALLY low-cost one? :-)
>
> Thanks in advance,
>
> --
> Brendan Lynskey
> Comodo Research Lab
>
> Click on www.comodogroup.com/secure-email to keep your emails
> confidential with a complementary FREE personal Secure Email Certificate
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55178Thank Matt. Pow -- ---------------------------------------------------- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917) "Matt" <bielstein2002@attbi.com> ha scritto nel messaggio news:nMlra.122117$Si4.107252@rwcrnsc51.ops.asp.att.net... > Under Synthesize in Project Navigator you will find a "View RTL Schematic" > item. Use it to show the schematic view you are asking about. > > > > "Powermos" <flatiron@libero.it> wrote in message > news:HBzqa.69574$DT4.2075004@twister1.libero.it... > > For Rosen, > > > > another question for you, I'm studing the VHDL with Douglal Perry 3 edtn > > book, with ISE is possible to show > > a schematic view of VHDL code, this can be helpful to check if my > > interpretation is correct or not. > > > > Thanks in advance > > Powermos > > > > -- > > ---------------------------------------------------- > > Ama il tuo mestiere con passione > > E' il significato della tua vita > > Auguste Rodin (1840-1917) > > "B. Joshua Rosen" <bjrosen@polybus.com> ha scritto nel messaggio > > news:pan.2003.04.26.16.42.30.976665.16831@polybus.com... > > > On Sat, 26 Apr 2003 12:14:50 -0400, Powermos wrote: > > > > > > > Hy, > > > > > > > > in this day i've received a ISE 5.2i evaluation pack. At this time I'm > > > > successfully working with Foundation 3.1i, during installation of ISE > > > > 5.2i the > > > > programm stop into the second form and not show the license agreement, > > > > hence I can't continue during > > > > installation step. > > > > > > > > Some help please.................I'm desperate I'd like to evaluate > ISE > > > > 5.2 but I'm not able to install it!!!! > > > > > > > > My SO is Windows ME from Xilinx web site seems only Windows 2000 or XP > > > > is supported it's right? > > > > > > > > Thanks for your help!!! > > > > > > > > Powermos > > > > > > > > -- > > > > ---------------------------------------------------- Ama il tuo > mestiere > > > > con passione > > > > E' il significato della tua vita > > > > Auguste Rodin (1840-1917) > > > > > > 5.2 is Win2K or XP only. It also works fine on Linux using Wine. None of > > > the Win9x OSs are supported including WinME. You are going to have to > > > upgrade your OS if you want to use 5.2. > > > > > >Article: 55179
Mads, my advice is: Do what you would do any intel '286s, which are of the same vintage: Throw them away! Newer parts are so much more capable, and the software so much better, that these old parts are not worth the time you waste on them. If my rule holds, that one year in the evolution of ICs equals 15 years in the aging of humans, then these 1989 XC3064s have the strength and staying power of a 200-year old great-great-great-great granddaddy. Let them rest forever! Peter Alfke =================== Mads Ulrik Kristoffersen wrote: > > Hi there! > > I recently got hold of some older Xilinx XC3064 FPGA's. As I understand it, > these are only supported by the old Xilinx XAct tools. Anyone knows where to > obtain a copy of these tools nowadays? > > Best regards, > Mads Kristoffersen > Aarhus, DenmarkArticle: 55180
Ken,
Get your hands on a copy of the ARRL Handbook for Radio Amateurs. It's got
enough info in there to build what you want out of just a few parts.
Depending on your carrier frequeucy, the receive side may be able to be done
with just an ADC and the FPGA. See the shortwave receiver demo block diagram
on the welcome page in my website. That example is a block diagram of a
radio we built using an Insight spartanII demo board, a Burr-Brown ADC807e A
to D eval card and a pair of PC speakers. It actually works remarkably well
considering we were digitizing the entire spectrum below about 60 MHz with a
single 12 bit ADC sampling at 40 MHz. I have listened to BBC and Deutche
Welle on it from my office on the US east coast. The transmit side could
theoretically be done the same way, although you'd want some filtering on the
analog side to avoid spattering energy all over the spectrum.
Ken wrote:
> Hello folks,
>
> We are looking at buying a pair of RF transmitters/receivers to use in
> conjunction with two Xilinx Xtreme DSP Kits
> (http://www.xilinx.com/ipcenter/dsp/development_kit.htm).
>
> The transmission distance will be across a table/room at the most I would
> think so high frequency/power gear is not required.
>
> We just want to amplitude modulate a baseband/IF signal from the xilinx
> kit's DAC to some carrier frequency, receive it at the other side,
> demodulate and send it to the ADC of the other board.
>
> Has anyone done anything like this with these boards?
>
> Could anyone recommend any bits of RF kit that might do the job?
>
> All comments/"questions to fill in any inadvertant blanks of mine" much
> appreciated.
>
> Thanks for your time,
>
> Ken
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 55181Brendan, Altera offers two Stratix DSP Development Kits and an APEX DSP Dev Kit. You can these and other dev kits listed at http://www.altera.com/products/devkits/kit-dev_platforms.jsp Regards, Paul Leventis Altera Corp "Brendan Lynskey" <brendan@comodogroup.com> wrote in message news:ePxra.12887$xd5.648578@stones.force9.net... > Hi. > > I'm looking for a low-cost FPGA development board with an ADC & DAC for DSP > applications. > > Could anyone recommend a REALLY low-cost one? :-) > > Thanks in advance, > > > -- > Brendan Lynskey > Comodo Research Lab > > Click on www.comodogroup.com/secure-email to keep your emails > confidential with a complementary FREE personal Secure Email Certificate > >Article: 55182
In article <3EAEA547.DCCD5C23@yahoo.com>, rickman wrote:
>
> My main aversion to uses a thermal switch like you are suggesting is
> that it has a fixed cut off.
You haven't seen all the thermal switches available.
> The board I am designing is not for a
> single purpose. It is for a variety of applications. Using a micro
> will not cost more and will give me a lot more flexibility to tailor the
> board for special requests. EEPROM is a wonderful thing!
Indeed. See if you can use the DS1822, which has a programmable
(EEPROM) alarm. I'd resist the urge to add one more computer
to the mix, with an additional firmware and development toolchains
to keep running.
- Larry
Article: 55183Frederic Rivoallon <frederic.rivoallon@xilinx.com> wrote in message news:<3EAEB976.2AC857D8@xilinx.com>... > Patrik Eriksson wrote: > > > I would like to use the DCM frequency synthesizer feature to multiply a > > input signal which frequency is less then 20MHz with 4. I do not need to > > deskew the signal (i.e. no fedback is needed). No other clock output > > will be used. How should I instantiate the DCM in my VHDL code? Which > > attributes should I apply? and where? (I use synplify for synthesis) > > Patrick, > > Provided you are using 5.1i or greater, you can use the Architecture Wizard > to generate the HDL code. > You can access it from ISE (Project-> New Source) or use it stand alone > (command: arwz). > > Below I pasted an example of generated code (intended for Synplicity). The > wizard also calculates jitter for the CLKFX output. > > Frederic Rivoallon. [snip code fragment, and rearranged top post] Frederic, Does this somehow get around the minimum (24 MHz) input frequency requirement of the V2 DCM? My understanding is that Patrik will not be able to use the DCM in his case. Patrik, you may want to look into ICS (if you can stand the jitter) or Cypress or someone like that for a x4 chip. They are available in pretty tiny packages. MarcArticle: 55184
Marc Randolph wrote: > > > Does this somehow get around the minimum (24 MHz) input frequency > requirement of the V2 DCM? No problem! In Frequency Synthesis mode, the 24 MHz min frequency limit refers to the output frequency, not the input frequency. So it is perfectly alright to feed any 6-to-50 or more MHz frequency into the DCM, and make it multiply the frequency by 4. ( If you thought there would be a problem, I thought so too, until I was corrected by Austin. It's nice to have expertise right around the corner...) Peter Alfke > > rArticle: 55185
> > I would like to use the DCM frequency synthesizer feature to multiply a > > input signal which frequency is less then 20MHz with 4. I do not need to > > deskew the signal (i.e. no fedback is needed). >Does this somehow get around the minimum (24 MHz) input frequency >requirement of the V2 DCM? > >My understanding is that Patrik will not be able to use the DCM in his >case. > >Patrik, you may want to look into ICS (if you can stand the jitter) or >Cypress or someone like that for a x4 chip. They are available in >pretty tiny packages. Peter's clock doubling trick should be good enough for the first factor of two. So I think it can work without external parts as long as the clock is over 12 MHz. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 55186
What's the prize for this challenge anyway?
reg [9:0] n;
wire [2:0] p1, p2;
wire [3:0] p;
wire [1:0] q1, q2;
wire [2:0] q;
wire [1:0] r1;
wire r2;
wire [1:0] r;
wire [1:0] out;
assign p1=n[8]+n[6]+n[4]+n[2]+n[0];
assign p2=n[9]+n[7]+n[5]+n[3]+n[1];
assign p={p2,1'b0}+{1'b0,p1};
assign q1=p[2]+p[0];
assign q2=p[3]+p[1];
assign q={q2,1'b0}+{1'b0,q1};
assign r1=q[2]+q[0];
assign r2=q[1];
assign r={r2,1'b0}+{1'b0,r1};
assign out = &r ? 2'b0 : r;
Paul Dankoski
"Ain't math great?"
RISC taker wrote:
>Hey, I need to calculate (n mod 3) in a Virtex-II design. n is a
>10-bit unsigned number and 3 is a constant. This has to be done in the
>same cycle (combinatorial!). Now what's a good way to implement that?
>
>I thought of a lookup table (distributed RAM) but this takes quite a
>lot of space. Any better ideas? (Ray, the arithmetic guru? :-)
>
>Do you think I can perform this operation at 200 MHz in a Virtex-II?
>
>Thanks!
>RISC_taker
>
>
Article: 55187It looks like you haven't included the entire homework problem. Could you provide the rest of the information? anup chandak wrote: > Respected sir, want to design a circuit which gives the output of '1' > for duration of 0.5us when an input transit from '0' to '1'. i want an > synthesisable code for this . so can you please mail me in this regard.Article: 55188
(My comments that follow are from the Spartan-II(E) perspective, not the Virtex-II(Pro) style of devices) You have an additional problem. The control for the F5MUX is the .BX input which is also the data input for the write to the lower RAM. You say you need to write to both simultaneously but I'm assuming here that you also need to write to a single memory on occasion, hence your original problem. Are there extreme needs that require packing in one LUT? Perhaps with a slightly different perspective the desired end result can be achieved without the same-LUT packing. Maybe we could generate ideas from that more distant perspective. Gilad Cohen wrote: > Hello. > > I am trying to put two 16x1 single port RAMs in one slice. > > I don't need to read from both of them simultainously, so I can use them > F5MUX to mux the 2 outputs. > > I only need to write to both of them simultainously. > > The problem is that the ISE uses the SR slice input as a Write Enable. > Since there is only one SR input per slice, I can have only one Write > Enable signal, and can write to only one RAM at a time. > > Anyone has any idea? > Maybe I can use the SLICEWE[2:0] inputs... >Article: 55189
"John_H" <johnhandwork@mail.com> wrote in message news:3EAF29CA.60607@mail.com... > It looks like you haven't included the entire homework problem. Could > you provide the rest of the information? > > > anup chandak wrote: > > Respected sir, want to design a circuit which gives the output of '1' > > for duration of 0.5us when an input transit from '0' to '1'. i want an > > synthesisable code for this . so can you please mail me in this regard. > I often wonder about the oft-used labeling of these posters, as students trying to make up for lack of studying. The truth may be much more sinister: I wonder how much information is gleaned off Google and Usenet, in order for desperate "outsourcing" firms to cobble together a product. By being overly helpful on Usenet, could we be devoting our own time to competition with ourselves? -----= Posted via Newsfeeds.Com, Uncensored Usenet News =----- http://www.newsfeeds.com - The #1 Newsgroup Service in the World! -----== Over 80,000 Newsgroups - 16 Different Servers! =-----Article: 55190
I would suggest using external (to the LUT) muxes to selectively feed back the output data. I.e., when you want to write to both bits, new data goes in to both input bits; when you only want to update one bit, the appropriate mux feeds in new data to one bit, and current data is fed back to the other bit. This assumes that the address is always the same for both bits. Jason Gilad Cohen wrote: > > Hello. > > I am trying to put two 16x1 single port RAMs in one slice. > > I don't need to read from both of them simultainously, so I can use > them F5MUX to mux the 2 outputs. > > I only need to write to both of them simultainously. > > The problem is that the ISE uses the SR slice input as a Write Enable. > Since there is only one SR input per slice, I can have only one Write > Enable signal, and can write to only one RAM at a time. > > Anyone has any idea? > Maybe I can use the SLICEWE[2:0] inputs...Article: 55191
Peter Alfke <peter@xilinx.com> wrote in message news:<3EAF1C85.D8E4528B@xilinx.com>... > Marc Randolph wrote: > > > > > Does this somehow get around the minimum (24 MHz) input frequency > > requirement of the V2 DCM? > > No problem! In Frequency Synthesis mode, the 24 MHz min frequency limit > refers to the output frequency, not the input frequency. > So it is perfectly alright to feed any 6-to-50 or more MHz frequency > into the DCM, and make it multiply the frequency by 4. Ah yes, I see that now. It's CLKIN_FREQ_FX_LF_Min, for anyone interested. > ( If you thought there would be a problem, I thought so too, until I was > corrected by Austin. It's nice to have expertise right around the corner...) > Peter Alfke And it's nice to have expertise here on the newsgroup. Thanks Austin, Peter, and all the other support engineers out there! Marc MarcArticle: 55192
I would have to have a better idea of what's on it, how much free space there is, and how many pins each BGA, and what constraints / routing is required before quoting. you would have to also accept Protel 98 SE files as that's the software I own Simon "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3EAEA547.DCCD5C23@yahoo.com... > Simon wrote: > > > > well.. actually its a sot23 5 pin package and costs 67c on the web site.. > > and a digital output so it wouldn't be hard to fit :-) > > considering it would shut down a standard temp micro, the micro cost saving > > would satisfy the extra cost of a $1 FET and a 67c thermal switch. Or > > better.. use a regulator with an on/off switch and just turn it on / off via > > the thermal switch.. it can be fed from 2.7V to 5.5V after all. Is not that > > silly if you add the pros and cons. Unless as you say the space will kill > > ya.. but I've yet to see a board I couldn't squeeze the last square mm out > > of (have been doing CAD for many a year) > > If you are really that good, maybe you can give me a price on doing my > board. It is only 3.5" x 3.8" and most of the parts are on one side. > But it is very dense. I have several BGAs the rest are tssops. I am > hoping to keep the board to just 6 layers, but it may well need to be > 8. I don't expect any three pin device will cause a 6 layer layout to > fail, but I would rather focus on adding value to the board while > keeping the layout as simple as possible. > > My main aversion to uses a thermal switch like you are suggesting is > that it has a fixed cut off. The board I am designing is not for a > single purpose. It is for a variety of applications. Using a micro > will not cost more and will give me a lot more flexibility to tailor the > board for special requests. EEPROM is a wonderful thing! > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55193
Hi, Thanks for all the responses which were quite helpful. I would like to point out that since this implementation should be very cost-effective, I am on the lookout for free synthesizable IIR cores, which have scalable data and coeff width. If you can direct me to any such link it will be a great help for me. Tom, thanks for the idea on confluence core. I hope you might have a case study or app note on an IIR implementation using this core. I would like to know the resource usage by the core. Thanks and Regards, Pramod tom1@launchbird.com (Tom Hawkins) wrote in message news:<833030c0.0304291036.5b1af72a@posting.google.com>... > pramod@procsys.com (Pramod) wrote in message news:<a7c0720d.0304152101.581c85be@posting.google.com>... > > Hi All, > > I am new to this group and also to the field of FPGA based design. > > I have some doubts and issues which I feel will be easy for you guys > > to answer. > > 1. For a 4 pole IIR Filter in FPGA (targeted device EP1C6), I have a > > spec of 24 bit wide data input and > > 32 bit wide coeff (dynamic) inputs. So, the multiplied results should > > ideally have > > 56 bits width. Are these widths practically relevant for a 4 pole > > filter > > or can we get an affordable precision with rounding to lower sizes? > > If so, can anyone suggest a standard procedure for > > rounding the results with lowest error and without causing the output > > to become unstable? > > > Pramod, > > You may want to check out the Confluence State Space Processor > on OpenCores: > > http://www.opencores.org/projects/cf_ssp/ > > We built the core specifically for linear operations including: > FIR filters, IIR filters, and general multi-variable state > space calculations; all of which are common in DSP and control > applications. > > The core is a processor with a very simple instruction > set -- only 8 instructions -- for addition, shifting, > sign-extending, limiting, and loading constant coefficients. > Multiplication is performed by sign-extending the data, then > performing a series of shifts and conditional adds on an > accumulator. > > The processor is designed for simplicity and takes up very > little area. Because the processor runs a program every sample > period, it works well for applications where the clock rate is > significantly faster that the sample rate of the discrete function. > > The architecture gives you 16 registers for I/O, intermediate > calculation, and state variables. Constants are stored in an > external memory with an 8-bit address giving you a possible > total of 256 different coefficients. > > The State Space Processor core is generated from Confluence with > configuration parameters of data width and instruction address > width. If you don't see the configuration you need, let me know > and I'll generate a custom processor for you. > > Regards, > TomArticle: 55194
Marc Randolph wrote: > Peter Alfke <peter@xilinx.com> wrote in message news:<3EAF1C85.D8E4528B@xilinx.com>... > >>Marc Randolph wrote: >> >>>>Does this somehow get around the minimum (24 MHz) input frequency >>> >>>requirement of the V2 DCM? >> >>No problem! In Frequency Synthesis mode, the 24 MHz min frequency limit >>refers to the output frequency, not the input frequency. >>So it is perfectly alright to feed any 6-to-50 or more MHz frequency >>into the DCM, and make it multiply the frequency by 4. > > > Ah yes, I see that now. It's CLKIN_FREQ_FX_LF_Min, for anyone > interested. > > >>( If you thought there would be a problem, I thought so too, until I was >>corrected by Austin. It's nice to have expertise right around the corner...) >>Peter Alfke > > > And it's nice to have expertise here on the newsgroup. Thanks Austin, > Peter, and all the other support engineers out there! > > Marc > > Marc Thanks for all the answers! I have noticed the CLKIN_FREQ_FX_LF_Min figure that says 1MHz if you don't use any feedback and the only output clock that will be used is the CLKFX. My problem is to get the software to understand what I want to do. My question is: How should I instantiate the DCM in my VHDL code? Which attributes should I apply? and where? (I use synplify 7.2.1 for synthesis) /Patrik -- Patrik Eriksson | patrik.eriksson@netinsight.net Net Insight AB | phone: +46 8 685 04 89 Västberga Allé 9 | fax: +46 8 685 04 20 SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.netArticle: 55195
Patrik Eriksson wrote:
> Marc Randolph wrote:
>
>> Peter Alfke <peter@xilinx.com> wrote in message
>> news:<3EAF1C85.D8E4528B@xilinx.com>...
>>
>>> Marc Randolph wrote:
>>>
>>>>> Does this somehow get around the minimum (24 MHz) input frequency
>>>>
>>>>
>>>> requirement of the V2 DCM?
>>>
>>>
>>> No problem! In Frequency Synthesis mode, the 24 MHz min frequency limit
>>> refers to the output frequency, not the input frequency.
>>> So it is perfectly alright to feed any 6-to-50 or more MHz frequency
>>> into the DCM, and make it multiply the frequency by 4.
>>
>>
>>
>> Ah yes, I see that now. It's CLKIN_FREQ_FX_LF_Min, for anyone
>> interested.
>>
>>
>>> ( If you thought there would be a problem, I thought so too, until I was
>>> corrected by Austin. It's nice to have expertise right around the
>>> corner...)
>>> Peter Alfke
>>
>>
>>
>> And it's nice to have expertise here on the newsgroup. Thanks Austin,
>> Peter, and all the other support engineers out there!
>>
>> Marc
>>
>> Marc
>
>
> Thanks for all the answers!
>
>
> I have noticed the CLKIN_FREQ_FX_LF_Min figure that says 1MHz if you
> don't use any feedback and the only output clock that will be used is
> the CLKFX. My problem is to get the software to understand what I want
> to do.
>
> My question is:
> How should I instantiate the DCM in my VHDL code? Which attributes
> should I apply? and where? (I use synplify 7.2.1 for synthesis)
>
> /Patrik
>
The software report the following warning.
WARNING:Timing:2721 - The clock pgmtclk_c is the input to DCM
MISCELLANEOUS/MULT_ADD_DCM. pgmtclk_c has a low pulse width of
25720 ps and
a high pulse width of 25720 ps. This violates the pulse width of
MISCELLANEOUS/MULT_ADD_DCM which has a maximum low pulse width of
20830 ps
and a maximum high pulse width of 20830 ps.
/Patrik
--
Patrik Eriksson | patrik.eriksson@netinsight.net
Net Insight AB | phone: +46 8 685 04 89
Västberga Allé 9 | fax: +46 8 685 04 20
SE-126 30 STOCKHOLM, Sweden | http://www.netinsight.net
Article: 55196Hi all, i am a novice at FPGA technology. My research group is interested in having a very fast network filter before the packets are sent for further routing (gigabit order). Preliminary searching has resulted in finding the following paper which talks about acheiving 2.88 gigabit/sec using ALTERA EP20K. www.ee.ucla.edu/faculty/papers/ billms_FPL2002_sept02.pdf There are other simillar papers which also talk about such work and give good resutls. What is not clear though is how the system is implemented. There are several boards which can be purchased which sit on the pci bus of a system. If i were to buy such a board, how would i interface it with the network interface ? Would the pci bus limit the speed of the implementation ? I would be really greatfull if you could give me some pointers as to how to set up such a system and how to program it. Thanks, Regards, SaurabhArticle: 55197
Ray, Thanks very much for your reply - we will certainly investigate this possible solution. However, we also have money that we need to spend so we would be interested in "off-the-shelf" solutions too... Cheers, Ken "Ray Andraka" <ray@andraka.com> wrote in message news:3EAEE41A.FED39635@andraka.com... > Ken, > > Get your hands on a copy of the ARRL Handbook for Radio Amateurs. It's got > enough info in there to build what you want out of just a few parts. > Depending on your carrier frequeucy, the receive side may be able to be done > with just an ADC and the FPGA. See the shortwave receiver demo block diagram > on the welcome page in my website. That example is a block diagram of a > radio we built using an Insight spartanII demo board, a Burr-Brown ADC807e A > to D eval card and a pair of PC speakers. It actually works remarkably well > considering we were digitizing the entire spectrum below about 60 MHz with a > single 12 bit ADC sampling at 40 MHz. I have listened to BBC and Deutche > Welle on it from my office on the US east coast. The transmit side could > theoretically be done the same way, although you'd want some filtering on the > analog side to avoid spattering energy all over the spectrum. > > Ken wrote: > > > Hello folks, > > > > We are looking at buying a pair of RF transmitters/receivers to use in > > conjunction with two Xilinx Xtreme DSP Kits > > (http://www.xilinx.com/ipcenter/dsp/development_kit.htm). > > > > The transmission distance will be across a table/room at the most I would > > think so high frequency/power gear is not required. > > > > We just want to amplitude modulate a baseband/IF signal from the xilinx > > kit's DAC to some carrier frequency, receive it at the other side, > > demodulate and send it to the ADC of the other board. > > > > Has anyone done anything like this with these boards? > > > > Could anyone recommend any bits of RF kit that might do the job? > > > > All comments/"questions to fill in any inadvertant blanks of mine" much > > appreciated. > > > > Thanks for your time, > > > > Ken > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 55198
Garrett Mace wrote: > > "John_H" <johnhandwork@mail.com> wrote in message > news:3EAF29CA.60607@mail.com... >> It looks like you haven't included the entire homework problem. Could >> you provide the rest of the information? >> >> >> anup chandak wrote: >> > Respected sir, want to design a circuit which gives the output of '1' >> > for duration of 0.5us when an input transit from '0' to '1'. i want an >> > synthesisable code for this . so can you please mail me in this regard. >> Hi Garrett, > I often wonder about the oft-used labeling of these posters, as students > trying to make up for lack of studying. The truth may be much more > sinister: I wonder how much information is gleaned off Google and Usenet, > in order for desperate "outsourcing" firms to cobble together a product. > > By being overly helpful on Usenet, could we be devoting our own time to > competition with ourselves? I'm also thinking about this sometimes. If we are honest to ourself, almost everybody that is posting a question on usenet shows some "lack of studying" (I'm including myself here as well). This is at least valid for technical issues and newsgroups like this. It is often more easy to ask somebody about a specific problem rather than doing some investigation in the library or on the web - although Google returns many answers quickly. These people that are very unexperienced will ask rather stupid questions while others will ask more difficult ones. Regarding the general publication of know-how and information, I think this is a process of giving and taking. When you give some answer to some questions, you are happy when you receive one for your problem. In case of such questions that appear to come from students that have to do their homework, it is probably the best to give only some fragments as answer. Then they can use their own brain to complete the puzzle... Regards, MarioArticle: 55199
Uwe Bonnes <bon@elektron.ikp.physik.tu-darmstadt.de> wrote: : Hallo, : the Spartan-3 datasheet talks about the XCF configuration Flash PROM : parts. I found no further information. Any pointers? Okay, the press-release and datasheets are out (030429) Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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