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On Sat, 26 Apr 2003 12:14:50 -0400, Powermos wrote: > Hy, > > in this day i've received a ISE 5.2i evaluation pack. At this time I'm > successfully working with Foundation 3.1i, during installation of ISE > 5.2i the > programm stop into the second form and not show the license agreement, > hence I can't continue during > installation step. > > Some help please.................I'm desperate I'd like to evaluate ISE > 5.2 but I'm not able to install it!!!! > > My SO is Windows ME from Xilinx web site seems only Windows 2000 or XP > is supported it's right? > > Thanks for your help!!! > > Powermos > > -- > ---------------------------------------------------- Ama il tuo mestiere > con passione > E' il significato della tua vita > Auguste Rodin (1840-1917) 5.2 is Win2K or XP only. It also works fine on Linux using Wine. None of the Win9x OSs are supported including WinME. You are going to have to upgrade your OS if you want to use 5.2.Article: 55101
Infinitely thanks Rosen, for XP all versione is right? At this time I can install the XP Professional Corporate Version, this OS is right? Thanks in advance Powermos -- ---------------------------------------------------- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917) "B. Joshua Rosen" <bjrosen@polybus.com> ha scritto nel messaggio news:pan.2003.04.26.16.42.30.976665.16831@polybus.com... > On Sat, 26 Apr 2003 12:14:50 -0400, Powermos wrote: > > > Hy, > > > > in this day i've received a ISE 5.2i evaluation pack. At this time I'm > > successfully working with Foundation 3.1i, during installation of ISE > > 5.2i the > > programm stop into the second form and not show the license agreement, > > hence I can't continue during > > installation step. > > > > Some help please.................I'm desperate I'd like to evaluate ISE > > 5.2 but I'm not able to install it!!!! > > > > My SO is Windows ME from Xilinx web site seems only Windows 2000 or XP > > is supported it's right? > > > > Thanks for your help!!! > > > > Powermos > > > > -- > > ---------------------------------------------------- Ama il tuo mestiere > > con passione > > E' il significato della tua vita > > Auguste Rodin (1840-1917) > > 5.2 is Win2K or XP only. It also works fine on Linux using Wine. None of > the Win9x OSs are supported including WinME. You are going to have to > upgrade your OS if you want to use 5.2.Article: 55102
For Rosen, another question for you, I'm studing the VHDL with Douglal Perry 3 edtn book, with ISE is possible to show a schematic view of VHDL code, this can be helpful to check if my interpretation is correct or not. Thanks in advance Powermos -- ---------------------------------------------------- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917) "B. Joshua Rosen" <bjrosen@polybus.com> ha scritto nel messaggio news:pan.2003.04.26.16.42.30.976665.16831@polybus.com... > On Sat, 26 Apr 2003 12:14:50 -0400, Powermos wrote: > > > Hy, > > > > in this day i've received a ISE 5.2i evaluation pack. At this time I'm > > successfully working with Foundation 3.1i, during installation of ISE > > 5.2i the > > programm stop into the second form and not show the license agreement, > > hence I can't continue during > > installation step. > > > > Some help please.................I'm desperate I'd like to evaluate ISE > > 5.2 but I'm not able to install it!!!! > > > > My SO is Windows ME from Xilinx web site seems only Windows 2000 or XP > > is supported it's right? > > > > Thanks for your help!!! > > > > Powermos > > > > -- > > ---------------------------------------------------- Ama il tuo mestiere > > con passione > > E' il significato della tua vita > > Auguste Rodin (1840-1917) > > 5.2 is Win2K or XP only. It also works fine on Linux using Wine. None of > the Win9x OSs are supported including WinME. You are going to have to > upgrade your OS if you want to use 5.2.Article: 55103
"Powermos" <flatiron@libero.it> wrote in message news:kwzqa.69403$iy5.2075066@twister2.libero.it... > Infinitely thanks Rosen, > for XP all versione is right? At this time I can install the > XP Professional Corporate Version, this OS is right? > > Thanks in advance > Powermos Probably both versions of XP will be OK... windows 2000, XP home & pro are all based on the same kernel... JamieArticle: 55104
Thank Jamie Pow -- ---------------------------------------------------- Ama il tuo mestiere con passione E' il significato della tua vita Auguste Rodin (1840-1917) "Jamie" <jamcquay@hotmail.BOOM.com> ha scritto nel messaggio news:0vAqa.5132$Zj2.1100502@news20.bellglobal.com... > > "Powermos" <flatiron@libero.it> wrote in message > news:kwzqa.69403$iy5.2075066@twister2.libero.it... > > Infinitely thanks Rosen, > > for XP all versione is right? At this time I can install the > > XP Professional Corporate Version, this OS is right? > > > > Thanks in advance > > Powermos > > Probably both versions of XP will be OK... windows 2000, XP home & pro are > all based on the same kernel... > > Jamie > >Article: 55105
On Sat, 26 Apr 2003 13:46:15 -0400, Powermos wrote: > For Rosen, > > another question for you, I'm studing the VHDL with Douglal Perry 3 edtn > book, with ISE is possible to show > a schematic view of VHDL code, this can be helpful to check if my > interpretation is correct or not. > > Thanks in advance > Powermos > > -- > ---------------------------------------------------- Ama il tuo mestiere I can't help you here, I don't use any of the graphical features of the Xilinx tools except for fpga_editor. As to your question about XP, any version of Win2K or XP will work. The difference between the home, pro and server versions is the inclusion, or enabling, of various features that have nothing to do with running an application like the Xilinx tools.Article: 55106
Hello! Can I change Cyclone PLL's divisor and multiply counter values on the fly? I will use Quartus, after license has arrived. I want that user can change clock frequency of device by pressing a button. Needed frequencys are between 30MHz and 100MHz. Frequencys may be for example 10MHz distances (30, 40, 50, 60, 70, 80, 90 and 100MHz). I was thinking, if input frequency will be 20MHz. Then it is divided by two and then multiplyed with user's wanted value (3 to 10). Is this reasonable way? How is input frequency's jitter effecting to output freq? If fIn is 20MHz with 50ppm, is fOut then 100MHz with 250ppm? (M=10, N=2) Is this possible or is there some better way to do this? Good ideas are welcome! =) Best Regards, JoonaArticle: 55107
Does it matter "how" or just accept "that" the LUT works? The elements shift such that the address you feed as inputs to the LUT address the elements in sequence along the chain. Address 0 is the first element (most recently) shifted into, address 15 was shifted in 16 (enabled) clock edges previously. The additional silicon expense to make the memory elemets sequentially shift wasn't much, so Xilinx started desinging the feature into the LUTs quite a few years back. Many of use are very happy they did. Nachiket Kapre wrote: > How does a Virtex implement a shift register in the same LUT? An LUT > is basically a RAM with an address bus and a single bit read/write > data bus. Are there special routes inside the LUT that write back the > most significant n-1 ( n= size of the SR) bits alongwith the newest > bit back into the same LUT? How are the bits physically moved inside > the RAM? > > regards, > Nachiket Kapre. > Paxonet Communications Inc.Article: 55108
"B. Joshua Rosen" <bjrosen@polybus.com> wrote in message news:pan.2003.04.25.16.03.12.617843.11775@polybus.com... > I've finally gotten around to updating the Xilinx on Linux HOWTO page. > It's available at, > > http://www.polybus.com/xilinx_on_linux.html How about the Xilinx on Linux on Xilinx page! RalpjArticle: 55109
During configuration the means of getting the configuration data into the LUTs is a shift register anyway. So it was only necessary to make a seperate control signal and the shift input for each lut visible to the user. For all that I know the area cost of makíng these additional signals routable to the LUTs is higher than the modification to the LUT itself. Kolja Sulimma John_H <johnhandwork@mail.com> wrote in message >[...] > The additional silicon expense to make the memory elemets sequentially > shift wasn't much, so Xilinx started desinging the feature into the LUTs > quite a few years back. > Nachiket Kapre wrote: > > How does a Virtex implement a shift register in the same LUT? An LUT > > is basically a RAM with an address bus and a single bit read/write > > data bus. Are there special routes inside the LUT that write back the > > most significant n-1 ( n= size of the SR) bits alongwith the newest > > bit back into the same LUT? How are the bits physically moved inside > > the RAM?Article: 55110
Hello. I am trying to put two 16x1 single port RAMs in one slice. I don't need to read from both of them simultainously, so I can use them F5MUX to mux the 2 outputs. I only need to write to both of them simultainously. The problem is that the ISE uses the SR slice input as a Write Enable. Since there is only one SR input per slice, I can have only one Write Enable signal, and can write to only one RAM at a time. Anyone has any idea? Maybe I can use the SLICEWE[2:0] inputs...Article: 55111
"Berend Ozceri (snip _news_ from address to reply)" <bozceri_news_@yahoo.com> wrote in message news:<de3qa.612785$F1.82432@sccrnsc04>... > I just came across Northwest Logic's (http://www.nwlogic.com) PCI/PCI-X > core offerings (for Altera and Xilinx) and was wondering if there were > any folks out there who have used them (or other cores from Northwest > Logic) and would like to share their experiences. > > Thanks in advance for information, > > Berend If all you need is PCI, check out the FREE PCI IP core at OpenCores: www.opencores.org. Regards, rudi ------------------------------------------------------- www.asics.ws -- Solutions for your ASIC/FPGA needs --- ---------------- FPGAs * Full Custom ICs * IP Cores --- * * * FREE IP Cores --> http://www.asics.ws/ <-- * * *Article: 55112
This is not exactly true. The configuration process uses only a single frame-size shift register. Every time this is filled, its content is loaded in parallel into the designated frame. (See any explanation of partial reconfiguration). The crucial root of SRL16 is the LUT-RAM capability. Once we had 16 writable latches, it was not too difficult to convert this structure into a shift register. Yes, the circuit designers had to be clever to insert something to avoid any race condition. The SRL16 is really a shift register in which data is physically shifted from input to output. Works like a champ, and can be quite addictive. Smart guys like Ray Andraka could not live without it. :-) You can read more about applications of this nifty feature by clicking on http://support.xilinx.com/support/techxclusives/SRL16-techxclusive2.htm Peter Alfke, Xilinx Applications ================================== Kolja Sulimma wrote: > > During configuration the means of getting the configuration data into > the LUTs is a shift register anyway. > aArticle: 55113
Rudolf Usselmann wrote: > If all you need is PCI, check out the FREE PCI IP core at > OpenCores: www.opencores.org. Rudi, Thanks for the pointer. I had already downloaded the PCI core design from www.opencores.org and looked at it. The problem is that I am definitely going to need 64-bit PCI and possibly PCI-X, so that core isn't an immediate good fit. I am still looking at it though and came across the Northwest Logic core as a part of my ongoing research. Thanks again, BerendArticle: 55114
rickman wrote: > > All this talk about low pin count FPGAs got me thinking about my current > problem. I am looking for a small collection of board supervisory and > control funtions that I can't seem to find in a single chip. I can't > even get them in two or three chips since my combination of inputs for > power control and reset are not common. > > So I thought about using one of the more recent, very small 8 bit micros > to become a "super" supervisor and provide signals such as reset and > power enable along with a RTC and temperature shutdown. Even > considering that this will require using software, I think it will be > the simplest, smallest and cheapest solution available. > > The only problem is, I am having a hard time finding the "right" 8 bit > micro. This circuit needs to operate in temps of -40 to 125C. The rest > of the board will only be rated for 85C and this circuit will shut off > all power to the board to prevent damage from running above 85C. Seems > there are some places in the world that get pretty durn hot. The inside > of a locomotive sitting in a tunnel is one of them. > > So can anyone recommend a small, cheap, very low power MCU that will > operate over -40 to 125C, has flash (OTP might be ok), RTC (software is > ok if power level is very low), and can measure the temperature? I > originally was going to use a 1% thermistor on an ADC, but all the ADC > inputs are now taken. I guess the (small, cheap, simple) way to do the > temperature is to just pick a resistor value that will give me a trip > point, but then that requires a comparitor and a vref. > > I looked at the TMS430 and Cygnal parts and did not find anything that > is rated to run over that temp range. The Fairchild ACE MCUs come in an > automotive range, but have too few IOs, I need about 10 that I know of. > > I am not really up to date on automotive temp MCUs and not so current > with the 8 bit MCUs either. I guess I will take a look at Motorola and > Microchip next. I am getting to hate the web... Max temperature specs are a bit of a briar-patch. Vendors quote a Ta, when what they really worry about is Tj. I suspect they are trying to simplify things for the customer, but any uC designer can manage a thermal eqn :) Newer devices that push the TMAX up, are starting to quote Tj with correct Thermal resistances ( just like power devices use ). ABS-MAX Tj has not moved much, but they can push up their Ta MAX quite a bit using this approach. Cygnal spec a ABS MAX of 125'C, and commit to functional spec within -40-85'C so I'd talk with them to clarify what happens 85'C to 125'C. They do have on chip temperature reading, and do use a low-thermal-resistance MLF package, and it also sounds like you are running low clocks, so will have very low thermal adders. It also sounds like your > 85'C is not a long-term usage need, but just an extreme case coverage, to protect other devices from going above their ABS MAX Tj ? It's the same as SMD power device problems :- lower chip power, and lower package thermal resistance mean higher tolerable ambients. -jgArticle: 55115
Hello all,
I am in desperate and urgent need of help here. Thanks to my poor
programming skill, I've been almost sleepless for days trying to come
up with ABEL source code for a 4 bit Multiplier and Divider. Can
anyone provide any kind of help?
Grateful,
Steve
Article: 55116Jim Granville wrote: > > Max temperature specs are a bit of a briar-patch. > > Vendors quote a Ta, when what they really worry about is Tj. > I suspect they are trying to simplify things for the customer, > but any uC designer can manage a thermal eqn :) > > Newer devices that push the TMAX up, are starting to quote Tj with > correct Thermal resistances ( just like power devices use ). > ABS-MAX Tj has not moved much, but they can push up their Ta MAX > quite a bit using this approach. > > Cygnal spec a ABS MAX of 125'C, and commit to functional > spec within -40-85'C so I'd talk with them to clarify what > happens 85'C to 125'C. > They do have on chip temperature reading, and do use a > low-thermal-resistance MLF package, and it also sounds > like you are running low clocks, so will have very low > thermal adders. > It also sounds like your > 85'C is not a long-term usage > need, but just an extreme case coverage, > to protect other devices from going above their ABS MAX Tj ? > > It's the same as SMD power device problems :- lower chip power, > and lower package thermal resistance mean higher tolerable ambients. Thanks for your comments. I am aware of the issues of Ta vs. Tj. But I have to go by what the vendors spec. When they rate the chip functions at Ta of 85C and then say they have an absolute max Tj fo 125, I have to assume that this simply prevents damage between 85C and 125C, but that correct operation is not verified by them or guaranteed. The Cygnal chips seem interesting, but I quit looking at them hard when I could not find a good temperature range. The prices seem a little high, but that may just be my not looking hard enough. So far I have found viable chips at Motorola, National and Microchip. I expect that will be good enough. Now I just need to nail the specs and pick one based on features and availability. The only thing that worries me is using software to control the board saftey systems. I have no plans to use this board in medical equipment or other critical applications, but software always has a way of biting you in the rear. But then I guess hardware can do that too, it just seems to happen sooner. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 55117
rickman wrote: > All this talk about low pin count FPGAs got me thinking about my current > problem. I am looking for a small collection of board supervisory and > control funtions that I can't seem to find in a single chip. I can't > even get them in two or three chips since my combination of inputs for > power control and reset are not common. > > So I thought about using one of the more recent, very small 8 bit micros > to become a "super" supervisor and provide signals such as reset and > power enable along with a RTC and temperature shutdown. Even > considering that this will require using software, I think it will be > the simplest, smallest and cheapest solution available. > > The only problem is, I am having a hard time finding the "right" 8 bit > micro. This circuit needs to operate in temps of -40 to 125C. The rest > of the board will only be rated for 85C and this circuit will shut off > all power to the board to prevent damage from running above 85C. Seems > there are some places in the world that get pretty durn hot. The inside > of a locomotive sitting in a tunnel is one of them. > > So can anyone recommend a small, cheap, very low power MCU that will > operate over -40 to 125C, has flash (OTP might be ok), RTC (software is > ok if power level is very low), and can measure the temperature? I > originally was going to use a 1% thermistor on an ADC, but all the ADC > inputs are now taken. I guess the (small, cheap, simple) way to do the > temperature is to just pick a resistor value that will give me a trip > point, but then that requires a comparitor and a vref. > > I looked at the TMS430 and Cygnal parts and did not find anything that > is rated to run over that temp range. The Fairchild ACE MCUs come in an > automotive range, but have too few IOs, I need about 10 that I know of. > > I am not really up to date on automotive temp MCUs and not so current > with the 8 bit MCUs either. I guess I will take a look at Motorola and > Microchip next. I am getting to hate the web... > Given your constraints, Atmel's ATTiny26 seems a good fit too. It's rated for 85C but with -55 to +125C abs. maximum operating temp (+150C storage) and as self heating will be negligible, Jim Granville's remarks apply here (ATTiny26 is available in low-thermal-resistance MLF package). It's low cost, low power, have 6 more IO than you need (16 IO), Flash & data EEPROM, 10 bits ADC ... The embedded EEPROM allows, among other things, for easy initial room temperature calibration if you use a thermistor. You can give ATTiny26 a look here : http://www.atmel.com/dyn/resources/prod_documents/doc1477.pdf If you want a 8 pins / 6 IO (or 4 + crystal) device with similar features, the ATTiny15 will do : http://www.atmel.com/dyn/resources/prod_documents/doc1187.pdf Their development system (AVR Studio) is complete and free. AVR architecture / assembly is a lot better than what you get with PICs and they are optimized for "C", if you ever do more advanced functions). ISP is done using a standard SPI interface, and that makes sense too. I used the ATTiny15 few months ago for a simple power supply monitoring device and I had a very good experience with it ... For the temperature sensor, you can use low cost digital sensors such as this one from National ( -50C +150C ) : http://www.national.com/pf/LM/LM70.html LM77 adds 3 integrated programmable over temperature switchs (TLow / THigh / TCritical) : http://www.national.com/pf/LM/LM77.html my 0.02 Eric.Article: 55118
On Thu, 24 Apr 2003 22:04:31 -0400, rickman <spamgoeshere4@yahoo.com> wrote: ><snip> >This circuit needs to operate in temps of -40 to 125C. I know someone currently using the TI MSP430F149's at elevated temperatures, in production. They are used in an environment which operates at an ambient in the 150 C to 175 C temp range. (The tougher part, I'm told, was finding batteries to operate well, in that range.) Just a data point. JonArticle: 55119
In comp.lang.vhdl sharan <sharan_nagashetty@yahoo.com> wrote: : 1) How do you synchronise the bits as the data transmitted is in : serial mode..ie. when decoding... Obviously you need to know the start of the symbol (or what ever is sequence length of the Viterbi output). Usually there are some symbol start signals present(which are extracted from the control data by the demodulator). : 2) I would like to add Low power design features, can u tell me if u : have any idea to implement.. I don't have any magic stuff, just do as much in parallel as you can, with as low a frequency as possible and use gated clocks if brave enough :) But I guess you already knew that stuff... regards, juza : Thanks. : regards, : Sharan : Jussi Lähteenmäki <jusa@students.cc.tut.fi> wrote in message news:<b87v2b$m29$1@news.cc.tut.fi>... :> In comp.lang.vhdl vikas <vikas_akalwadi@indiatimes.com> wrote: :> I have been working quite a lot with viterbi, but feel somewhat inadequate :> to answer to your questions. I have always felt that the only things truly :> affecting the overall area consumption are the number of softbits and and :> the chosen traceback depth. Things beyond those are merely bits and :> pieces. Anyhow, my intention was to tell you that I have access to those :> ieee papers, so if you drop me a mail I can send them to you in return. I :> don't really know how legal it is to do so, but it can never be too :> illegal to share knowledge (yes I am a researcher :) )... :> :> regards, :> juza :> :> :> : 3. After survival data equal to trace back deapth has been stored, we :> : start trace back. If we are to start the traceback with lowest partial :> : path metric, how do we determine that state if we do "localised :> : normalisation" :> :> : 4. What are the different techniques for trace back operation ? :> : Since i am implementing it on hardware, functionality, area and timing :> : all are very important. :> :> : expecting reply, :> : regards, :> : Vikas -- JuzaArticle: 55120
> So, do you sort of want the Amba split transaction feature or do you want > to have a general transaction queue? > > The split transaction feature allows the bus to be freed while a slave > device completes the transaction, but the slave will accept no additional > requests. In the meantime other slave devices may be addressed. > > A transaction queue implies that a master can issue a number of > transaction requests to an arbitrary number of slaves without stalling. > This is tricky, especially with reads. > > Ben Yes, a kind of transaction queue would be fine. And i know it is tricky! That's why I posted here ;-) I know AMBA has split transaction, but I tried to use Wishbone for that. I now have to admit, Wishbone is not the optimal protocol for that. My idea is to develop an universal bridge module, which can wrap requests on an existing PCB-bus system, and which is fully transparent to the on-chip cores, and has a defined interface in order to cope with on chip protocols. regards chris.Article: 55121
On 23 Apr 2003 09:26:28 -0700, rdschwarz@spamcop.net (Zeke) wrote:
>
>Check at http://www.associatedpro.com APS still carries Virtex boards
>in a small form factor. PC104 or stand alone
>
>It seems like XILINX also quit placing the third party board links on
>its website., or it is incomplete. Neither APS nor Xess are listed ,
>nor is Annapolis Micro or many others. Maybe that is influencing the
>board vendors.
There is a well maintained list of boards at
http://www.fpga-faq.com/FPGA_Boards.htm
===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM
Article: 55122On Wed, 23 Apr 2003 20:07:33 +0200, "Frederic Bastenaire" <frederic.bastenaire@wanadoo.fr> wrote: >Great! I posted questions about this but never got anything concrete. This >is interesting and partly answers my questions. >I have extra questions (sorry) : That ok. Many people post questions to comp.arch.fpga >- Is there any VHDL similar example? No, I only have it in Verilog. Also the code I posted is not an "example", it is actual code from an actual project. >- What software do you use to play with the JTAG USER1 commands on the PC >side? The host side software is in two pieces. An application, and a low level JTAG driver. The application code is totally application specific, and I wont post it. The JTAG driver code is application independent, and is linked in with the application code. (i.e. it runs in user mode, not kernel mode). This driver contains proprietary code so I can't post it. The JTAG driver makes calls to a lower level kernel mode driver that does the actual I/O to the JTAG cable. This is in a Windows NT/W2000 environment. An example of such a driver is: http://www.driverlinx.com/DownLoad/DlPortIO.htm although this is not the one I am using. >Thanks for your help, > >Frederic Bastenaire > >"Philip Freidin" <philip@fliptronics.com> a écrit dans le message de news: >n7hv9v438bfif84cg3mjoaeim15b3qkla0@4ax.com... >> You need to create your own data register, and connect it to >> the JTAG primitive. >> >> For your entertainment, here is an example of doing it for >> Virtex-II. >> >> > (...) >> Philip Freidin >> Fliptronics > Philip Freidin FliptronicsArticle: 55123
On 26 Apr 2003 03:50:21 -0700, nachikap@yahoo.com (Nachiket Kapre) wrote: > >How does a Virtex implement a shift register in the same LUT? An LUT >is basically a RAM with an address bus and a single bit read/write >data bus. Are there special routes inside the LUT that write back the >most significant n-1 ( n= size of the SR) bits alongwith the newest >bit back into the same LUT? How are the bits physically moved inside >the RAM? > >regards, >Nachiket Kapre. >Paxonet Communications Inc. Whenever you have questions about how stuff is implemented in an FPGA, the US patent office often has the information available, and often in a more acurate form than you are likely to get in this news group (guesses that are often wrong). For this question, try this: www.uspto.gov Go to the search page and look at the following patents 6373279 FPGA lookup table with dual ended writes for ram and shift register modes 6388466 FPGA logic element with variable-length shift register capability 6445209 FPGA lookup table with NOR gate write decoder and high speed read decoder Philip Freidin Philip Freidin FliptronicsArticle: 55124
Firstly you might consider VHDL or verilog either would be simpler and you might get some hits from others here, then go back to first principles on long division and long multiply. The same rules apply to base 10 and base 2. Another good pointer is look at source code for a processor it is basically done the same in hardware. P.S. if your designing a PAL .. there's a reason why its difficult to write multiply in able .. its difficult to fit too :-) Simon "Steve" <pheyhing@yahoo.com> wrote in message news:cc72c839.0304271939.677aab12@posting.google.com... > Hello all, > I am in desperate and urgent need of help here. Thanks to my poor > programming skill, I've been almost sleepless for days trying to come > up with ABEL source code for a 4 bit Multiplier and Divider. Can > anyone provide any kind of help? > Grateful, > Steve
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