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Hey All, Im using a XC2S300E and a 5V CPU. The XC2S300E implements a simple memory interface to the CPU. My question is related to using the 5V CPU with the 3.3V XC2S I/O Pins. In a past design i've used a XC95288 (CPLD), and had to use strong pull up resistors (<1K to 5V) to meet the timing requirements of the bus, along with floating the Xilinx I/O Pins to implement a bi-directional interface. In this new design its not suitable to use such a "dodgey" method of interfacing. Can anyone suggest any possible solutions I could try? Thanks in advance. Lockie.Article: 62601
In article <bo2uce$mpq$1@wsc10.lrz-muenchen.de>, 5ebNOSPAM@NOSPAMgmx.net says... > Hello! > > I've searched Xilinx' knowledge-base and this group to no extend. > When I run "Implement Design" on any project (also example-projects) for > a XC9500 I get a > > Mapping a total of 23 equations into 2 function > blocks......................... > java.lang.RuntimeException: Attempting to format number '0.0' using > pattern ''. > at > org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1063) > at > org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1071) > ... > > from the "Fit" and later the "Generate HTML report"-processes. > > Obviously, this is a Java-problem. As far as I've seen the Webpack uses > it's own version of the JRE in java\nt\jre, so I don't think this is a > problem with my JRE-installation. > > I've got the latest SP installed. > > Any ideas? > > Thanks, > Seb > > I have the same problem. I'm using german XP, and I think it comes from using an OS with different language settings, probabely from formatting a number with commas, instead of periods. Best regards -- Klaus Falser Durst Phototechnik AG kfalser@IHATESPAMdurst.itArticle: 62602
We have been working with Xilinx parts for the past 4 years. Whenever I had problem the local FAE couldn't solve I used the Xilinx WEB case system. I always got very fast and professional response, usually within the same working day. Recently we decided to use Altera Cyclone part in a new design. When we ran into problems I opened a web case using "Altera's my support". After two days of silence I added an update explaining why the problem is urgent. After 10 days !!! I got the first response asking for the name of the local FAE and providing no more information. I answered the question and in exchange I got email saying "your service request will be closed" . Did anyone else had this kind , maybe better ?, experience with Altera web support ? I think that as FPGAs become more and more complicated, and design cycles shorter, the support level is becoming one of the key factors when selecting an FPGA. Cheers, RotemArticle: 62603
Hi! Thanks for your tip, it works flawlessly now. I use the english XP but had german-Region settings (numbers are 10,5 instead of 10.5 here), that was the problem. Xilinx should fix this, I'll file a bug-report. Regards, Seb Klaus Falser wrote: > In article <bo2uce$mpq$1@wsc10.lrz-muenchen.de>, 5ebNOSPAM@NOSPAMgmx.net says... > >>Hello! >> >>I've searched Xilinx' knowledge-base and this group to no extend. >>When I run "Implement Design" on any project (also example-projects) for >>a XC9500 I get a >> >>Mapping a total of 23 equations into 2 function >>blocks......................... >>java.lang.RuntimeException: Attempting to format number '0.0' using >>pattern ''. >> at >>org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1063) >> at >>org.apache.xalan.xsltc.runtime.BasisLibrary.runTimeError(BasisLibrary.java:1071) >>... >> >>from the "Fit" and later the "Generate HTML report"-processes. >> >>Obviously, this is a Java-problem. As far as I've seen the Webpack uses >>it's own version of the JRE in java\nt\jre, so I don't think this is a >>problem with my JRE-installation. >> >>I've got the latest SP installed. >> >>Any ideas? >> >>Thanks, >>Seb >> >> > > I have the same problem. > I'm using german XP, and I think it comes from using an OS with > different language settings, probabely from formatting a number with commas, > instead of periods. > > Best regards >Article: 62604
I assume its still correct.. but there have often been FPGA's which are pin bound.. that is there are more I/O's internally than there are pins.. that's why the same device fits into a TQ144 and a TQ208 with no free pins. Simon "kryten_droid" <kryten_droid@ntlworld.com> wrote in message news:hRipb.1394$wY2.963@newsfep1-gui.server.ntli.net... > "Simon Peacock" <nowhere@to.be.found> wrote in message > news:3fa45ff8$1@news.actrix.gen.nz... > > I think you will find that you have over committed the pinout of the > device. > > For some reason this isn't always classified as a fatal error :-) > > Checked out the chip and there are only 146 I/O pins. > > Although my user config file only said that only 123 were used, > the design still had more I/O blocks than the device could bond to pins. > > So even though the design could theoretically fit, if the UCF was > considered, the place-and router would reject the design. > > D'oh! > > So I removed a load of I/O that was just redundant test signals > and the software has compiled and fitted the design. > > >Article: 62605
I don't know of any good books.. but.. FPGA's can run rings around code... especially if you can define what you want them to do. that's the tricky part... and as far as parallel processing is concerned.. they will blow your mind.. or sit there flashing a light...Xilinx are working on a JAVA compiler for FPGA's. I think its a student partnership thing so am not sure how good it is but it converts java into hardware. And FPGA's will eat any cluster.. just see above.. But if you can't define the problem in a way the FPGA can handle then it would be no faster. FPGA's are literally OR's AND's and flip flops (latches) and that's what you need to start with.. they also have adders and even processors.. small memories and stuff like that.. if you need large memory they can do that too. its hardware.. want SDRAM ? just connect it up and write a program to access it. (just don't forget to refresh it too :-) There are already a number of super cluster FPGA projects around. One of the fusion reactor projects uses several hundred of them .. I read an article once.. don't remember the web site sorry. Simon "mikegw" <mikegw20@hotmail.spammers.must.die.com> wrote in message news:bo4na0$5qk$1@tomahawk.unsw.edu.au... > Hello all, > > Firstly I would like to say that other than knowing what a FPGA is on a most > basic level my knowledge about the subject is nil. I am looking at this > from an application that needs a solution. I have seen about the place add > on boards for PC's that act as co-processors. This is the interesting bit > to me. Our research group is looking into building a computer (cluster > perhaps) for calculation of particle dynamics, similar to CFD in > application. Our programs are in C/C++ running on Linux ( any flavour will > do). > > My questions are > > a) Will a FPGA co-processor board(s) offer a speed improvement in running > our simulation jobs over using a 'traditional' cluster (mosix/Bewoulf)? > Bearing in mind that ours will be the only job on the machine so can we > reconfigure our FPGA boards to speed calculation? > > b) Can anyone recommend a good book that I can read and hopefully be able to > ask more informed questions? > > Cheers > > Mike > >Article: 62606
I would suggest that you use a proper reset chip to reset the FPGA and then you can use a simple machine to generate resets going out. FPGA's have always been a little problematic starting up in my experience I believe that its due to the power supply dipping :-).. never been proved but the always work floorlessly with a clean reset. (rather than floorless .. as in bottomless pit) Simon "Tullio Grassi" <tgrassi@cut_here.mail.cern.ch> wrote in message news:Pine.LNX.4.44.0311022103250.23452-100000@lxplus020.cern.ch... > I'd like to use my Virtex2 to generate an off-chip power-on-reset, > for other devices on the board. > I thought about bringing the internal GSR signal to a pin, but > Xilinx support (Case # 503734) said it's impossible. > > I am thinking about a state machine like that: > > Start --> POR --> Stop > > that will remain in "Stop" forever. > I am worried about illegal transitions/states creating a mess > on the board. Comments ? > -- > Tullio Grassi > > ===================================== > Univ. of Maryland-Dept. of Physics | > College Park, MD 20742 - US | > Tel +1 301 405 5970 | > Fax +1 301 699 9195 | > ====================================== >Article: 62607
Actually the main problem with that batter is the word lithium :-) something about the quantity allowed on airplanes :-) Simon "Erik Widding" <widding@birger.com> wrote in message news:Fkcpb.66878$1C5.30471@nwrdny02.gnilink.net... > "Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote... > > > > Erik, are you not in danger of over charging the battery? > > > > Don't phone batterys degrade fairly quickly if they're > > constantly trickle charged rather than being fully > > discharged then re-charged? Are the characteristics > > of your batterys different? > > Have you done any long term tests with this set up? > > The battery that we use is a Niobium-Lithium (NBL) from Panasonic. > More information: > http://www.panasonic.com/industrial/battery/oem/chem/lith/niobium.htm > > Austin's post that parallels this one, makes the very important > point that few engineers bother to understand battery chemistry > or even read the data sheets (Nial - this is not directed at you). > > The major point is Lithium-Ion batteries have a bunch of problems > that are a trade off against the extremely high energy per unit > volume, and the capability of providing high currents (discharge > entire battery in 1 hour), that makes them desireable for cell > phones for example. > > NBL batteries are basically everything that a LiIon battery isn't. > Very low self discharge (2%/year), not capable of providing much > current (discharge the entire battery in no less than 400 hours) and > with probably the crappiest energy per unit volume rating of > any commercially viable battery on the market. This is the perfect > (or as perfect as was available two years ago when we qualified it > for design use) battery chemistry for this application. > > There are a lot of battery chemistries available. No single > chemistry is right for every application. With fuel cells on the > way shortly, we will soon have yet another option to understand. > > > > Regards, > Erik Widding. > > --- > Birger Engineering, Inc. -------------------------------- 617.695.9233 > 100 Boylston St #1070; Boston, MA 02116 -------- http://www.birger.com > >Article: 62608
Erik Widding <widding@birger.com> wrote in message news:Fkcpb.66878$1C5.30471@nwrdny02.gnilink.net... > "Nial Stewart" <nial@spamno.nialstewart.co.uk> wrote... > The battery that we use is a Niobium-Lithium (NBL) from Panasonic. > More information: > http://www.panasonic.com/industrial/battery/oem/chem/lith/niobium.htm > > Austin's post that parallels this one, makes the very important > point that few engineers bother to understand battery chemistry > or even read the data sheets (Nial - this is not directed at you). No problem, I've never had to use embedded batteries, it was just a general interest query. > The major point is Lithium-Ion batteries have a bunch of problems > that are a trade off against the extremely high energy per unit > volume, and the capability of providing high currents (discharge > entire battery in 1 hour), that makes them desireable for cell > phones for example. > NBL batteries are basically everything that a LiIon battery isn't. > Very low self discharge (2%/year), not capable of providing much > current (discharge the entire battery in no less than 400 hours) and > with probably the crappiest energy per unit volume rating of > any commercially viable battery on the market. This is the perfect > (or as perfect as was available two years ago when we qualified it > for design use) battery chemistry for this application. > There are a lot of battery chemistries available. No single > chemistry is right for every application. With fuel cells on the > way shortly, we will soon have yet another option to understand. > Regards, > Erik Widding. Thanks for the info Erik, this could be useful backround for a design I've had in mind for some time. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 62609
Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:3FA28A84.AAA1FE7A@xilinx.com... > Nial, > Go look thru the design guides for the battery chemistry you want to use: I haven't wanted to use any yet, hence the ignorance. > you will be glad you did. I'm sure I will, when I have :-) Nial.Article: 62610
Mike Treseler <mike.treseler@flukenetworks.com> wrote in message news:<3FA2FC98.4030800@flukenetworks.com>... > Kevin Neilson wrote: > > Can anybody else explain how Shannon's information > > theory applies to black holes? > > Sounds like just the place for a > First In Never Out (FINO) transmit buffer. > > -- Mike Treseler I had to debug somebody else's hardware that implemented a FINO He had invented the wonderful new memory type... 2K by 8 WOM Write-Only Memory :-) IanArticle: 62611
Does anyone still have Synplify Pro version 7.3.1? Could you please give it to me or let me know where should I get it? Thanks a lot. cheers, moonygals@yahoo.comArticle: 62612
"Simon Peacock" <nowhere@to.be.found> wrote in message news:3fa621eb@news.actrix.gen.nz... > I don't know of any good books.. but.. FPGA's can run rings around code... > especially if you can define what you want them to do. that's the tricky > part... and as far as parallel processing is concerned.. they will blow your > mind.. or sit there flashing a light...Xilinx are working on a JAVA compiler > for FPGA's. I think its a student partnership thing so am not sure how good > it is but it converts java into hardware. > > And FPGA's will eat any cluster.. just see above.. But if you can't define > the problem in a way the FPGA can handle then it would be no faster. FPGA's > are literally OR's AND's and flip flops (latches) and that's what you need > to start with.. they also have adders and even processors.. small memories > and stuff like that.. if you need large memory they can do that too. its > hardware.. want SDRAM ? just connect it up and write a program to access it. > (just don't forget to refresh it too :-) > > There are already a number of super cluster FPGA projects around. One of > the fusion reactor projects uses several hundred of them .. I read an > article once.. don't remember the web site sorry. > > > Simon > > Thanks Just so I understand you, if I want to "realise" my c code in a FPGA array, I can upload the code, data and the processing array. Run it and download the data? The code (not actually mine I am just seeing if this is all possible) is basically applying an equation on a data set looping for all particles for each time step. The tricky bit (in at least the programming sense) is to constantly calculate the relative positions of each particle to calculate their effect on each other. I would really like it if there exists such a book that could take someone who has a c/c++ program and hold their hand through a whole "Realisation" of that code. Cheers MikeArticle: 62613
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message news:ZzCob.71991$Fm2.57178@attbi_s04... > I read an article in "Scientific American" about how much information can be > compressed into a certain volume, and apparently all objects have a Shannon > entropy in addition to the thermodynamic entropy. Also, black holes have a > Shannon entropy that is based on the surface area of the event horizon. I > was totally lost. Can anybody else explain how Shannon's information > theory applies to black holes? > -Kevin > > For the ignorant (me): what it Entropy? RichArticle: 62614
Please look Xilinx website, there are good advice about the reset system. You can do proper reset signal inside the FPGA. If you have an onboard FPGA, you don't need to add a expensive external reset chip. You can generate a synchronous reset signal inside your FPGA and drive external rst from your synchronous reset. Laurent www.amontec.com Simon Peacock wrote: > I would suggest that you use a proper reset chip to reset the FPGA and then > you can use a simple machine to generate resets going out. > > FPGA's have always been a little problematic starting up in my experience I > believe that its due to the power supply dipping :-).. never been proved but > the always work floorlessly with a clean reset. (rather than floorless .. as > in bottomless pit) > > Simon > > > "Tullio Grassi" <tgrassi@cut_here.mail.cern.ch> wrote in message > news:Pine.LNX.4.44.0311022103250.23452-100000@lxplus020.cern.ch... > >>I'd like to use my Virtex2 to generate an off-chip power-on-reset, >>for other devices on the board. >>I thought about bringing the internal GSR signal to a pin, but >>Xilinx support (Case # 503734) said it's impossible. >> >>I am thinking about a state machine like that: >> >> Start --> POR --> Stop >> >>that will remain in "Stop" forever. >>I am worried about illegal transitions/states creating a mess >>on the board. Comments ? >>-- >>Tullio Grassi >> >>===================================== >>Univ. of Maryland-Dept. of Physics | >>College Park, MD 20742 - US | >>Tel +1 301 405 5970 | >>Fax +1 301 699 9195 | >>====================================== >> > > >Article: 62615
> > It would be nice if there were a script/program that would > take an intermediate file and make both the schematic library > parts and the pin constraints file for the FPGA. Or something > like that - the idea is to make sure they were kept in sync. > Apologies if this is of no use (my third post in FPGA land). Is http://sourceforge.net/projects/pinout/ of any use? Cheers MikeArticle: 62616
"mikegw" <mikegw20@hotmail.spammers.must.die.com> wrote in message news:<bo4na0$5qk$1@tomahawk.unsw.edu.au>... > Hello all, > > Firstly I would like to say that other than knowing what a FPGA is on a most > basic level my knowledge about the subject is nil. I am looking at this > from an application that needs a solution. I have seen about the place add > on boards for PC's that act as co-processors. This is the interesting bit > to me. Our research group is looking into building a computer (cluster > perhaps) for calculation of particle dynamics, similar to CFD in > application. Our programs are in C/C++ running on Linux ( any flavour will > do). > > My questions are > > a) Will a FPGA co-processor board(s) offer a speed improvement in running > our simulation jobs over using a 'traditional' cluster (mosix/Bewoulf)? > Bearing in mind that ours will be the only job on the machine so can we > reconfigure our FPGA boards to speed calculation? > > b) Can anyone recommend a good book that I can read and hopefully be able to > ask more informed questions? > > Cheers > > Mike Hi Mike Think of a coprocessor as a black box with input output channels that sits in your PC. The computing elements may be a fraction of the speed of a 3GHz P4 at some things or maybe many orders of magnitude more. I am guessing that your app needs FP calculations, maybe IEEE, maybe any adhock FP will do. The IEEE is still costly to do in FPGA but see a previous post for some pointers. An adhock FP may be all thats needed but you would have to do a similar version in SW for a unaccelerated node to get same results. Where FPGA boards really shine is when you can arrange for them to be in series with streaming data that that may be orders faster than a PC could normally handle. If your data is on HD and has to come through PCI bus then you are IO bound. That may be ok if you can perform N million comps per word transfered such as say crypto but if you needed to do minimal comps per point, FPGA can be wrong solution. Figure how much parallelism you can extract. P4 may run at 3GHz. An FPGA board may run at 50MHz to 200MHz, if you perform integer *+ that may limit to 100MHz. So you need to be doing atleast 30x more in parallel just to match 1 P4. If you can do an order more in parallel than that, then you could be doing fine as long as you aren't IO bound. Consider a faster PCI bus that will get you a few x more throughput. Consider if you can dump one time all data into onboard ram on PCI board, ie get the PC out of the eqn except for basic system support. Take alook at TimeLogic Decypher board as an example of Bioinformatics that get accelerated at similar rates to your app, but AFAIK its mostly pattern matching & integer comps. Can't say I heard of any books on this matter as its still immature field! Good luck johnjaksonATusaDOTcomArticle: 62617
Hello,
there is an application note from Xilinx: XAPP130 (v1.4)
http://www.xilinx.com/bvdocs/appnotes/xapp130.pdf
On page 4 there is table 3: Port Address Mapping.
There are some formulas given for Start and End.
My question: What do Start and End mean?
What is the meaning of ADDRport(Read or Write?)?
What is the meaning of Widthport(Read or Write?)?
Maybe someone can it explain on some example:
write port data width[0..0]
write address [14..0]
read port data width [9..0]
read address [31 ..0]
How can the formulas be applied to this example?
Thank you for your help.
Kind regards
Andres Vazquez
G&D System Development
Article: 62618hmurray@suespammers.org (Hal Murray) writes: > >Doing a board design with a 456 pin Xilinx FPGA, I find myself in the > >laborious and potentially error-prone process of building a symbol, > >footprint and part model from scratch. ... > <snip> > It would be nice if there were a script/program that would > take an intermediate file and make both the schematic library > parts and the pin constraints file for the FPGA. Or something > like that - the idea is to make sure they were kept in sync. > Mentor have this - it's called Boardlink. It reads the PAR tool output and then can automatically, or with guidance, create a fragmented set of symbols for use in your schematics. They also have Boardlink Pro which allows you to do pin assignment upfront in a nicer place than either PACE or Altera's pin assigment GUI (that's their claim, I haven't used it :-)... <snip> > > What I've done on many occasions is to collect paper copies of > all the data sheets and net lists (both by net and by part/pin) > and all the other info you think might be interesting, and take > over a conference room with a big table and do a check-everything > level design review just before the board goes out. And gerber > plots and ... Get somebody to check everything you can think > of to check. They don't have to know much about your design, > just have enough experience and common sense to read the data > sheets and schematics and see if the connections make sense. > (Double-double check the bubbles/inversions.) > And RS232 Tx and Rx :-) <snip> -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 62619
Hi all, I have recently started to look into FPGA defect and fault tolerance, I was wondering if anyone could suggest a book or paper I could read reflecting what has been done in the field. Thanks, NickArticle: 62620
Steve, It will support - all Xilinx components, FPGA CPLD EEPROM FLASH configuration over JTAG (programm + verify, with X devices on the JTAG chain) - FPGA configuration SLAVE SERIAL MODE - True I2C generic port for onboard I2C-EEPROM configuration and other I2C-chip configuration. We will add more features in the future. I will do notification on the begin of 2004 when our pockeTAG is ready to use and buy. Laurent www.amontec.com Stephan Buchholz wrote: > Laurent: > > Do you have a target date for the release of the USB based JTAG pod? > Also any specs on what it will support? > > Steve Buchholz > > "Amontec Team, Laurent Gauch" <laurent.gauch@amontecDELETEALLCAPS.com> wrote > in message news:3f9e8436$1@news.vsnet.ch... > >>Henk van Kampen wrote: >> >>>Dear Laurent: >>> >>> >>> >>>>Could you explain what we can do with your JTAG option ? Can we do >>>>on-chip PicoBlaze debugging or ROM download ? >>> >>> >>>That is the idea. You can generate an SVF file by including in your >>>source file: >>> SVF "testjtag.svf" >>> >>>It will generate an SVF file based on the specifications in the JTAG >>>tab of the settings dialog and your source. Since this is still in its >>>infance please let me know is this is useful or what to change/add. >>>Since your are an probably an expert on JTAG considering your >>>Chamelion product I welcome your advice. >>> >> >>We are interested to do something in this way. >>I will ask my Team about the idea to do a OCD (On-Chip Debug) solution >>for the PicoBlaze. >> >>We have a relative good knowledge about JTAG on Arm processor. >>For the PicoBlaze, we have to add, in the PicoBlaze, a small register >>bank for On-chip debug solution including breakpoint fsm and to read >>back the PicoBlaze registry. We have naturally to think about the >>possibility to chain multi-PicoBlaze boundary Scan together >> >>Do you know if Xilinx have a support or source for On-chip debug >>machanism on JTAG ... other way we will do that! >> >>Then, we will use our new very low cost pockeTAG POD based USB to play >>the JTAG TAP to accelerate the job. >>And we will give you instructions for upgrade your software with our OCD >>solution, to be able to mark the breakpoint and to execute the on-chip >>debugging step. >> >>Our new POD will be about $89.-, and can run JTAG trace at the same >>speed that Cable IV (for download without verify, we are a better >>datarate on the JTAG !) but it works over USB with the big advantage of >>the power from USB, on MS and Linux. JTAG target can be 1V, 1.2V, 1.8V, >>2.5V and 3.3V with 5V IOs tolerant! It can be a good solution for this >>JOB too. A low cost On-chip debug solution for a free Picoblaze Processor! >> >> >>>>Actually, we are working on reconfigurable high speed automat machine. >>>>We will try to use picoblaze as base. One automat will have about 10 to >>>>100 picoblaze. The goal is to keep the speed and true multi-processing >>>>achitechture of sequencial function. >>> >>> >>>Very interesting. You will, however, need a lot of blockrams. And with >>>the JTAG option you can not use two PB's with one blockram. By the >>>way, how do you want to let the PB's communicate? One of my own wishes >>>for pBlazIDE is to be able to simulate several PB's in cooperation. >>>This will need some for of inter I/O port, which needs to be simulated >>>and therefore some how specified. I also have used more than 1 PB in a >>>design and have them communicate but that was by some form of >>>dual-ported RAM. So let me know what your ideas are. >> >>Yes you right, and when I saw the SPARTAN-III architecture, I thinking >>this was not a good idea. The RAM is bigger, but too much regrouped for >>this JOB. >> >>But for the first run we will do the job with 10 Picoblazes. >> >> >>>Henk van Kampen >>>www.mediatronix.com >> >>Before, we have to contact Xilinx if they are interested or if that too >>much for this small PicoBlaze. >> >>Laurent Gauch >>www.amontec.com >> >> >> > > >Article: 62622
Mike Silva wrote: > I'd like to thank everybody who answered my questions. Very helpful > group here! I've downloaded some tools and ordered some books, and > I'll just hope not to disturb the horses. > > BTW, is there some convenient list "ranking" the various FPGA families > available, in terms of size (however that might be measured), and > cost? > > Also, where do CPLDs end and FPGAs begin? Is there some fundamental > difference in architecture that draws the line, or is it just a size > thing, or??? Are all CPLDs smaller than all FPGAs? (again, however > that might be measured) From reading your posts on this thread it looks like you're in a similar position to how I was not so long ago when I was just starting to learn about FPGAs and HDL coding so I thought you might like to know some of my mistakes so you can avoid them. The best advice from this thread was from Matt North when he said: "This is because languages like VHDL are HARDWARE description languages, you code should be written is such a way that a synthesis tool can recognise it as a counter, memory, mux etc." which is something that I read on this group when I started out, but didn't really appreciate how important this fact is. So I got advice about which book to learn VHDL from and I bought The Student's Guide to VHDL by Ashenden, starting reading it alongside Digital Systems Design Using VHDL by Roth and all along I had the feeling that there was something wrong with the way both books were teaching the subject, and recently I found out what it is and it is that the Ashenden book just teaches the VHDL language from a theoretical basis, which means that it is good as a reference book to learn the language but if you want to synthesize your VHDL code to make something that actually works then this book (and the book by Roth) doesn't teach you how to do it. So what I'd suggest is to buy one or two books that concentrate on the synthesis side of things so that you learn what code will synthesize to what hardware right from the start rather than just reading about the VHDL language. After doing a bit of research into what books have been recommended on here and on amazon.com I bought the following books: VHDL for Programmable Logic, by Kevin Skahill - http://tinyurl.com/tg4l Digital Systems Design with VHDL and Synthesis, by K.C. Chang - http://tinyurl.com/tg54 The first one has been mentioned on here favourably a few times and gets good reviews on amazon and from what I've read of it so far it is very well written and it is answering the questions that have been left unanswered for me when reading the other books. It's pretty basic, but that's exactly what you need when you're just starting out and I certainly wish I'd have started reading this book first. The other books is a bit more advanced and I've not started reading it yet because I'm going to read it straight after the book by Skahill but it gives you a load of VHDL code for real cicruits and explains the code and what hardware the synthesizer produces. I can't tell you whether it is badly written yet (one of the people who've reviewed it on amazon said it's badly written) but from flicking through it it looks at just the right level for when I'll have finished reading the book by Skahill. As others have said, there's masses of free literature on the Xilinx website as well. -- Steve - http://www.digitalradiotech.co.uk/ - Digital Radio News & InfoArticle: 62623
I wonder why FPGA Express can't directly infer 5 input LUT, a feature of virtex (even xc5200), even for obvious expression such as: y <= a and b and c and d and e; Would anyone tell the workaround, if any, to this problem. Thank you. Regards, Taufik SiswantoArticle: 62624
Marc Randolph <mrand@my-deja.com> wrote: > Mike Silva wrote: > > Also, where do CPLDs end and FPGAs begin? Is there some fundamental > > difference in architecture that draws the line, or is it just a size > > thing, or??? Are all CPLDs smaller than all FPGAs? (again, however > > that might be measured) > > As you appear to have surmised, there are some very high end CPLDs that > would, in some cases, do more than low-end FPGA's. Thats right for a specific kind of problem. A fpga with 1000 logicgates could be seen as a box with 1000 NAND2s you could do nearly any logic. A CPLD would offer you (fictive example) a the same time a box with 200 Nands followed by 50 4bit-adder followed by 50 registers. So your logic is limited to a smaller degree of freedom. So the line between CPLD and FPGA is the degree of freedom you've got to rearange the logic. > We've found that FPGA's can be used to do most things that CPLD's do > [except FPGAs must be programmed upon power-up], but not the reverse. Neither fusebased FPGAs nor Fpgas with flashram need to be programmed during power-up. I think there is nothing a CPLD could do that a FPGA can't but sometimes a CPLD is cheaper or needs less power or area. bye Thomas
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