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Messages from 60475

Article: 60475
Subject: Re: Spartan 3 ICAP primitive
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 15 Sep 2003 11:31:18 +1000
Links: << >>  << T >>  << A >>
Hi Antti,

Antti Lukats wrote:
> Xilinx what is correct in ISE 5.1 schematics editor the ICAP primitive
> doesnt show, but if looking at XDL output then ICAP primitive does
> exist ?!
> 
> I was very disappointed to see that Spartan 3 doesnt have ICAP 
> (i.e. self reconfig) but it seems it is there?

Spartan3 is basically a Virtex2, trimmed down in various ways.  The 
internal logic is pretty much identical as far as I can gather (CLBs, 
IOBs etc).

So, physically there's probably an ICAP hiding in every Spartan3, it's 
just hidden by the tools.  The philosophy seems to be that 
self-reconfiguration is still an experimental/research concept, and as 
such doesn't have a place in Spartan3, which Xilinx views and markets as 
a commodity FPGA.

Note also that Jbits now supports Virtex2, but don't hold your breath 
waiting for Jbits for Spartan3 - the same thinking probably applies.

Bitstream hacking could probably uncover the S3's ICAP - Virtex2 and 
Spartan3 bitstreams will likely have much in common.

Regards,

John


Article: 60476
Subject: Re: logic from jed file
From: Andrew Paule <lsboogy@qwest.net>
Date: Sun, 14 Sep 2003 22:36:20 -0500
Links: << >>  << T >>  << A >>
I'd email hotline@xilinx.com - they bought the able compilers from 
dataio, and the jed2abl utility was part of that.

Andrew

jb wrote:

>In message <3mP8b.824$TJ.103957@news.uswest.net>
>          Andrew Paule <lsboogy@qwest.net> wrote:
>Hi
>
>
>  
>
>>jed2abl - get it from xilinx free
>>    
>>
>
>any chance of a URL.. its not obvious on th xilinx site..
>
>Thanks
>
>John
>  
>
>>Andrew
>>
>>jb wrote:
>>
>>    
>>
>>>Hi Folks
>>>
>>>I have a maintenance need to recover a compilable source fronm the jedec
>>>fusemap file for a lattice ispmach96/48 device.
>>>
>>>Can anyone suggest a tool for the job.. or am I to resort to a dumb
>>>manual method?
>>>
>>>Thanks
>>>
>>>
>>> 
>>>
>>>      
>>>
>
>  
>


Article: 60477
Subject: Re: Spartan 3 ICAP primitive
From: rickman <spamgoeshere4@yahoo.com>
Date: Mon, 15 Sep 2003 00:12:36 -0400
Links: << >>  << T >>  << A >>
John Williams wrote:
> 
> Hi Antti,
> 
> Antti Lukats wrote:
> > Xilinx what is correct in ISE 5.1 schematics editor the ICAP primitive
> > doesnt show, but if looking at XDL output then ICAP primitive does
> > exist ?!
> >
> > I was very disappointed to see that Spartan 3 doesnt have ICAP
> > (i.e. self reconfig) but it seems it is there?
> 
> Spartan3 is basically a Virtex2, trimmed down in various ways.  The
> internal logic is pretty much identical as far as I can gather (CLBs,
> IOBs etc).
> 
> So, physically there's probably an ICAP hiding in every Spartan3, it's
> just hidden by the tools.  The philosophy seems to be that
> self-reconfiguration is still an experimental/research concept, and as
> such doesn't have a place in Spartan3, which Xilinx views and markets as
> a commodity FPGA.
> 
> Note also that Jbits now supports Virtex2, but don't hold your breath
> waiting for Jbits for Spartan3 - the same thinking probably applies.
> 
> Bitstream hacking could probably uncover the S3's ICAP - Virtex2 and
> Spartan3 bitstreams will likely have much in common.

Looks like I have not done my homework on this.  I had done some
research on modular configuration which was what I required.  The
Spartan lines seem to be supported for this although they don't yet list
the Spartan3 chips.  But I was under the impression that partial
configuration was the down load technique to support this in the
devices.  I see that only Virtex and Virtex-II are supported by partial
configuration.  This is not good.  

What is up with this?  I guess there may be other reasons to use partial
configuration other than cost, but I would expect this to be the main
driver.  If I don't care about cost, I can just implement all of the
possible configurations at the same time and mux the IOs.  If I care
about cost, I certainly don't want to be forced to use the Virtex or
Virtex-II chips.  The Spartan chips are all about cost.  

So why the disconnect on partial configuration Xilinx?  Why not support
Spartan-3 devices?  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX

Article: 60478
Subject: Re: Verlog 2001 signed numbers
From: sharp@cadence.com (Steven Sharp)
Date: 14 Sep 2003 21:45:32 -0700
Links: << >>  << T >>  << A >>
"Kevin Neilson" <kevin_neilson@removethistextcomcast.net> wrote in message news:<x7Q2b.268731$Ho3.35401@sccrnsc03>...
> In Verilog-2001, there is signed number support.  However, I'm not sure what
> any of it actually does.  You can declare registers as signed, but I don't
> know how they are treated differently.  You can assign a number a signed
> value, like 16'shFF, but I don't know how that is different that assigning
> 16'hFF.  

Signed numbers aren't about different bits in the variables, they are
about how those bits are treated.  Some operations in the language are
really two different operations: one that gets used on signed values,
and a different one that gets used on unsigned ones.

For example, consider division.  If you take a 4-bit value with all
1 bits and divide it by the number 3, you will get different results
depending on whether you do unsigned or signed division.  If you treat
these as unsigned values, you are dividing 15 by 3, and the result
should be 5.  If you treat them as signed values, you are dividing
-1 by 3, which is 0 with a discarded remainder of -1.

Most operations in the language are actually the same for signed and
unsigned operands.  That is why we use twos-complement representation,
because it means we can use the same hardware for signed and unsigned
operations.

Division is different, as noted above.  The >>> operator you mentioned
is different also.  It is an arithmetic shift in signed expressions, but
a logical shift in unsigned ones.  The most important operation is
probably the automatic width-extension of operands to the width of the
expression.  This is done with sign-extension in signed expressions
and zero-extension in unsigned ones.

For example, suppose you are building a multiplier that multiplies two
16-bit quantities together to produce a full 32-bit result.  What really
happens in Verilog is that both factors are extended to 32 bits, and
then multiplied together.  If the factors are sign-extended, then this
is effectively a signed multiply.  If they are zero-extended, then it
is effectively an unsigned multiply.

The signedness of the operands (such as regs and constants), is used
to determine whether the expression is signed or unsigned.  Generally,
if all of the operands are signed, then the expression is signed and
the operations are done signed.  If any of them are unsigned, then
the expression is unsigned, and all operations are done unsigned.
 
>I don't think it's possible, even with the new features, to assign
> negative numbers to a register, like A <= -16'shAB.

Sure it is.  But the value -16'shAB has the same bit pattern as the
value 16'hFF55 in twos-complement notation.  There is no difference
in those two values stored in a 16-bit register.  However, if A were
a 20-bit register, there is a difference in the values that would end
up being assigned.  The signed value -16'shAB would get sign-extended
to 20 bits, so A would end up with the bit pattern 20'hFFF55.  But if
you assigned A the unsigned value 16'hFF55, it would get zero-extended
to 20 bits, so A would end up with the bit pattern 20'h0FF55 instead.
 
> There are also the $signed and $unsigned functions, but I can't see that
> they work.

They aren't supposed to change the bits of the value.  They change whether
the value is to be treated as signed or unsigned by the expression.  They
are of limited use for that though.  Unless you make sure that all of the
values in an expression are signed, the expression ends up unsigned anyway.

Article: 60479
Subject: Re: Spartan 3 ICAP primitive
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Mon, 15 Sep 2003 04:58:09 GMT
Links: << >>  << T >>  << A >>
ICAP, or the Internal Configuration Access Port, is not supported in
Spartan-3 FPGAs.  Glimpses of the ICAP interface appear in various tools,
either because it was too difficult to remove this function from the
software, or the software mistakenly assumed that Spartan-3 had ICAP.

Dynamic reconfiguration is still supported in Spartan-3 via the external
SelectMAP interface or JTAG, just not through the ICAP interface.  The
decision to remove it was due to silicon resource requirements and testing
cost.  Although dynamic reconfiguration is a powerful concept, few
consumer-oriented applications use it.

The following is some background on partial reconfiguration in Spartan-3 and
the ICAP primitive.

Does Spartan-3 Support Partial Reconfiguration?

Virtex/E, Virtex-II, and Virtex-II Pro devices - generically called Virtex
throughout this article - support a feature called partial reconfiguration.
Using this feature, an application can modify a portion of the bitstream
programming inside an FPGA to change the FPGA's functionality. Spartan-3
FPGAs support some of these same capabilities, but with limitations compared
to Virtex.

Via today's design software, partial bitstream changes must be performed on
an entire IOB, CLB, or Block RAM column basis in both Virtex and Spartan-3
FPGAs. For example, to change a single bit within a single LUT, the
application must update all the CLBs in the affected column. Any unmodified
CLBs within the column are overwritten with the same configuration data.

Perhaps the most important difference between Virtex and Spartan-3 FPGAs is
how the FPGA logic behaves during the reconfiguration process. In the Virtex
devices, any unmodified bits in the affected column continue to operate
normally. Consequently, if bits within a column are unchanged, then the
surrounding logic continues to function normally. In Spartan-3 FPGAs,
however, even unmodified bits in a column are temporarily reset during the
reconfiguration process, which greatly complicates using partial
reconfiguration. Partial reconfiguration works in Spartan-3 FPGAs, just with
extra complications.

A column consists of multiple configuration frames. Physically, the Virtex
hardware supports configuration changes at the frame level, but software
currently just supports changes at the column level. The Spartan-3 hardware
supports bitstream changes at the column level only.

The application can partially reconfigure the FPGA via a variety of means,
including the parallel SelectMap configuration interface and the FPGA's JTAG
port. Virtex-II and Virtex-II Pro families also support another means called
the ICAP (Internal Configuration Access Port). The ICAP interface is similar
to the parallel SelectMAP interface, but is available from within the FPGA.
Although the Spartan-3 architecture is based on the Virtex-II and Virtex-II
Pro architectures, the Spartan-3 family does not support the ICAP interface.

Table 1 summarizes how partial reconfiguration compares between families.

Table 1.  Partial Reconfiguration Support in Virtex-II vs. Spartan-3.


     Software supports...
     Virtex:  Column-based reconfiguration
     Spartan-3:  Column-based reconfiguration

     Hardware supports...
     Virtex:  Frame-based reconfiguration
     Spartan-3:  Column-based reconfiguration

     Unmodified logic remains active during reconfiguration?
     Virtex:  Yes
     Spartan-3:  No

     Reconfigure via SelectMAP?
     Virtex:  Yes
     Spartan-3:  Yes

     Reconfigure via JTAG?
     Virtex:  Yes
     Spartan-3:  Yes

     Reconfigure via ICAP?
     Virtex:  Virtex-II and Virtex-II Pro only
     Spartan-3:  No




For more information on partial reconfiguration, visit the following web
links:

Partial Reconfigurability Frequently Asked Questions
http://www.xilinx.com/ise/advanced/partial_reconf_faq.htm

XAPP151:  Virtex Series Configuration Architecture User Guide
http://support.xilinx.com/xapp/xapp151.pdf

XAPP290:  Two Flows for Partial Reconfiguration: Module Based or Small Bit
Manipulations

http://www.xilinx.com/xapp/xapp290.pdf

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC

"Antti Lukats" <antti@case2000.com> wrote in message
news:80a3aea5.0309131115.164ea0ee@posting.google.com...
> Xilinx what is correct in ISE 5.1 schematics editor the ICAP primitive
> doesnt show, but if looking at XDL output then ICAP primitive does
> exist ?!
>
> I was very disappointed to see that Spartan 3 doesnt have ICAP
> (i.e. self reconfig) but it seems it is there?
>
> antti





Article: 60480
Subject: Re: Spartan 3 ICAP primitive
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Mon, 15 Sep 2003 14:59:09 +1000
Links: << >>  << T >>  << A >>
Hi Rick,

rickman wrote:
> John Williams wrote:
> 
>>Hi Antti,
>>
>>Antti Lukats wrote:
>>
>>>Xilinx what is correct in ISE 5.1 schematics editor the ICAP primitive
>>>doesnt show, but if looking at XDL output then ICAP primitive does
>>>exist ?!
>>>
>>>I was very disappointed to see that Spartan 3 doesnt have ICAP
>>>(i.e. self reconfig) but it seems it is there?
>>
>>Spartan3 is basically a Virtex2, trimmed down in various ways.  The
>>internal logic is pretty much identical as far as I can gather (CLBs,
>>IOBs etc).
>>
>>So, physically there's probably an ICAP hiding in every Spartan3, it's
>>just hidden by the tools.  The philosophy seems to be that
>>self-reconfiguration is still an experimental/research concept, and as
>>such doesn't have a place in Spartan3, which Xilinx views and markets as
>>a commodity FPGA.
>>
>>Note also that Jbits now supports Virtex2, but don't hold your breath
>>waiting for Jbits for Spartan3 - the same thinking probably applies.
>>
>>Bitstream hacking could probably uncover the S3's ICAP - Virtex2 and
>>Spartan3 bitstreams will likely have much in common.
> 
> 
> Looks like I have not done my homework on this.  I had done some
> research on modular configuration which was what I required.  The
> Spartan lines seem to be supported for this although they don't yet list
> the Spartan3 chips.  But I was under the impression that partial
> configuration was the down load technique to support this in the
> devices.  I see that only Virtex and Virtex-II are supported by partial
> configuration.  This is not good.  

Don't panic! the S3 still supports partial reconfiguration - the ICAP 
primitive that Antti and I were talking about is a block that allows the 
partial reconfigruration to be controlled from within the device itself 
ie. self-reconfiguration.

All the Virtex's and S3 can be partially reconfigured from *outside* the 
device, via SelectMap or slave serial or whatever, either partial or 
total reconfiguration.


> So why the disconnect on partial configuration Xilinx?  Why not support
> Spartan-3 devices?  

As I said, it's just the ICAP (internal configuration access port), not 
the partial reconfig capability itself.

Regards,

John

> 


-- 
Dr John Williams, Research Fellow,
Reconfigurable Computing, School of ITEE
University of Queensland, Brisbane, Australia
Ph : (07) 3365 8305


Article: 60481
Subject: Re: DCM not locking in XC2V4000
From: "Arthur Sharp" <arthur@nospam.com>
Date: Mon, 15 Sep 2003 15:30:43 +1000
Links: << >>  << T >>  << A >>
> Hi
> Look at signal connected to feedback in DCM.
> Try to connect output signal from DCM (that You use for feedback) to
> ordinary BUF and then to feedback input (CLKFB). Maybe feedback needs
little
> delay?

Who knows, I tried your suggestion and unfortunately it didn't work.

> Best regards
>
> Jerzy Gbur

Thanks,

Enzo



Article: 60482
Subject: Re: Altera's Quartus II "smart compilation" feature killed my design?
From: vbetz@altera.com (Vaughn Betz)
Date: 14 Sep 2003 22:31:00 -0700
Links: << >>  << T >>  << A >>
enq_semi@yahoo.com (enq_semi) wrote in message news:<cd4a30b8.0309110632.7ee5a488@posting.google.com>...
> Hi, there,
> 
> I have a design contains 12K logic cells and 300K bit memories and
> runs at 5MHz. I compiled it for an EP20K1500 device and it worked
> (tested on FPGA).
> 
> Then I wanted to switch 8 output bits from pin location AF1, AF2, AF3,
> AF4, G4, G5, G6 and H2 to DAC0 pins (AE1, AD1 -- AD6 and AC6).
> 
> I had the smart compilation option turned on when I successfully
> compiled and tested the design. So when I move 8-bit signals to new
> pin locations it should be as easy as a few top-level re-wiring. No
> need to recompile and re-fit the design.
> 
> However, the tool spent one hour re-do the whole synthesis and
> fitting. Worst of all, the compiled the design does NOT work on FPGA
> at all!
> 
> When I say "does NOT work at all", it means not only I cannot get
> anything from the DAC0 pins, but also I cannot bootload the FPGA (I
> have bootloader in the design) after I download the new design.
> 
> Somehow during the re-compilation, the bootloader (8051 processor,
> intruction ROM and RAM) are affected, which should have nothing to do
> with the 8 wires I changed at the top level.
> 
> Any help/suggestions are greatly appreciated.
> 
> Yi Zhang
> ENQ Semi.

Hi Yi,

There seem to be two issues here.  First, you're wondering why it
takes so long for smart recompile to occur after you move some pins.

The smart recompile feature in Quartus skips only entire steps in the
compilation process that aren't needed.  So if you move pins, it knows
that your design does not need to be re-synthesized & mapped, but it
does need to be re-placed and routed (fit).  So you still wind up
paying the CPU time for a full place and route, even though you moved
only a few pins.

To speed things up, you can back-annotate your design to LABs before
you recompile.  Back-annotate, move the pins you want to move, and
recompile.  It will now be a lot faster, since your logic is locked
down, so placement is trivial.  It will still need to be routed and
timing analyzed though, but it should still be 3x or so faster to
compile.

Our most recent families (Stratix and Cyclone) have two other features
that help speed up recompiles like this -- incremental fitting, and
back-annotated routing.  Unfortunately they won't help you with an
APEX design.

Incremental fitting does what I think you want here -- just figure out
what changed in the design, and make only the changes needed to
re-place and route those changes.

An alternative (again only for Stratix & Cyclone) is back-annotated
routing.  This lets you back-annotate your design, including routing,
move the pins you want, and recompile.  Now the placement is trivial,
and most of the routing is re-used too, so the compile time is much
faster.

Now for your second issue:  why did your design not work after a smart
recompile?  I can think of two possibilities:

1.  There is some dangerous timing in your design (race conditions,
asynchronous transfers without handshaking, transfers between clock
domains without timing constraints, etc.).  By re-placing and routing
your design, a race condition that was latent may have become a
problem.

2.  Something strange happened in the smart recompile.  As another
poster suggested, try deleting the db/ subdirectory before
recompiling.  This will force a full recompile with no information
re-use.  If that fixes your problem, I'd be interested to hear the
details so I can open a bug report on this.

Hope this helps.

Vaughn
Altera

Article: 60483
Subject: What CPU for Quartus II?
From: H. Peter Anvin <hpa@zytor.com>
Date: 14 Sep 2003 23:05:18 -0700
Links: << >>  << T >>  << A >>
Hi all,

I wonder if anyone has benchmarked contemporary high-end desktop
processors -- Athlon, Opteron and P4/Xeon basically -- for which is
better to do Quartus II synthesis?

	-hpa

-- 
<hpa@transmeta.com> at work, <hpa@zytor.com> in private!
If you send me mail in HTML format I will assume it's spam.
"Unix gives you enough rope to shoot yourself in the foot."
Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64

Article: 60484
Subject: Re: need help with Xilinx ISE 4.2i software
From: "Neeraj Varma" <neeraj@cg-coreel.com>
Date: Mon, 15 Sep 2003 11:50:37 +0530
Links: << >>  << T >>  << A >>
FPGA express is obsolete (Xilinx removed it and Synopsys also does not have
it)...and I doubt there is anything anyone could do to setup the license
again (I may be wrong though...)

If you are using any of the devices supported by the Xilinx Webpack (All
CPLDs, All Spartan-II, All Spartan-IIe except 400e and 600e, XCV50E-XCV300E,
XC2V40-XC2V250, XC2VP2, 3S50, 3S200, 3S400) you can use the XST tool for
synthesis. Webpack can be downloaded free from downloads page of
support.xilinx.com

--Neeraj

ps- spartan-3 support will be available in webpack in 6.1i release scheduled
to be available end of sep...






"Jon Elson" <elson@pico-systems.com> wrote in message
news:3F62B97D.5010903@pico-systems.com...
> Hello, all, I hope someone can help,
>
> I used to have my Xilinx Foundation/ISE up to date, but
> I let the support lapse, as all the new work seemed to be aimed at
> devices I was not going to use in the forseeable future.
>
> I had Foundation running on an older Win 95 system, and
> just stored the upgrade boxes.  I got A win 2000 system set up,
> installed ISE 4.2i, got my licenses for ISE and Foundation from
> Xilinx, and everything seemed to be working.  Now, I'm trying
> to seriously learn VHDL, and so I need to get FPGA Express
> working.  This used a different license scheme, as it was licensed
> from Synopsys.  I can't figure out how to get a license file from
> Xilinx, or convert my old license, or whatever it takes.  I have
> an old license from the Win 95 Foundation, but of course the
> disk serial numbers are different.
>
> Does anyone have any suggestions on how to make this work?
> I really can't expect Xilinx to help, as I dropped my support
> contract.
>
> Thanks very much in advance,
>
> Jon
>



Article: 60485
Subject: About two open source 32bit MCU
From: "John Smith" <305liuzg@163.net>
Date: Mon, 15 Sep 2003 16:01:20 +0800
Links: << >>  << T >>  << A >>
Hi all£º
Please give some comment on the following MCU I found on internet:

1.OpenRisc1000 @ www.opencores.org
2.LEON2   @ www.gaisler.com
or any other open source MCU

I want to make a development board to verify the MCU.
Which open MCU is better with better performance,gates,easy to use?

Thanks an Regards



Article: 60486
Subject: Re: Webpack Vs. ISE
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Mon, 15 Sep 2003 10:12:53 +0100
Links: << >>  << T >>  << A >>
Clyde R. Shappee <clydes@the_world.com> wrote in message
news:3F64ABE0.783CE26F@the_world.com...
> I just did  a little experiment with the webpack software, instantiating a
> fifo in the block ram.... and the software black boxes it because it
doesn't
> know how to hook it up.
> The .edn file from the core generator  is missing, and as such XST does
not
> know how to configure the block ram.
> This is consistent with information I received from the Xilinx Apps guy.
> Clyde

What are you trying to instantiate? If it's a component that you
previously generated from Coregen then it won't work as coregen
stitches whatever Blockrams together to get the structure you
need, creates a wrapper round them and gives it a sensible name.

If you try to instantiate the wrapper web-pack won't know what you're
talking about.

Have a look at the data sheet for whatever device you're targeting to
see what the blockrams should be called. As an example a 256* 8 bit dual
port
ram in SpartanIIE is RAMB4_S8_S8, you'll have to check the data sheet for
port names.

If you want bigger/wider structures than you get with one block ram you've
got to stitch them together yourself (with a wrapper if you want).


It would be almost a complete waste of time for Xilinx to release web-pack
if you couldn't access blockrams.


Nial.

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk







Article: 60487
Subject: Re: Spartan 3 ICAP primitive
From: antti@case2000.com (Antti Lukats)
Date: 15 Sep 2003 02:16:59 -0700
Links: << >>  << T >>  << A >>
"Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com> wrote in message news:<XFb9b.2983$n22.624510994@twister1.starband.net>...
> ICAP, or the Internal Configuration Access Port, is not supported in
> Spartan-3 FPGAs.  Glimpses of the ICAP interface appear in various tools,
> either because it was too difficult to remove this function from the
> software, or the software mistakenly assumed that Spartan-3 had ICAP.

Hi Steven,

I was not referring to tools! Tools dont show S3 ICAP!
ICAP as primitive is visible when doing -report query with XDL e.g.

XDL -report 3s200

	(tile 29 29 BR LR 9
		(primitive_site RLL_X23Y0 RESERVED_LL internal 8 6)
		(primitive_site DCI3 DCI internal 13 -1)
		(primitive_site DCI4 DCI internal 13 -1)
		(primitive_site DCIRESET3 DCIRESET internal 1 -1)
		(primitive_site DCIRESET4 DCIRESET internal 1 -1)
		(primitive_site STARTUP STARTUP internal 3 -1)
		(primitive_site ICAP ICAP internal 20 -1)
		(primitive_site CAPTURE CAPTURE internal 2 -1)
		(primitive_site VCC_X24Y0 VCC internal 1 -1)
	)

this is report from Xilinx S3 database, so I assume tools have to
use it when doing doing placement, routing and bitgen.

if the ICAP actually isnt there then xilinx S3 databases are wrong
not the tools.

anyway its real sad news that S3 doesnt support ICAP. 
It meanst that NO XILINX FGPA in NON-BGA support ICAP. 
this means that NO XILINX FPGA (in NON-BGA) can compete 
with Atmel Cachelogic device AT40, AT94K (self reconfig).

if there have been no real world applications for self reconfig then
well that doesnt mean that they would not come. It doesnt mean that
they would make much sense on Spartan 3 - larger S3 have actually
more resources than V2 - so partial reconfig and self reconfig would
make sense.

for me this is sad news.

I am planning a small litte thing an Pascal-Programmable FPGA 
it executes the original (modified version from N. Wirth's) 
Pascal-S pseudocode directly (most single cycle). The idea was
to put the Pascal-S engine on one side, and let the other part
of FPGA to be user configurable (from Pascal program). If S3
doesnt have ICAP, I can still achieve the goal by inserting
an array of MPGA (Meta FPGA) cells as user FPGA, but allows
way less resources to be used. Sure it using MPGA would allow
full toolchain without using any xilinx software or tools.

a web-based (SVG + javascript) MPGA - Editor is already work in progress
http://www.graphord.com/proj/ChipDesigner/mpga.html
(project to be moved to www.openchip.org soon)
its only local interconnect view and no editor bounded yet.

antti

Article: 60488
Subject: Spartan-3 : preconfiguration pull-up/float ?
From: Amontec Team <laurent.gauch@www.DELALLCAPSamontec.com>
Date: Mon, 15 Sep 2003 11:23:44 +0200
Links: << >>  << T >>  << A >>
Hi,

For the Spartan-II, the preconfiguration pullup resistors were selected 
by the M2 configuration pin. What about for the Spartan-3?

My new design has to connect an ARM7TDMI bus to the SPARTAN-3. I need to 
make sure my ucLinux will boot correctly, and so make sure about the IO 
pins states of the SPARTAN-3 on the poweron.

Regards,
Laurent


Article: 60489
Subject: Re: Power on problems
From: etraq@yahoo.fr (etrac)
Date: 15 Sep 2003 03:15:40 -0700
Links: << >>  << T >>  << A >>
At poweron I think the FPGA is not programmed ! It is in boundary scan
mode (pins M0-M1-M2), but I can't access to it with JTAG because the
voltage isn't sufficient. So I'm sure the FPGA is free !

There are some other components on the board, such as DSPs, they have
independant power supplys, but they are connected on some FPGA IOs. Do
you think they can disturb the FPGA at poweron ? My meaning was that
the FPGA IOs were tristated at poweron, nevertheless could they be
active when core or IO voltage are not yet stabilized ?

etrac

Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F5F3C37.9758AF5F@xilinx.com>...
> etrac,
> 
> Sounds broken.
> 
> Virtex II and II Pro have no power on current surges whatsoever.
> 
> Are you sure that you are not programming it to do something?  Like all
> IOs are DCI  HSTL input terminations (~54 mW each IO, 17 mA)?  One hundred
> of these IOs programmed this way makes ~ 1.7 amperes, and 5.4 watts.
> 
> The delay one one second is billions of times faster than the logic works,
> so it is unlikely it is the part doing something, it is more likely
> programming has just completed.....
> 
> Open a hotline case.
> 
> Austin
> 
> etrac wrote:
> 
> > We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
> > seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
> > are asking too much current (> 1.5A) for a long time. This occurs
> > approximatively 1 second after the power is on.
> > We have a current limitation power supply, so the VccAux/VccO voltage
> > fall at nearly 1.5V, that is to say that the FPGA needs very much than
> > 1.5A ..
> >
> > Does anybody ever had this kind of issue ? Or do you know a possible
> > cause of this event ?

Article: 60490
Subject: Xilinx Timing Constraints for Asynchronous Logic (asynch latches)
From: Andy.Nisbet@cs.tcd.ie (Dr. Andy Nisbet)
Date: 15 Sep 2003 05:07:04 -0700
Links: << >>  << T >>  << A >>
Hello,
I'm trying to implement an ISE 5.2.03i XST verilog dual-rail adder
core (generated from Balsa) on an XCV2000E-bg560-6 that is included in
an EDIF (generated by HandelC) design flow. A post-translate
simulation of the core indicates successful reset and valid then empty
inputs are applied. However, evil red lines/Xs occur waiting for
indication that the add has completed.

Behavioural simulation of the core, and behavoural cosimulation of
handelc+core are fine

The core is delay insensitive, but I must still (obviously) meet setup
and hold constraints. Could anyone point me to an example/tutorial or
give me instructions on how to apply xilinx timing constraints when
dealing with LD and LDC latches driven by asynchronous signals.

Sorry if this is a stupid question, I did try to find this on the
support site and RTFMed but there was no clear answer.

Cheers,
       Andy

Article: 60491
Subject: Re: DCM not locking in XC2V4000
From: Jerzy Gbur <furia@valhalla.bofh.pl>
Date: Mon, 15 Sep 2003 12:25:23 +0000 (UTC)
Links: << >>  << T >>  << A >>
Arthur Sharp <arthur@nospam.com> wrote:
>> Hi
>> Look at signal connected to feedback in DCM.
>> Try to connect output signal from DCM (that You use for feedback) to
>> ordinary BUF and then to feedback input (CLKFB). Maybe feedback needs
> little
>> delay?
> 
> Who knows, I tried your suggestion and unfortunately it didn't work.

I had similar problem with DLL so from here was that advice, nothing else I
can say, maybe this is stupid mistake with signal names or something like
that. I'm afraid I can't help more :(

Regards
furia

-- 
"Everything is simple until it'll be comprehensible" - furia

Article: 60492
Subject: Re: Downloading into XCV600 FPGA using PCI
From: fpga_uk@yahoo.co.uk (Isaac)
Date: 15 Sep 2003 05:48:07 -0700
Links: << >>  << T >>  << A >>
HI there ,
> 
> I have written program in a way that I have logic which is being
> already download in to FPGA( PCI ). In my C code I am using API
> function to write to FPGA and then on the same bus but using different
> Address I am reading the values out of FPGA. What I have in my C code
> that I have used Sleep()command make pause then to execite the next
> statement which is read fucntion.  But If I change time in sleep
> command than I am getting different values.
> It means that inside the FPGA in evertying clock cycle the value the
> signal which I am reading is changing all the time. Also in my VHDL
> code I haven't got anything which makes the values to change as time
> passes. And also according to the simulation I have a stable output as
> well.
> Could any body tell me how to do this properly to get stable output or
> if some one has done this before then please give me some hint to sort
> out this prob.
> 
> Cheers 
> 
> 
> Isaac

Article: 60493
Subject: Re: Xilinx S3 I/O robustness question
From: lecroy7200@chek.com (lecroy)
Date: 15 Sep 2003 06:24:35 -0700
Links: << >>  << T >>  << A >>
Peter Alfke <peter@xilinx.com> wrote in message news:<3F62569A.BB3294B0@xilinx.com>...

What happens at 25 ohms??


> My answer would be: NO.
> But I have copied Steve Knapp,
> who handles Spartan applications. He may add his opinion to this.

This is what I have been running into.  There seems to be no one at
Xilinx who is sure. I had hoped that with this news group being a bit
more visable that I could find the right person to ask.  Here is David
Anderson&#8217;s and Paul&#8217;s (who both work for Xilinx) responses
which are different from yours.  In Paul's note, he even talks about
asking the factory.



*****************************************

So yes the reflected energy can still cause damage, but again if you
limit
the current to 10mA there shouldn't be any damage.  This will be the
same
limitations as if this was an input.  So you can refer to the max
specs
in the first page of the datasheet.  See link below: 
http://direct.xilinx.com/bvdocs/publications/ds099-3.pdf
Mainly you need to take a look at Vin and note 4. When VCCO is 3.0 V
or
less, VIN overshoot may go as high as VCCO + 1.0 V for up to 11 ns
provided
that the current entering the I/O pin is limited to 10 mA. Also, when
VCCO
is 3.0 V or less, VIN undershoot may go as low as -1.0 V for up to 11
ns
provided that the current entering the I/O pin is limited to 10 mA.

Hope this helps.

Regards,
David Anderson

*****************************************


Going back to your original question, the answer back from the factory
is at
3.3 V signaling, it is possible to have reflections damage the part.
If you have a particular circuit that you would like to model for you
we can
do that.

In general,  IBIS simulation is the way to go in, to insure signal
integrity
(especially for high speed designs).  It should be possible to use the
XCITE
technology to use a few resistors to impedance match the board layout,
assuming that most trace lengths are about the same.  Should a few
signals be
much longer/shorter, XCITE or DCI can be disabled on an IO by IO
basis, and
these pins can then be terminated separately, if necessary (do IBIS
simulation to see if overshoot will be a problem).

Hope this helps,
Paul

*****************************************


I know we have gone back and forth on this, but I think the answer is
that
there is not an issue.  The from what I have seen, the IO on the
Spartan III
are speced the same as the Virtex II Pro, regarding maximum voltage,
and
reflections are not an issue with Virtex II Pro.

Brain,

Please correct me if I am wrong.  Again, I believe the initial
response was
wrong, and that reflections cannot damage the IO.  Also, what data can
we
provide that backs our position.

Thanks,
Paul

Article: 60494
Subject: Re: What CPU for Quartus II?
From: "Ken Land" <kland1@neuralog1.com>
Date: Mon, 15 Sep 2003 08:32:39 -0500
Links: << >>  << T >>  << A >>
Hi Peter,

I haven't formally benchmarked it, but for my Nios compiles with take about
80% of the memory and 50% of the LE's of the big Cyclone (so about 10k) the
P4's seem to do well.

What takes 25+ minutes on my 1GHz PIII takes less than 5 on my 3.2GHz P4 or
even a 2.4GHz.

One thing that seems true no matter the processor is the memory.  QII needs
lots of fast memory.  I only have 500MB in these machines and it could
clearly use more.

Ken

"H. Peter Anvin" <hpa@zytor.com> wrote in message
news:bk3kqu$mqi$1@cesium.transmeta.com...
> Hi all,
>
> I wonder if anyone has benchmarked contemporary high-end desktop
> processors -- Athlon, Opteron and P4/Xeon basically -- for which is
> better to do Quartus II synthesis?
>
> -hpa
>
> -- 
> <hpa@transmeta.com> at work, <hpa@zytor.com> in private!
> If you send me mail in HTML format I will assume it's spam.
> "Unix gives you enough rope to shoot yourself in the foot."
> Architectures needed: ia64 m68k mips64 ppc ppc64 s390 s390x sh v850 x86-64



Article: 60495
Subject: Re: Xilinx S3 I/O robustness question
From: lecroy7200@chek.com (lecroy)
Date: 15 Sep 2003 06:45:13 -0700
Links: << >>  << T >>  << A >>
hmurray@suespammers.org (Hal Murray) wrote in message news:<vm9n0if1mm4fda@corp.supernews.com>...
> 
> There is nothing special about Spartan or FPGAs in this area.  Right?

Well, let's see if they can answer this. My fear was that they boasted
about their lastest 90nm technology and then turned around and made a
comment about how sensitive it is to transients.
 
> Is there a general rule in output pad design that the pad must
> be rugged enough so that it can't shoot itself in the foot with
> its own reflections?  (I don't remember seeing any warnings about
> this in data sheets.)

 
> What about busses, like PCI, where the driver might be in the middle
> so the effective line impedance is half of the nominal 50 ohms.
> (Can it get even lower than that due to capicative loading?)

I agree, a very interesting question.

Article: 60496
Subject: USB transceiver for FPGA
From: "jakab tanko" <jtanko@ics-ltd.com>
Date: Mon, 15 Sep 2003 09:49:33 -0400
Links: << >>  << T >>  << A >>
Hi,

 I am looking for an USB transceiver chip that can be interfaced to an
FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok.
Any suggestions?

Thanks,
---
jakab



Article: 60497
Subject: Re: Xilinx S3 I/O robustness question
From: Magnus Homann <d0asta@mis.dtek.chalmers.se>
Date: 15 Sep 2003 16:06:43 +0200
Links: << >>  << T >>  << A >>
lecroy7200@chek.com (lecroy) writes:

> hmurray@suespammers.org (Hal Murray) wrote in message news:<vm9n0if1mm4fda@corp.supernews.com>...

> > What about busses, like PCI, where the driver might be in the middle
> > so the effective line impedance is half of the nominal 50 ohms.
> > (Can it get even lower than that due to capicative loading?)
> 
> I agree, a very interesting question.

PCI requires that the input withstands higher voltages during 11ns, if
I recall correctly.

Homann
-- 
Magnus Homann, M.Sc. CS & E
d0asta@dtek.chalmers.se

Article: 60498
Subject: Re: USB transceiver for FPGA
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Mon, 15 Sep 2003 15:25:56 +0100
Links: << >>  << T >>  << A >>
jakab tanko <jtanko@ics-ltd.com> wrote in message
news:bk4g4g$j0f$1@news.storm.ca...
> Hi,
>
>  I am looking for an USB transceiver chip that can be interfaced to an
> FPGA WITHOUT microcontroller. USB 2.0 would be ideal, 1.1 is also ok.
> Any suggestions?

The FTDI 245BM sounds like what you want (although it's only 1.1).

See..

http://www.ftdichip.com/

..for details.

I've a board based on this I built for my own use (see under
downloads on my web site). I've a couple sitting here that
someone said they wanted but money hasn't been forthcoming.

Yours for £30 each if you want one/both for prototyping.

See my downloads page for details of an example project showing
how to drive it, it's relatively easy.


Nial Stewart

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk




Article: 60499
Subject: Quartus internal synthesis more verbose?
From: remove_spam_rprager@frequentis.com
Date: Mon, 15 Sep 2003 15:49:36 GMT
Links: << >>  << T >>  << A >>
Hi

I am using Quartus internal synthesis (Quartus3.0). Is there a way to
switch it to a little bit more verbose output (i.e. there are nearly no
warnings if there are flaws in your code, like problematic type
conversions. I like the output of Leonardo much better

Roman



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