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Messages from 60300

Article: 60300
Subject: Re: VGA display
From: "Abby" <abhigayl@hotmail.com>
Date: Wed, 10 Sep 2003 09:29:27 GMT
Links: << >>  << T >>  << A >>

"Jean Nicolle" >

can I suggest taking a look to this tutorial?
> http://www.fpga4fun.com/PongGame.html
>
> Jean
>


Yeah, It's wonderful!!
Thx!!!
:-***




Article: 60301
Subject: Re: VGA display
From: "Abby" <abhigayl@hotmail.com>
Date: Wed, 10 Sep 2003 09:33:07 GMT
Links: << >>  << T >>  << A >>

"Jan Kindt"  ha scritto nel messaggio > You also might be interested in
following link :
> http://home.freeuk.com/fpgaarcade/pac_main.htm
>
> It has a very simple vga-interface implemented in VHDL. Might be
> enough to kickstart your design.

Thank you very much!
I don't know VHDL language, but I think this file will be very useful when I
will start to work with VHDL too!

Thanx to all!





Article: 60302
Subject: Re: Original (5V) Xilinx Spartan ?
From: oen_br@yahoo.com.br (Luiz Carlos)
Date: 10 Sep 2003 03:38:16 -0700
Links: << >>  << T >>  << A >>
Hi Peter,

> Sorry, Luiz. I can handle German, French, Italian and Scandinavian.

Amazing!

> But Spanish and Portuguese are not my forte...

What a pity!

> What is it you want to discuss?
> Peter

I just said that, if you want, we can recapitulate the metastability
stuff. During your absence we found the cure for metastability (Rick
designed the circuit), we built, tested and patented a perpetual
motion machine (Ray worked a lot here) and finally, we almost finished
a prototype of a Time Machine. We are preparing a Dinosaur Hunt, do
you want to join us?

Now, coming back to Earth.
You said (@ Thinking out loud about metastability): "I have never seen
strange levels or oscillations ( well, 25 years ago we had TTL
oscillations). Metastability just affects the delay on the Q output."
But Philip Freidin showed (@ Mitigating metastability) some pictures
of the FF output during metastability that disagree.
Do the Xilinx FFs have a different behavior?

One more question.
You also said (@Thinking out loud about metastability): "Remember:
Metastability causes an extra 3 ns of unpredictable delay once in a
billion years...  Seems to be an affordable risk.".
What kind of input? What clock frequency?

Luiz Carlos

Article: 60303
Subject: Crystal Input to FPGA
From: nagaraj_c_s@yahoo.com (Nagaraj)
Date: 10 Sep 2003 05:48:28 -0700
Links: << >>  << T >>  << A >>
Hi,
   I want to interface a crystal to a Xilinx FPGA. Earlier Xilinx FPGA
devices like XC2000 series had crystal input provision which is not
there in Spartan 30K gate device which I am using for my design.
   I want to know how to build an oscillator circuit (amplifier) for
the crystal in FPGA.
   Any references?

Regards,
Nagaraj

Article: 60304
Subject: Re: Original (5V) Xilinx Spartan ?
From: oen_br@yahoo.com.br (Luiz Carlos)
Date: 10 Sep 2003 06:01:10 -0700
Links: << >>  << T >>  << A >>
Peter,

Forget my last question, I saw your post at "opinions are OK".

Luiz Carlos

Article: 60305
Subject: Re: Crystal Input to FPGA
From: "Jonathan Bromley" <jonathan.bromley@doulos.com>
Date: Wed, 10 Sep 2003 14:16:48 +0100
Links: << >>  << T >>  << A >>

"Nagaraj" <nagaraj_c_s@yahoo.com> wrote in message
news:91710219.0309100448.6e8ab050@posting.google.com...

>    I want to interface a crystal to a Xilinx FPGA. Earlier Xilinx FPGA
> devices like XC2000 series had crystal input provision which is not
> there in Spartan 30K gate device which I am using for my design.
>    I want to know how to build an oscillator circuit (amplifier) for
> the crystal in FPGA.

Don't mess around.  Buy a packaged oscillator.  The price of the
oscillator is about three orders of magnitude lower than the value
of the headaches you will get from not using one.
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223                    mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573                           Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.




Article: 60306
Subject: Re: opinions are OK
From: oen_br@yahoo.com.br (Luiz Carlos)
Date: 10 Sep 2003 06:23:07 -0700
Links: << >>  << T >>  << A >>
Hi Austin,

I was just kidding with Peter. No ofense at all. I just said that, if
he wants, we can recapitulate all the metastability stuff, so he does
not need to be sad about not beeing here! See my other post.

As he come back from Portugal, I wrote in portuguese!

Luiz Carlos

Article: 60307
Subject: Re: Spartan-3 3S50 in Web ISE 5.2i = no block RAM, no multiplier?
From: "Steven K. Knapp" <steve.knappNO#SPAM@xilinx.com>
Date: Wed, 10 Sep 2003 07:30:15 -0700
Links: << >>  << T >>  << A >>
WebPack ISE 5.2i only supports the device called the XC3S50J (note the 'J'),
which has no block RAM or multipliers.

WebPack ISE 6.1i, due out at the end of September, supports the XC3S50 (no
'J'),  which has four 18Kbit block RAMs, four 18x18 hardware multipliers,
and two Digital Clock Managers (DCMs).  WebPack 6.1i also supports the next
few larger Spartan-3 devices, namely the XC3S200 and the XC3S400.

My apologies on the short-term confusion.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
Spartan-3/II/IIE FPGAs
http://www.xilinx.com/spartan3
---------------------------------
Spartan-3:  Make it Your ASIC

"Kirill 'Big K' Katsnelson" <kkm@dtmx.com> wrote in message
news:73163042.0000d078.086@drn.newsguy.com...
> I downloaded Xilinx free Web ISE 5.2i, and toying with different design to
get
> the feeling of this Spartan-3 thingy.  The only Spartan-3 device supposed
to be
> supported by the free verison is 3S50.  I am saying "supposed", because I
cannot
> make it instantiate neither multipliers nor block RAMs.  According to the
data
> sheet, there are enough of them in the device, but mapper thinks there are
none.
> Why is that?
>  - My error (so I hope!)
>  - Bug in ISE
>  - Limitation of the free version
>  - Typo in the datasheet, and there are no multipliers really.
>
> Code follows.  In this test (one of so many!) I let ISE infer a
multiplier:
>
> <<<
> module mult (input clk, input [7:0] x, input [7:0] y, output reg [15:0]
q);
>
> always @(posedge clk)
>   q <= { 8'h0, x } * { 8'h0, y };
>
> endmodule
> >>>
>
> Synthesizer infers one:
>
> <<<
> Synthesizing Unit <mult>.
>     Related source file is mult.v.
> WARNING:Xst:643 - Multiplier result width is 16 bits.
>     Found 16x16-bit registered multiplier for signal <$n0000> created at
line 4.
>     Summary:
> inferred   1 Multiplier(s).
> Unit <mult> synthesized.
>
>
> =========================================================================
> HDL Synthesis Report
>
> Macro Statistics
> # Multipliers                      : 1
>   16x16-bit registered multiplier  : 1
> >>>
>
> but then, in the final report, says *something* is overmapped.  Note it
does not
> mark overused resource with an asterisk like '(*)':
>
> <<<
> =========================================================================
> *                            Final Report                               *
> ----snip----
> # MULTs                            : 1
> #      MULT18X18S                  : 1
> =========================================================================
>
> Device utilization summary:
> ---------------------------
>
> Selected Device : 3s50pq208-4
>
>  Number of bonded IOBs:                 32  out of    124    25%
>  Number of GCLKs:                        1  out of      8    12%
>
> WARNING:Xst:1336 -  (*) More than 100% of Device resources are used
> >>>
>
> There supposed to be 4 of MULT18X18S in this part, but then maper fails
with a
> more detailed, but not more explainable diagnostics:
>
> <<<
> Design Summary
> ---snip--- 
>    Number of bonded IOBs:              33 out of     124   26%
>    Number of MULT18X18s:                1 out of       0    0%
(OVERMAPPED)
>    Number of GCLKs:                     1 out of       8   12%
> >>>
>
>  -kkm
>



Article: 60308
Subject: Power on problems
From: etraq@yahoo.fr (etrac)
Date: 10 Sep 2003 07:38:37 -0700
Links: << >>  << T >>  << A >>
We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
are asking too much current (> 1.5A) for a long time. This occurs
approximatively 1 second after the power is on.
We have a current limitation power supply, so the VccAux/VccO voltage
fall at nearly 1.5V, that is to say that the FPGA needs very much than
1.5A ..

Does anybody ever had this kind of issue ? Or do you know a possible
cause of this event ?

Article: 60309
Subject: simulating memory models in sopc builder
From: jwing23@hotmail.com (J-Wing)
Date: 10 Sep 2003 07:53:39 -0700
Links: << >>  << T >>  << A >>
what does including a file under simulation in build or file in the
simulation tab of a memory in sopc builder? its a megafunction to
build a nios processor.
pls advice.

Article: 60310
Subject: Embedded/Microcontroller FPGA and Software Defined Radio
From: tom1@launchbird.com (Tom Hawkins)
Date: 10 Sep 2003 07:56:48 -0700
Links: << >>  << T >>  << A >>
I need a single chip solution for a control system and DSP
application.
The primary consideration is board area.  The second, cost.
Here's what I'm looking for:
  - 5V supply and I/O.
  - Embedded ADC (at least 1, preferably 8).  Slow rate (50 Hz).
  - Small FPGA fabric.  About the size of a small spartan.
  - Embedded block ram (4 KBytes).
  - Flash FPGA.  Would like not to have separate config prom.
  - Low I/O count.  I only need about 30 pins.

Does anything like this exist?  If 5V I/O is not possible, what's
needed to translate about 12 pins from 3.3/1.2 to 5V?

Also, what's envolved for FPGA based software defined radio?  I'd like
to build an RC (as in radio control airplane) receiver.  Most FM
radios hop between 2 frequencies to encode pulse widths which in turn
drive the RC servos.  So nothing digital.  It just needs to extract
the pulse train from the FM.  I would consider trading an FM receiver
chip for an external high-speed ADC and a larger FPGA if it buys
enough flexibility.

Regards,
Tom

Article: 60311
Subject: Re: Xilinx clk to out variation
From: johnp3+nospam@probo.com (John Providenza)
Date: 10 Sep 2003 07:57:28 -0700
Links: << >>  << T >>  << A >>
I suspect you're seeing variations in the routing delay caused by
your internal clock having to 'jump' off its global clock lines
onto slower nets to get to the output IOB.  To avoid this, I use
a Xilinx DDR pad to drive my clock signals out of the chip.

Try something like:

// instantiate a DDR type I/O cell for low clock output skew
FDDRRSE uddr_clk(
        .Q              (sram_clk),
        .C0             (g_sr_clk),
        .C1             (~g_sr_clk),
        .CE             (1'b1),
        .D0             (1'b1),
        .D1             (1'b0),
        .R              (1'b0),
        .S              (1'b0)
);

This keeps the clock signal (g_sr_clk) on the dedicated clock lines thus
avoiding odd routing delays.

Good Luck!

John Providenza
Providenza & Boekelheide, Inc



alann@accom.com (Alan Nishioka) wrote in message news:<a2db9b48.0309091302.7a9d11bf@posting.google.com>...
> If I register all my signals in the IOB and use the global clock,
> why is the clock to out different on different outputs?
> Why does my clock to out vary from compile to compile?
> 
> clock to out ranges 4.664ns to 5.355ns
> Is this just skew in the global clock?
> Can it be controlled with constraints?
> 
> I am using Synplify 7.2, XST 5.2.03, Win2K SP4, XCV1000E-6FG860C
> 
> Alan Nishioka
> alann@accom.com

Article: 60312
Subject: Re: Power on problems
From: Austin Lesea <Austin.Lesea@xilinx.com>
Date: Wed, 10 Sep 2003 07:59:03 -0700
Links: << >>  << T >>  << A >>
etrac,

Sounds broken.

Virtex II and II Pro have no power on current surges whatsoever.

Are you sure that you are not programming it to do something?  Like all
IOs are DCI  HSTL input terminations (~54 mW each IO, 17 mA)?  One hundred
of these IOs programmed this way makes ~ 1.7 amperes, and 5.4 watts.

The delay one one second is billions of times faster than the logic works,
so it is unlikely it is the part doing something, it is more likely
programming has just completed.....

Open a hotline case.

Austin

etrac wrote:

> We want to power on a Virtex II xc2v3000 FPGA (Xilinx). The core power
> seems to work correctly (VccInt = 1.5V ; I<100mA), but VccAux and VccO
> are asking too much current (> 1.5A) for a long time. This occurs
> approximatively 1 second after the power is on.
> We have a current limitation power supply, so the VccAux/VccO voltage
> fall at nearly 1.5V, that is to say that the FPGA needs very much than
> 1.5A ..
>
> Does anybody ever had this kind of issue ? Or do you know a possible
> cause of this event ?


Article: 60313
Subject: DDR in EDK 3.2sp2...
From: "Terry Andersen" <terr@sea.com>
Date: Wed, 10 Sep 2003 18:01:42 +0200
Links: << >>  << T >>  << A >>
I have a MB1000 board from Insight, I use the reference design available
"VII_MicroBlaze_DDR_Reference_Design". It works ok, but as soon as I ad an
interrupt controller (opb_intc) and make the timer go thorugh the interrupt
controller and interrupt the Microblaze I cant read anything from the
DDR-RAM!!! The timer runs fine though.....All I read from the DDR_RAM is
zeros :-(
Anyone has an idea of what is wrong? Someone has tried similar?

Best Regards



Article: 60314
Subject: Re: Original (5V) Xilinx Spartan ?
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 10 Sep 2003 09:15:00 -0700
Links: << >>  << T >>  << A >>


Luiz Carlos wrote:

> You said (@ Thinking out loud about metastability): "I have never seen
> strange levels or oscillations ( well, 25 years ago we had TTL
> oscillations). Metastability just affects the delay on the Q output."
> But Philip Freidin showed (@ Mitigating metastability) some pictures
> of the FF output during metastability that disagree.
> Do the Xilinx FFs have a different behavior?

I have a lot of respect for Phil, we are personal friends and have
worked together for over 20 years. I think he used old TTL pictures.
> 
> One more question.
> You also said (@Thinking out loud about metastability): "Remember:
> Metastability causes an extra 3 ns of unpredictable delay once in a
> billion years...  Seems to be an affordable risk.".
> What kind of input? What clock frequency?

300 MHz clock, ~50 MHz data, Virtex-IIPro. See TechXclusive on the
Xilinx web.

Peter

Article: 60315
Subject: ABEL help needed
From: timoreinhardt@yahoo.com (Tim)
Date: 10 Sep 2003 09:15:23 -0700
Links: << >>  << T >>  << A >>
Hi there

I like to realize a counter, which has an UP and DOWN (and others).
I know, I need a clock for realizing asynchronious reset.
UP and DOWN are triggered by user switches. But I just found a
possiblity for realisation by using an extra Clock-Button - that's a
pretty bad solution!

Can somebody help me and tell me what to change in my ABEL-Code, so I
don't need the Clock-Button??

I use this code

MODULE unicnt


title '6 bit universal counter with parallel load' ;
	"constants
	X,C,Z = .X., .C., .Z. ;
	

	"inputs
	D5..D0 pin ; "Data inputs, 4 bits wide
	clk pin ; "Clock input
	rst pin ; "Asynchronous reset
	cnten pin ; "Count enable
	ld pin ; "Load counter with input data value
	up pin ; "Up/Down selector: HIGH selects up
	down pin;

	"outputs
	q5..q0 pin istype 'reg'; "Counter outputs

	"sets
	data = [D5..D0]; "Data set
	count = [q5..q0]; "Counter set
	
"mode equations
	MODE = [cnten,ld,up,down]; "Mode set composed of control pins.
	LOAD = (MODE == [ X , 1, X, X ]);"Various modes are defined by
	HOLD = (MODE == [ 0 , 0, X, X ]);"values applied to control pins.
	UP = (MODE ==   [ 1 , 0, 1, 0 ]);"Symbolic name may be defined as
	DOWN = (MODE == [ 1 , 0, 0, 1 ]);"a set equated to a value.

equations
	when LOAD then count := data "Load counter with data
	else when UP then count := count + 1 "Count up
	else when DOWN then count := count - 1 "Count down
	else when HOLD then count := count  "Hold count
	else count := count;
	
	count.clk = clk;
	 "Counter clock input
	count.ar = rst; "Counter reset input

END 


Thanks


Tim

Article: 60316
Subject: Re: Crystal Input to FPGA
From: Peter Alfke <peter@xilinx.com>
Date: Wed, 10 Sep 2003 09:24:51 -0700
Links: << >>  << T >>  << A >>
Don't do it!
In XC3000 we had a single-stage amplifier between two pins, and that
worked kind of ok with most crystals. But there were problems with very
low frequencies (like 32 kHz) and some overtone designs. We (i.e.I) got
dragged into many complicated analog discussions, so we never offered
such a circuit again. If you implement an inverter from one input pin to
an output pin, you actually have more than half a dozen stages cascaded
(that's the way we build our input and output buffers) and that is not a
healthy arrangement for a reliable oscillator that always starts and
never goes into spurious odcillations. It might work in the lab, but is
not good for production.
Buy a complete oscillator can. You can buy them retail for <$1, and they
always work and draw little power.

Peter Alfke, Xilinx Applications
====================
Nagaraj wrote:
> 
> Hi,
>    I want to interface a crystal to a Xilinx FPGA. Earlier Xilinx FPGA
> devices like XC2000 series had crystal input provision which is not
> there in Spartan 30K gate device which I am using for my design.
>    I want to know how to build an oscillator circuit (amplifier) for
> the crystal in FPGA.
>    Any references?
> 
> Regards,
> Nagaraj

Article: 60317
Subject: Re: pipelined divider
From: "Steve Casselman" <sc_nospam@vcc.com>
Date: Wed, 10 Sep 2003 16:31:11 GMT
Links: << >>  << T >>  << A >>
Look up online arithmetic.

Steve

>
> well my requirement is too for double precision .. would u like to
> suggest me a pipelined
> comp arch book for this purpose.. anyway what is the best way, that's
> what i want to explore first.
>
> Xilinx coregen divider core doesn't offer that much width in its
> pipelined divider .. don't know why
> may be xilinx gurus can justify .. anybody knows which algorithm they
> are using ?
>
> regards
> --yka



Article: 60318
Subject: Re: simulating memory models in sopc builder
From: "Nial Stewart" <nial@spamno.nialstewart.co.uk>
Date: Wed, 10 Sep 2003 18:13:25 +0100
Links: << >>  << T >>  << A >>
J-Wing <jwing23@hotmail.com> wrote in message
news:d6e7734d.0309100653.2fe98165@posting.google.com...
> what does including a file under simulation in build or file in the
> simulation tab of a memory in sopc builder? its a megafunction to
> build a nios processor.
> pls advice.

Off the top of my head, when you buld a NIOS module the SOPC
builder generates a model of it for you.

If you want this to do what your final device will do you
need the rams in your model to contain the code that'll be
in the final device.

Selecting a source file in the simulation tab causes it to
be compiled and the results placed in the memory contents in
your model.

Nial.

------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
www.nialstewartdevelopments.co.uk



Article: 60319
Subject: Re: CMOS camera w/ USB2 -- crazy?
From: james <buckanear7@yahoo.com>
Date: Wed, 10 Sep 2003 17:18:17 GMT
Links: << >>  << T >>  << A >>
On Tue, 9 Sep 2003 01:42:27 +0000 (UTC), Sander Vesik
<sander@haldjas.folklore.ee> wrote:

>john jakson <johnjakson@yahoo.com> wrote:
>> "GB" <donotspam_grantbt@jps.net> wrote in message news:<GFJ6b.2610$PE6.1782@newsread3.news.pas.earthlink.net>...
>>> "hamilton" <hamilton@deminsional.com> wrote in message
>>> news:3f5b561c_3@omega.dimensional.com...
>>> 
>>> > What image sensor chip are you looking at ???
>>> >
>>> 
>>> That's another undecided at this time, but CMOS most likely.
>>> 
>>> GB
>> 
>> Until recently I was under the impression that CMOS sensors were junk
>> and were of low resolution & quality typically 320.240 used in $0-50
>> cameras. I have an old Connectix webcam device thats is all green that
>> demonstrates that.
>
>I believe all present digtal cameras use CMOS. That includes monsters
>in the 16Mpixel range. 
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

"CMOS" sensors are usually 1 megapixel or less and have most of the
timing generation integrated on board. They are less flexible than CCD
imagers which are CMOS technology.  

james


Article: 60320
(removed)


Article: 60321
Subject: LVDS in cyclone
From: "Eduard Nikke" <ednikke@hotmail.com>
Date: Wed, 10 Sep 2003 18:00:18 GMT
Links: << >>  << T >>  << A >>
Hi,

Can someone help me with this issue.

I am looking to build a serialer in a FPGA.
Base frequence is 72MHz - 7 bits serialiser - so I need a LVDS frequence of
504MBps.

I thought this wat not possible in a Cyclone device but just reads the app.
note and it seems to be possible.

I have only some strong concerns because there is no timing budget and the
IOB are not DDR IOB blocks.

Does any one has experience with this app. note ?

Thanks,

Eduard



Article: 60322
Subject: Re: CMOS camera w/ USB2 -- crazy?
From: james <buckanear7@yahoo.com>
Date: Wed, 10 Sep 2003 18:02:55 GMT
Links: << >>  << T >>  << A >>
On Sun, 07 Sep 2003 15:03:39 GMT, "GB" <donotspam_grantbt@jps.net>
wrote:

>Hi,
>
>I'm a firmware guy pulled into a project well out of my area of
>expertise.  My boss wants to build (essentially) a digital camera
>using an image sensor chip (1600x1200) and output it's data
>"as fast as possible" using USB2.0.  His initial concept, being
>that I'm a firmware guy, was to use a "really fast micro."
>Normally the company is involved with small 8-bitter micro
>projects, so you can see I'm well out of my normal bounds.
>
>Now this seems like a pretty big stretch to me... and I don't see
>how it can be done without the speed of hardware (the image
>chips all seem to have clock speeds in the tens of MHz and the
>USB2 transfer rate is 480Mbps (theor.).  Do aspects of this
>project require an FPGA to keep the data "as fast as possible?"
>If we use and FPGA for camera-to-RAM and then use a
> micro for the USB2 part, what kind of fast micros can
>move data at that rate?
>
>Also, this is something that I am sure we will have to contract
>out, so if you have any past experience with this, please let
>me know your thoughts (and if you are available).
>
>Thanks!
>
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
1600x 1200 is essentially a 2 megapixel camera!

1) First step is to determine what the camera is going to be used for!

Terrestial or astronomical or video photography  

2) Pick an imager! Either Sony, TI, Kodak, or Panasonic to name a few.

3) From the Imager specs you can derive how fast the data can be
clocked out of the imager. Most imagers will transfer the image area
into a serial register one line at a time. How fast this is depends on
how fast you can clock the serial register. Transfer speeds differ
from vendor to vendor. 

4) Then build the circuitry around the imager based on its ability to
transfer the full image as fast as you want and that meet your cost
goals.  

Again depending on what you determine as reasonably fast will effect
the cost of the imager along with its size. Another consideration will
be the speed of the ADC. That can slow things down also. Even if you
can clock the serial register of the imager out at 20Mhz rate, if the
ADC sasmple rate is 10 MHz  that is as fast as you can get the pixel
data out. 

IF your imager's max clock frequency for the serial register is 20
MHz., you can clock a 1600 pixel row out in about 80 uS. Or the whole
image area out of the chip in about 100 mS.  So your microC or FPGA
will have to read the ADC once every 50 nS or so during the readout
period. 

There are some CPU cores as well as USB cores that can drop into an
FPGA. You can build a large FIFO or add onboard flash to store the
picture. 

It is not crazy at all in fact it is quite doable. The two key items
in a digital camera is the imager and the ADC. All the rest is digital
hardware that is well suited for an ASIC or FPGA.  


james


Article: 60323
Subject: Silicore adopts open source business model for semiconductor IP; releases SLC1657 uP core under LGPL license
From: "Wade D. Peterson" <wadep@silicore.net>
Date: Wed, 10 Sep 2003 18:22:17 GMT
Links: << >>  << T >>  << A >>
*** Press Release / For Immediate Release: Silicore Adopts Open Source
Business Model for Semiconductor IP; Releases SLC1657 uP Core Under LPGL ***

   September 9, 2003 - Minneapolis, MN - USA. Silicore Corporation announced
today the adoption of an open source business model for semiconductor IP.
According to Wade Peterson, Silicore President and CEO: "We have been
studying the semiconductor market for some time now, and have concluded that
the best way to create and distribute soft IP is under an open source
business model. It's the same model that's used by Red Hat and other
GNU/Linux distributors. Until now we've operated under a traditional
software business model that's been used by companies like Microsoft and
Oracle. Under that approach we viewed IP as a product, but now we see it as
a service. We believe that System-on-Chip [SoC] integrators will prefer this
model because it lowers costs, simplifies licensing, reduces parts
obsolescence, improves security and allows them more control over their
system level IP."

   In a related move, Silicore released its SLC1657 microcontroller core
under the GNU Lesser General Public License (LPGL). VHDL source code and
documentation are now available on the Silicore website. Originally released
in 1998, the SLC1657 is a complete 8-bit RISC processor solution for use on
FPGA or ASIC devices. Typical applications include sensors, medical devices
and consumer electronics.

<End of snippit>


To see the entire press release, go to: http://www.silicore.net/pr090903.htm




Article: 60324
Subject: Re: Embedded/Microcontroller FPGA and Software Defined Radio
From: antti@case2000.com (Antti Lukats)
Date: 10 Sep 2003 11:30:15 -0700
Links: << >>  << T >>  << A >>
tom1@launchbird.com (Tom Hawkins) wrote in message 
> I need a single chip solution for a control system and DSP
> application.

if you need true single chip solution it would only be possible
using full custom ASIC, this is out of the question.

> The primary consideration is board area.  The second, cost.
> Here's what I'm looking for:
>   - 5V supply and I/O.

most semicon industry people say there is no 5V any more.
even 5V tolerant device are vanshing

>   - Embedded ADC (at least 1, preferably 8).  Slow rate (50 Hz).

there is no FPGA with ADC (no real large FPGA at least)

>   - Small FPGA fabric.  About the size of a small spartan.

small like XC2S15?

>   - Embedded block ram (4 KBytes).

most FPGAs have that amount

>   - Flash FPGA.  Would like not to have separate config prom.

there is only 2 Flash (or instant on) FPGAs
1) lattice xPGA (only in large BGA pacakge)
2) Actel ProAsic+

>   - Low I/O count.  I only need about 30 pins.

APA075, 100pin TQFP, 17EUR single qty, (price from mcs-ge.com)
 
> Does anything like this exist?  If 5V I/O is not possible, what's
> needed to translate about 12 pins from 3.3/1.2 to 5V?

inputs series resistor
outputs direct connection
(in most cases)
 
> Also, what's envolved for FPGA based software defined radio?  I'd like
> to build an RC (as in radio control airplane) receiver.  Most FM
> radios hop between 2 frequencies to encode pulse widths which in turn
> drive the RC servos.  So nothing digital.  It just needs to extract
> the pulse train from the FM.  I would consider trading an FM receiver
> chip for an external high-speed ADC and a larger FPGA if it buys
> enough flexibility.
> 
> Regards,
> Tom

I hope Ray Andraka will reply on SDR side.

I have build model airplanes and I have build radio tranceivers and
transmitters. so the topic is kind interesting.

I guess you also need low power, right?

if you need low power then use TI MSP430 those are microcontrollers
that run out of wires plugged into an apple - no joke there was a demo
of webserver powered by an apple. Whatever you do with FPGA you need more
power.

you wanted single chip solution, this would be really hard!
www.cypressmicro.com advertises their products as Programmable SOC
well its RISC micro with configurable logic and analog blocks, but
the logic blocks are not PLD or FPGA unfortunatly.

you come to 3 chips so or so
1) radio front end
2) MCU or FPGA+config (or MCU holding FPGA config)

no way around it. very small micro could be run from internal memory
of ProAsic, then you could have, no still 3 chips, you need ADC


so use the radio chip
select some low power MCU (with ADC)
select some FPGA (possible loaded by the MCU)

antti



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