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David, asyncronous counters generate glitches, not syncronous ones. Use a syncronous design. You don't need to waste resources, use the output flip-flop of the pin. Luiz Carlos. "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:<bi2m0c$ig1$1@home.itg.ti.com>... > Ok sounds like I should use the flip flops. I don't care about the delay, > since this clock is for other part of the circuit (outside the fpga) that > are not synchronized with anything else. However, I have always been told to > never use the output of a counter as a clock since it can glitch. This is > almost what I'm about to do... > Is there a way to avoid glitches? > Thanks > David >Article: 59551
Jonathan Bromley wrote:
> One solution, I humbly suggest, is for practitioners and educators
> to swap places on a regular basis.
Another might be to focus on simulation
for introductory courses.
Learning how to write and test code
for synthesis does not require a circuit board.
-- Mike Treseler
Article: 59552Austin, So that means theres no problem if DCM input is 25MHZ and CLKDV will be 12.5MHZ, assume that I will monitor the LOCK signal and reset the DCM if necessary. Am I right?Article: 59553
Right, Also monitor the input clock stopped status pin, and if you really want to be cautious, you could monitor the overflow bit and the DLL not in phase status bits (bit 0 is overflow, 1 is CLKIN stopped, and 7 is the not in phase bit). If any of these go high, you could reset the DCM. If you are also using the CLKFX output, bit 2 tells you if the DFS has stopped. These are the default status bit outputs (address 0000) on the 8 status output bits. One big advantage of the DCM over a PLL, is that there are 16 registers with 8 bits each to tell you what is going on in the circuit...... Austin Marlboro wrote: > Austin, > > So that means theres no problem if DCM input is 25MHZ and CLKDV will > be 12.5MHZ, assume that I will monitor the LOCK signal and reset the > DCM if necessary. > > Am I right?Article: 59554
Not true! Asynchronous counters, as well as synchronous ones, use flip-flops. And flip-flops or registers do not create glitches. Bad decoding does... And it's good to use the output flip-flop, but they are D-flip-flops, so the toggle control still needs a LUT. But who cares these days, when you have tens of thousands of them... Peter Alfke ======================= Luiz Carlos wrote: > > David, asyncronous counters generate glitches, not syncronous ones. > Use a syncronous design. > > You don't need to waste resources, use the output flip-flop of the > pin. > > Luiz Carlos. > dArticle: 59555
Hi, I am using Xilinx ISE (Synthesis using XST VHDL) to implement my design on a Virtex2 FPGA. I have the following questions. a) Is there a way to constrain ISE to place a "process" in a VHDL design, to a particular region on the FPGA? COnstraints guide says that AREA_GROUP is applicable to logic blocks. Can I make a VHDL "process" a logic block? I understand that this may not be a very efficient thing to do (in terms of area optimization), but can this be done (area is not a big constraint for my design)? b) The constraints guide says that AREA_GROUP affects routing too. How does it affect routing? c) Some modules of my design are in EDIF format, using a different target library than Synopsys or Xilinx. How do I go about adding them into my design? This must be a pretty common problem. The Development System Reference guide says that we need to include definition of all macros. I am not sure how to do this. It will help if you could point me to some reference that describes this. Your help will be deeply appreciated. Thanks, AmanArticle: 59556
Austin, I don't quite understand. If the buffered CLKDV cannot be used as a feedback, then how can the DCM account for the delay across the BUFG connected to CLKDV? It sounds like the CLKDV will be phase-aligned with the output of a BUFG connected to whatever is on the feedback, and if the CLKDV BUFG has a different load, then the output of the CLKDV BUFG won't be phase-aligned with the input. That is, the CLKDV and CLK0 outuputs will be phase-aligned, but the output of the BUFG connected to the CLKDV line won't be phase-aligned with the input, which seems to make the CLKDV output no more useful than a divider. -Kevin "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3F44E083.B61E5BC5@xilinx.com... > Kevin, > > The CLKDV output is also precisely phase aligned (when it coincides with the > incoming edge). > > CLK0 or CLK2X is used as CLKFB for all of the outputs. > > All outputs are generated by identical delay cells (as best as can be matched). > > Austin > > Kevin Neilson wrote: > > > From mt interpretation of the datasheet, the CLKFX and CLK2X and CLK0 > > outputs are phase-aligned with the input clock, but the CLKDV outputs are > > not, or, in other words, the CLKDV output does not subtract a BUFG delay. > > Is my interpretation incorrect? > > -Kevin > > > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > > news:3F44049D.C266402C@xilinx.com... > > > David, > > > > > > Well, the input clock of the DCM must be greater than 24 MHz, so you can't > > (by > > > the recommended specifications) use 20 MHz. > > > > > > The advantages of the DCM are the fact that the output will be phase > > aligned > > > with the input, and the outputs will directly drive the global clock > > resources. > > > > > > Austin > > > > > > David Lamb wrote: > > > > > > > Hi, > > > > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > > > > clock for other devices. I am using a virtexII device, so I can use the > > DCM > > > > wizard to divide the clock by two. How is this better than using a state > > > > machine with two states that inverts the output signal on each rising > > edge > > > > of the input clock? That scheme could be used to divide the clock by any > > > > power of two number...Why would I use the DCM for those? > > > > > > > > Thanks > > > > Dave > > > >Article: 59557
Hi all, I have an old project in Foundation4 that contains only schematic files. Can it migrate easily to Xilinx ISE 5.2? I heard that Aldec Acvite hdl can do the conversion but it is quite expensive... Thanks DaveArticle: 59558
David Lamb wrote: >Hi all, >I have an old project in Foundation4 that contains only schematic files. Can >it migrate easily to Xilinx ISE 5.2? I heard that Aldec Acvite hdl can do >the conversion but it is quite expensive... >Thanks >Dave > > > > I was told some time ago that there was no way to do this, at least using tools provided by Xilinx. Fortunately, my schematics have not been massive. JonArticle: 59559
Jeff Sampson wrote: > I remember back when I used Xilinx XC95xx CPLDs that Xilinx was > bragging about the pin locking capabilities of the 9500 series. And > the few designs that I did always routed to the assignment that I gave > the pins. > > Do the FPGAs have that kind of success? Or do people end up have to > redesign boards when they change the logic? (I can't imagine that.) > > I have given up on the Spartan II chips for my prototyping system. I > decided the 3.3V I/O was going to be too much screwing around to > interface with my other 5V parts. The reason is that I want to > randomly assign any pin as input or output and have it be 5V in or out > respectively. So I'll put my Spartan II chips on the shelf for stage 2 > develepment. (ie. first PCB prototype where I can group outputs into 8 > or 16 bit chunks and use level translator chips.) > > So I'm back to either XC31xxA or XC52xx parts. I can easily get these > parts and my software supports them. (I could probably get Spartan 1 > parts if I really tried hard. But the ones I have found are pretty > pricey.) Yuck! Why don't you use the original Spartan, with 5 V everything? They ARE a little more expensive than the Spartan II, but you don't have any voltage translation problems. The XCS30TQ144 ran me only $30 each, and that has a lot of gates on it! The XCS10PC84 is only about $18. > > I just don't want to go to the trouble of making the board with a > bunch of connectors and find out the PAR won't assign the bits on my > connectors. My designs will probably be lean on logic usage so I > assume that greatly improves my chances of successful routing. This is why I always design the FPGA (or CPLD) BEFORE laying out the board. I take the initial pin assignment and use that to design the board. Later changes are usually small enough that the P&R software can handle it. > > On the CPLD I tried to group the 8-bits of the connector to the same > function block. Is that necessary on the FPGAs? The XC3000 data sheet > doesn't even seem to group them. They are just labled "I/O" on the pin > listing. > It may actually be detrimental to the ground-bounce situation. Having only a few simultaneously-switching outputs on each set of power/ground supply pins is probably more robust. JonArticle: 59560
On 18 Aug 2003 13:07:39 -0700, orgulhosamenteso@hotmail.com (Pedro Claro) wrote: >"Davo" <dgwood@optushome.com.au> wrote in message news:<3f3f8e6f$0$10355$afc38c87@news.optusnet.com.au>... >> I want to work from home on my University project. The University uses >> Foundation 4.2 and I want to know if any of the free downloads (i.e Webpack) >> will be compatitble so that I can take me designs into Uni done from home >> and have no trouble simulating on their platform. I am sure this question >> has been asked and answered many times. Apologies if so. >> >> Dave > >I believe the Xilinx Webpack is compatible with the ISE 4.2. You can >also save only the vhdl files and the waveforms. > >Pedro Claro ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ I have Webpack 4.2WP3 and it supports only the SpartanII/IIe, Virtex2, Virtexe, Coolrunner and 9500 series devices. If I remember correctly the ISE 4.2 Student version will only support the XC4xxx and Spartan devices. Webpack does not come with coregen, but does have statecad and schematic editor. That is real nice for doing top level wiring and documentation purposes. For a student or hobby purposes the Webpack is fine piece of software. I have saved schematic files with webpack 4.2 no problem. The main limitation is that on the Spartan II is limited to 200K devices and IIe limited to 300K devices and the Virtex2 is limited to 250K and "e" are limited up to 300K devices. The only reason I have not moved up to 5.x webpack is that I am still using Windoze 98. If Webpack 5 or newer version had a linux port then I would consider switching. jamesArticle: 59561
Hello, Has anyone had any success with creating schematic pages with other tools and then getting ise 4.1.03i to accept it (preferably as an edif file)? I'm using Protel 99SE, which has a schematic entry package that I much prefer to the GHASTLY xst. There are some differences in the way they like to see schematics, though. Protel insists on ipads and opads, while ise insists on just having ports on the top level sheet. There are some other problems, like Protel puts a '&' before every symbol and pin name. Well, I just strip them in the editor. Oddly, Protel makes the ibuf and obuf parts disappear, so I'm converting the unwanted ipad and opads to ibuf and obuf. It is close, but not quite there, yet. Does anyone know of a freeware solution, have written a converter or have a procedure of what to do to make the conversion? Or, as another possibility, does anyone have a complete EDIF file that is completely acceptable to ise? (There is exactly one EDIF file in the entire examples dir, and it is a very complicated design, and not very good to use as a reference on how to construct a valid edif. Thanks much for any help you can offer! JonArticle: 59562
On Tue, 19 Aug 2003 18:49:20 GMT, "JoeG" <JoeG@nowhere.net> wrote: >Who has current design tools that will maintain legacy 22V10 design using >ABEL? We used to use DataIO's ABEL package and Minc Synario's ABEL(before >Xilinx swallowed them). > >Thanks in advance > >JoeG > ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ If you do a google search you may find a few web pages that have palasm or opaljr on their sites. I downlooaded a copy of opaljr v2.00 for windozes about a year ago. Needed to program a couple of 22V10's myself. There are a few programmer kits around that are still available. There are some individuals that have tried to build programmers that are of questionable use but are findable on the net. jamesArticle: 59563
Kevin, All BUFGs are identical (ie matched) and all ouitputs are matched. Thus, feedback is only required on one of them to match all of them. Austin Kevin Neilson wrote: > Austin, > I don't quite understand. If the buffered CLKDV cannot be used as a > feedback, then how can the DCM account for the delay across the BUFG > connected to CLKDV? It sounds like the CLKDV will be phase-aligned with the > output of a BUFG connected to whatever is on the feedback, and if the CLKDV > BUFG has a different load, then the output of the CLKDV BUFG won't be > phase-aligned with the input. That is, the CLKDV and CLK0 outuputs will be > phase-aligned, but the output of the BUFG connected to the CLKDV line won't > be phase-aligned with the input, which seems to make the CLKDV output no > more useful than a divider. > -Kevin > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > news:3F44E083.B61E5BC5@xilinx.com... > > Kevin, > > > > The CLKDV output is also precisely phase aligned (when it coincides with > the > > incoming edge). > > > > CLK0 or CLK2X is used as CLKFB for all of the outputs. > > > > All outputs are generated by identical delay cells (as best as can be > matched). > > > > Austin > > > > Kevin Neilson wrote: > > > > > From mt interpretation of the datasheet, the CLKFX and CLK2X and CLK0 > > > outputs are phase-aligned with the input clock, but the CLKDV outputs > are > > > not, or, in other words, the CLKDV output does not subtract a BUFG > delay. > > > Is my interpretation incorrect? > > > -Kevin > > > > > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > > > news:3F44049D.C266402C@xilinx.com... > > > > David, > > > > > > > > Well, the input clock of the DCM must be greater than 24 MHz, so you > can't > > > (by > > > > the recommended specifications) use 20 MHz. > > > > > > > > The advantages of the DCM are the fact that the output will be phase > > > aligned > > > > with the input, and the outputs will directly drive the global clock > > > resources. > > > > > > > > Austin > > > > > > > > David Lamb wrote: > > > > > > > > > Hi, > > > > > I have a 20Mhz external clock going in my fpga. I need to output a > 10Mhz > > > > > clock for other devices. I am using a virtexII device, so I can use > the > > > DCM > > > > > wizard to divide the clock by two. How is this better than using a > state > > > > > machine with two states that inverts the output signal on each > rising > > > edge > > > > > of the input clock? That scheme could be used to divide the clock by > any > > > > > power of two number...Why would I use the DCM for those? > > > > > > > > > > Thanks > > > > > Dave > > > > > >Article: 59564
In article <3F3C0ED8.22C4376A@xilinx.com>,
Peter Alfke <peter@xilinx.com> wrote:
>There are only a few exceptions:
>XC5200 and XC6200 are orphans.
I thought the upgrade path for XC5200 was Virtex and Spartan: the logic cell
in Virtex seems like an XC5200 superset: 4 input LUTs with CY_MUX-style
carry chains. No crystal oscillator in either.
XC6200 is the real orphan.
I have now used: XC2000, XC3000, XC3000A, XC3100A, XC4000E, XC4000XLA,
XC5200, XCVxxx, XCVxxxE, XC2Sxx, and XC2Vxxx. Oh yeah and XC95xxxXL and
XCR3xxxXLs. Waiting for XC3V....
I remember when my current employer arrogantly informed the Xilinx rep that
they had chance to replace one of our datapath ASICs. All I could think was
that Xilinx had been around way before this company started and would be
around way after it was gone...
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 59565
In article <3F416E2C.12F31ABC@andraka.com>,
Ray Andraka <ray@andraka.com> wrote:
>Add to the list:
> Cutting out half the LUT RAMs/SRL16s in SpartanIII
Yeah this was a bad idea.
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 59566Peter Alfke <peter@xilinx.com> wrote in message news:<3F45067F.9F36C084@xilinx.com>... > Not true! > Asynchronous counters, as well as synchronous ones, use flip-flops. And > flip-flops or registers do not create glitches. Bad decoding does... > And it's good to use the output flip-flop, but they are D-flip-flops, so > the toggle control still needs a LUT. But who cares these days, when you > have tens of thousands of them... > Peter Alfke Sorry, I thought of using the flip-flops asynchronous sets and/or resets. Luiz CarlosArticle: 59567
Grrrrr! :-( Luiz Carlos wrote: > > > Sorry, I thought of using the flip-flops asynchronous sets and/or resets. > > Luiz CarlosArticle: 59568
Mikeandmax wrote: > > Hi Jim - <snip > Time-bomb licenses have never been one of my favorites, and a 'full-up' package > with a permanent license is not an expensive proposition. I'll leave that up to > the sales rep to figure out tho' :) > > I will pass along the suggestion for a minimal download tool. Thanks, could you also ask if the ABEL portion is actually time-bombed ? It rates a minimal mention in the docs, and it is possible they did not bother to time-bomb the ABEL flow, or maybe left the command-line compiler as-was. Would solve the OP's problems... -jgArticle: 59570
Andrew Paule wrote: > > Atmel I might believe (honeywell will keep some of it going, but > probably only for internals), but Lattice will stop making them once > financials dictate. How much time are you going to bet a semi company > runs these things as they are now OLD -spending time with old technology > in this industry (even though some may stay) is setting yourself up - > reason I mentioned intel in an earlier post - our company had to deliver > a 10 year support - oops processors dropped, last time buy was not big > enough, now how did I do that four years ago, did I really do that - can > I make it work "better"???? - oops, no shippee for a couple a months > boss - sorry. Can I have your espresso machine at my desk for awhile? > > I think that the current shake up in our industry may well lead some of > the smaller chamber/wafer manufacturers to go belly up - even if you > think you're in good company, look around. Mot made ECL ASICs for years, > with support provisions, but when their last CVD on the line failed, and > they could not get it back up, Cray fell onto hard times (only one of > the many reasons, but still a valid one - just one piece of the > crumble). Upgrading the code to verilog will allow them to keep using > the "current" parts (22v10's) - and then go to different parts later. > The company that Joe works for is going to have to support the design > for many years to come, delaying the inevitable may make it so that > there are no more of us people who used abel (albeit not for the last 10 > yeras except to convert to verilog) are still around - you don't want > the consequences if someting happens in this arena. The little part is > min priced at about 2.29 (arrow) for a 25 ns part - I used to buy the > 7032 parts for less than that. I hope you're right, but I've been > burned too many times, pessimism (sp) kicks in. All valid points, for new designs, but the OP was wanting to maintain existing products - to me that does not include PCB respins .... I would hope the graduates of 10 years hence do not 'drop dead from culture shock' when seeing ABEL code - raise their eyebrows, sure, but they should be able to maintain it :) > > test vectors? I can find tons of college kids who can generate a good > test bench, I'd better be able to - your machine is running a processor > that was tested on equipment I used to build - guaranteed. I was meaning append of functional test vectors, to the JED file. ( something ABEL and CUPL do ) Last time I checked, the fancy HDLs SIMs could do ns timing, but lost the ability to generate functional/state test vectors in JED files - did I miss something ? -jgArticle: 59571
Problem for this application is that support will still have to be done for some time - when do you jump to new tools and parts. I bet you can get boards and parts and assembly done cheaper now than a year ago, and if you wait a year, we might all be back in the late 90's mess - remember tant caps 1 year, boards backed out etc. I've still got applications that run on CPM around - but how many can say that - also have a "working" PDP-11 in my garage. Get me some hard sectored floppies for it. james wrote: >On Tue, 19 Aug 2003 18:49:20 GMT, "JoeG" <JoeG@nowhere.net> wrote: > > > >>Who has current design tools that will maintain legacy 22V10 design using >>ABEL? We used to use DataIO's ABEL package and Minc Synario's ABEL(before >>Xilinx swallowed them). >> >>Thanks in advance >> >>JoeG >> >> >> >^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ > >If you do a google search you may find a few web pages that have >palasm or opaljr on their sites. I downlooaded a copy of opaljr v2.00 >for windozes about a year ago. Needed to program a couple of 22V10's >myself. There are a few programmer kits around that are still >available. There are some individuals that have tried to build >programmers that are of questionable use but are findable on the net. > >james > > > >Article: 59572
On Thu, 21 Aug 2003 09:49:51 +1200, Jim Granville <jim.granville@designtools.co.nz> wrote: >Mikeandmax wrote: >> >> jim thought - >> >My understanding is the 'free' version is a 6 month demo, and $$$ are >> >needed for more than that ? >> > Lattice also do not have a separate ABEL download, but instead have one >> >very large bundle. >> > Seems there would be an opening for a smaller download, of ABEL only, >> >for SPLD and CPLDs (eg new 4000 family ) ? >> > >> >-jg >> >> Well, the free license expires in 6 months, and you can always get another free >> license in 6months, so it'll never cost more than a minute on the weblicense >> page. > > Thanks Mike, > > The problems with this is not the 'never cost more than a minute', but >the real risk exposure of the user, to a change in policy or >circumstance at Lattice. > > Timebombed licenses are a disaster waiting to happen. > I could not agree with this more ! In fact after being a long time Lattice fan and spec'ing tons of their parts have stopped using their parts because I didn't want to potentially deal with the timebomb support issue. ( and now that I'm over the learning curve with the competition it's easier to keep using A&X )Article: 59573
Hi, If someone can help me with this, I'll be very happy. I would like to change the slew rate of some of my output pins of a SpartanII to "FAST". Tried to put it in the UCF file, it obeys all the other constraints that I put in there, but not the "FAST" one. The syntax used was NET "c" FAST; I also declared some stuff in my VHDL source as follows: attribute FAST : string; attribute FAST of c : signal is "true"; I looked at the properties of the Place-and-route but cannot find anywhere where the option has to be enabled. The software is happy with all of this, but the PAD report still says that pin c is "SLOW". Thanks very much. Stephen du Toit I triedArticle: 59574
Hi! I have an question about the main differences between this two filter architecture. In my design I would like to minimize slice resources used by the filter also I have to take in consideration that my sampling frequency. The MAC filter is ideal for my requirements but I would like to hear some more opinion about that. Filter details: Filter type: FIR (raised-cosine) Filter order : 32 Sampling freq.: 5 MHz Decimation rate: 4 I also have a question about CIC filter and its related CIC Gain, if anyone can help me understand this issue, I would really like to know more about it. Best regards, Sasa
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