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Thank you very much for your help. Another solution is migrating from XC2S600E to Spartan-3. I found there are eight of IBUFG in Spartan-3, right? But how many BUFG are there in it? Same as Spartan-IIE? Besides, is BUFGMUX output also a clock network? "Austin Lesea" <Austin.Lesea@xilinx.com> : Louis, : : Too bad you ran out of resources, and can not change its design. : : I suspect that the only way to get around this is to check the timing and the routing using : FPGA_Editor, and hand fix any places where the timing is vilolated. : : More constraints may cause the design to become unroutable once you run out of resources. : : Austin :Article: 59526
1. The DCMs are already there. Why use logic resources unless you run out of DCMs? 2. The DCMs will guarantee zero phase error between the two clocks. This may not be necessary depending on the application, but it's certainly a nice perk. 3. Unless there's a compelling reason not to do this, why not? It's easy. Jake "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:<bi0ufn$6nt$1@home.itg.ti.com>... > Hi, > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > clock for other devices. I am using a virtexII device, so I can use the DCM > wizard to divide the clock by two. How is this better than using a state > machine with two states that inverts the output signal on each rising edge > of the input clock? That scheme could be used to divide the clock by any > power of two number...Why would I use the DCM for those? > > Thanks > DaveArticle: 59527
From mt interpretation of the datasheet, the CLKFX and CLK2X and CLK0 outputs are phase-aligned with the input clock, but the CLKDV outputs are not, or, in other words, the CLKDV output does not subtract a BUFG delay. Is my interpretation incorrect? -Kevin "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message news:3F44049D.C266402C@xilinx.com... > David, > > Well, the input clock of the DCM must be greater than 24 MHz, so you can't (by > the recommended specifications) use 20 MHz. > > The advantages of the DCM are the fact that the output will be phase aligned > with the input, and the outputs will directly drive the global clock resources. > > Austin > > David Lamb wrote: > > > Hi, > > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > > clock for other devices. I am using a virtexII device, so I can use the DCM > > wizard to divide the clock by two. How is this better than using a state > > machine with two states that inverts the output signal on each rising edge > > of the input clock? That scheme could be used to divide the clock by any > > power of two number...Why would I use the DCM for those? > > > > Thanks > > Dave >Article: 59528
Peter Alfke wrote: > > Jeff Sampson wrote: > > >>I guess because the big tables of I/O standards that I didn't recognize scared >>me. ;-) And then Peter pointed out that 5V tolerant doesn't mean 5V tolerant >>and quoted using limiting resistors. > > > Not true. I made a distinction between "tolerant" and "compatible". That was meant to be a joke. I guess I needed one more smiley faces... What you wrote was: > We use the English language carefully: > TOLERANT means that the pin tolerates to be driven with a specified > standard voltage, perhaps a series-resistor is needed. (Heck, with the > right resistor, we are 1000-V tolerant!) > COMPATIBLE means that we can receive and drive the proper level > directly. I thought this odd. From everything I have seen Xilinx uses the term "tolerant" to define an input. As far as I can see the term tolerant simply means the upper clamp diode is disabled. Then by default (or maybe it is switched) a zener type clamp circuit conducts at 6.5V (I think I saw 5.5V somewhere else). So it seemed to me that you were mixing three concepts into 2 catagories. "Compatible" (in Spartan II terms) means the clamp diode to Vcco is enabled and an input voltage of 0-Vcco is acceptable. In "Tolerant" mode the clamp diode is disabled and an input voltage of 0-5V is acceptable. Now anything above the clamp voltage is shunted (I assume to ground) through the zener clamp. (ie. A classic shunt regulator, Like you do to make a fake RS232 converter) It looked to me like that was something other than "Compatible" or "Tolerant" since you are now trying to drive outside the acceptable voltage limits. So the reference to "the right resistor, we are 1000-V tolerant!" seemed totally irrelevant. So I didn't know if you were kidding, or talking about something else. But it sounded to me like you were saying "5V tolerant isn't really 5V tolerant". >>But I tried to balance that with statements >>like "You can lead a 286 to water, but you can't make it drink." :-) >> >>So I went back and checked the spec sheets for the parts I already have defined: >> >> >>>Part ViL ViH VoL VoH >>> >>>IDT 7208 FIFO 0.8 2.0 0.4 2.4 >>>KM681000 RAM 0.8 2.2 0.4 2.4 >>>ADC1175 1.0 3.0 0.4 2.4 >>>LM1881 - - 0.8 4.5 >>>OV5017 Imager 0.8 2.0 0.6 2.4 >>> >>>The ATMega103L on the STK300 board can run at 5V or 3.3V. >> >>[If I use a big part like Spartan then I probably don't need an external FIFO] >> >>I see that the only one that may not work seems to be the ADC1175. So open drain >>and a pullup to 5V? > > 3.0 is actually lower than 3.3. So you are safe. Spartan-II overdrives > the ADC input by 300 mV. The only number I could find in the spec was page 3 of ds001-3.pdf "DC input and output levels" lists the highest VoH of 2.4V. Should I not use that number? Your "What are Virtex and Spartan-II I/O Pins Doing?" document says "If they are active, they will be pulling all the way to Vcco, or pulling to ground (except GTL, which pulls to ground only, or LVDS, which is a current sink or source)". Are those the numbers I should be using instead of something from the spec sheet? >>So, do I just default all inputs to LVTTL? > > > Read it up in TechXclusives: > http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp > > and go to "What are the...pins doing?", byAustin and Peter, published > Jan 03. > It tells you that LVTTL is a pin that does nnot have the clamping diode > to Vcc. I assume you mean Vcco and not Vcc. > I would go with LVCMOS and Vcco=3.3 V. That gives you the diode to Vcco. > Then you configure the output as open collector ( i.e. use the signal > that drives the data also to drive the Tristate output signal ( note the > polarity, which is up to you to adjust). Now you need an external > pull-up resistor to 5 V, and it will pull a whole diode drop higher than > Vcco, i.e. to 4.0 V in your case. > It's all not necessary, since 3.3 V already gave you enough drive, but > apparently you want more noise immunity. Both the spec ds001_2.pdf and your document "What are Virtex and Spartan-II I/O Pins Doing?" state that all three modes; LVTTL, LVCMOS2 and PCI5V all have the clamp diode disabled. Is there a difference between LVTTL and LVCMOS2. And do I want a clamp diode? If I can set the tristate output to open-drain, an external resistor will pull to 5V. The zener should still be in effect if it goes above that. The reason I mentioned GTL is because according to the spec sheet, that was the only apparent way to get an open-drain output. Speaking of the spec sheet (ds001_1.pdf - ds001_4.pdf), is there a REAL spec sheet? Or is that it? And why is it in 4 parts. And is the Spartan really a subset of the Virtex? If so can I assume that statements about the Virtex also apply to the Spartan? I'll read through the references that Peter and Austin posted. Maybe it will all become clear. > Forget about GTL, no need for it. > Peter Alfke > > > > This gives me 5V tolerance and > >>doesn't require VREF. Can all outputs also default to LVTTL? Or is one of the >>PCI standards a better choice? Except outputs that have to swing higher, then >>would I use OBUF_GTL and an extertnal pullup for those? >> >>And can I do OBUFT_GTL with external pullup? >> >>If I do a bidirectional do I use IOBUF_GTL with external pullup? But that sets >>up a diferential input buffer. Maybe I'll just avoid using bidirectional with a >>5V swing. >> >>Will setting GTL require the VREF pin? Or is there another way to specify open >>drain? If I can specify it directly then I could run LVTTL and tell it the >>output is open drain. >> >>[I'm sorry to be such a pain about this. Does Xilinx have an APP note or White >>Paper about 5V interfacing?] >> >>-- >>Jeff Sampson >>http://tcrobots.org/members/jsamp.htm -- Jeff Sampson http://tcrobots.org/members/jsamp.htmArticle: 59529
Jeff Sampson wrote: > Peter Alfke wrote: >> Then you configure the output as open collector ( i.e. use the signal >> that drives the data also to drive the Tristate output signal ( note the >> polarity, which is up to you to adjust). Now you need an external >> pull-up resistor to 5 V... > The reason I mentioned GTL is because according to the spec > sheet, that was the only apparent way to get an open-drain output. Oh, it just hit me. You don't actually configure it as open collector, you drive the output low OR it is tristate. If I just tie the data bit low will it optimize it away? Or do I need to drive the data bit and the tristate at the same time? I guess I can just try it, huh? -- Jeff Sampson http://tcrobots.org/members/jsamp.htmArticle: 59530
I run synplicity tools that can go to lattice GALs (I think that this is about all that's left out there) - who makes PALs anymore? Anyway, most of the ABEL code can be quickly (run a perl script on it ) upgraded to verilog - only the test vectors and pin assignments will need to be dealt with, but these are also easy going into a good simulator/program verification environment. The other thing that this does is free you from the PALs - I think that lattice is the last one making them, and neither arrow or avnet stock em - digikey lists them as obsolete, who else - time to upgrade unless you only put out a few units a year or are EOLing the thing I know you aircraft guys have to make things for years, but you could qualify newer devices here, and save time in the future - you've been through this before many times (I can say processor -did some work for a friend on one for you), and you are going to have to go through the hoop eventually. Andrew JoeG wrote: >We literally have hundreds of PALs/GALs to maintain. Nevertheless after one >migrates from ABEL to VHDL or Verilog which tool can target the code to a >22V10 these days? > >JoeG > > >"Andrew Paule" <lsboogy@qwest.net> wrote in message >news:sQD0b.1565$br1.56228@news.uswest.net... > > >>Just convert your abel code to verilog - it's easy, and then you don't >>have to worry about it for a few more years. You can do the conversion >>for a PAL (16xx,20xx, 22xx) in an hour or so. >> >>Andrew >> >>JoeG wrote: >> >> >> >>>Who has current design tools that will maintain legacy 22V10 design using >>>ABEL? We used to use DataIO's ABEL package and Minc Synario's ABEL(before >>>Xilinx swallowed them). >>> >>>Thanks in advance >>> >>>JoeG >>> >>> >>> >>> >>> >>> > > > >Article: 59531
Andrew Paule wrote: > > I run synplicity tools that can go to lattice GALs (I think that this is > about all that's left out there) - who makes PALs anymore? Lattice, Atmel & Anachip/ICT are active, and cypress is in EOL mode. > Anyway, most > of the ABEL code can be quickly (run a perl script on it ) upgraded to > verilog - only the test vectors and pin assignments will need to be > dealt with, but these are also easy going into a good simulator/program > verification environment. What about test vectors in JED files ? > The other thing that this does is free you > from the PALs - I think that lattice is the last one making them, and > neither arrow or avnet stock em - digikey lists them as obsolete, who > else Search for 22V10 in findchips, and you get plenty. Digikey only show TI's old OTP 22V10s as obsolete, they have plenty of Atmel variants, and some cypress ones. Search for 22CV10/18CV8, and all the ICT/PEEL devices show up. > - time to upgrade unless you only put out a few units a year or are > EOLing the thing I know you aircraft guys have to make things for > years, but you could qualify newer devices here, and save time in the > future - you've been through this before many times (I can say processor > -did some work for a friend on one for you), and you are going to have > to go through the hoop eventually. The 22V10 will be around for a long time yet, as will the 16V8, and maybe the 18CV8. We still do new designs using the ATF16V8BQL, but you are right that the 22V10 is under some pressure from 32 MCell CPLDs. The 16V8 is a little safer. What's needed there is a smaller package for 32MC devices. We have suggested vendors look at bonding a 32MC device into a 22V10 footprint. - jgArticle: 59532
Austin Lesea wrote: > JoeG, > > How do you support the Mentor schematic capture software? Again -- we keep a couple of old Sun Workstation that support SunOS 4.1.4. On these same Workstation we keep a copy of Mentor's CAD tools Version A4F. XACT 5.2 will NOT work on Solaris! > > We have archived versions of XACT for PC's. I have XACT for PCs on CDROM too -- but the problem is moving the Mentor schematic based designs from Sun Workstations to a PC environment. > > Maybe you could email me directly, and I'll put you in touch with the right > folks? I will do that ... > > As has been pointed out before, I am not really one person, but one person who > knows all the right people....to ask. > > Austin > Thanks again ... The problem as I see it is NOT with the design capture tools but with the place/route/generate Bitstream tool for the XC4000! I dont mind moving/migrating the design database onto a newer platform/tool. The problem is what to do with the netlist/edif/xnf file! --- I need to be able to place/route & generate a bitstream on a *current* host such as a Pentium 4/Xenon under WinXP or Win2K or via Ultra Sparc under Solaris. JoeGArticle: 59533
JoeG wrote: > <snip> > The problem as I see it is NOT with the design capture tools but with > the place/route/generate Bitstream tool for the XC4000! I dont mind > moving/migrating the design database onto a newer platform/tool. The > problem is what to do with the netlist/edif/xnf file! --- I need to be > able to place/route & generate a bitstream on a *current* host such as a > Pentium 4/Xenon under WinXP or Win2K or via Ultra Sparc under Solaris. Sounds reasonable to me - let us know how you get on. SCH and GUI Stuff is likely to have fish-hooks ( as you realise ), but one could expect place/route/bitstream to be 'portable' software ? Simulation could be a challenge, but that could be an open source timing-library approach ? ( after all, the older devices are both simpler, and slower :) On real legacy 'maintain only' designs, simulation is not a 'must have', but it would be good for teaching. -jgArticle: 59534
Atmel I might believe (honeywell will keep some of it going, but probably only for internals), but Lattice will stop making them once financials dictate. How much time are you going to bet a semi company runs these things as they are now OLD -spending time with old technology in this industry (even though some may stay) is setting yourself up - reason I mentioned intel in an earlier post - our company had to deliver a 10 year support - oops processors dropped, last time buy was not big enough, now how did I do that four years ago, did I really do that - can I make it work "better"???? - oops, no shippee for a couple a months boss - sorry. Can I have your espresso machine at my desk for awhile? I think that the current shake up in our industry may well lead some of the smaller chamber/wafer manufacturers to go belly up - even if you think you're in good company, look around. Mot made ECL ASICs for years, with support provisions, but when their last CVD on the line failed, and they could not get it back up, Cray fell onto hard times (only one of the many reasons, but still a valid one - just one piece of the crumble). Upgrading the code to verilog will allow them to keep using the "current" parts (22v10's) - and then go to different parts later. The company that Joe works for is going to have to support the design for many years to come, delaying the inevitable may make it so that there are no more of us people who used abel (albeit not for the last 10 yeras except to convert to verilog) are still around - you don't want the consequences if someting happens in this arena. The little part is min priced at about 2.29 (arrow) for a 25 ns part - I used to buy the 7032 parts for less than that. I hope you're right, but I've been burned too many times, pessimism (sp) kicks in. test vectors? I can find tons of college kids who can generate a good test bench, I'd better be able to - your machine is running a processor that was tested on equipment I used to build - guaranteed. Andrew Jim Granville wrote: >Andrew Paule wrote: > > >>I run synplicity tools that can go to lattice GALs (I think that this is >>about all that's left out there) - who makes PALs anymore? >> >> > >Lattice, Atmel & Anachip/ICT are active, and cypress is in EOL mode. > > > >> Anyway, most >>of the ABEL code can be quickly (run a perl script on it ) upgraded to >>verilog - only the test vectors and pin assignments will need to be >>dealt with, but these are also easy going into a good simulator/program >>verification environment. >> >> > >What about test vectors in JED files ? > > > >> The other thing that this does is free you >>from the PALs - I think that lattice is the last one making them, and >>neither arrow or avnet stock em - digikey lists them as obsolete, who >>else >> >> > >Search for 22V10 in findchips, and you get plenty. > >Digikey only show TI's old OTP 22V10s as obsolete, they have plenty >of Atmel variants, and some cypress ones. > >Search for 22CV10/18CV8, and all the ICT/PEEL devices show up. > > > >>- time to upgrade unless you only put out a few units a year or are >>EOLing the thing I know you aircraft guys have to make things for >>years, but you could qualify newer devices here, and save time in the >>future - you've been through this before many times (I can say processor >>-did some work for a friend on one for you), and you are going to have >>to go through the hoop eventually. >> >> > > The 22V10 will be around for a long time yet, as will the 16V8, and >maybe the 18CV8. > > We still do new designs using the ATF16V8BQL, but you are right that >the >22V10 is under some pressure from 32 MCell CPLDs. The 16V8 is a little >safer. > > What's needed there is a smaller package for 32MC devices. We have >suggested vendors look at bonding a 32MC device into a 22V10 footprint. > > - jg > >Article: 59535
"Peter Alfke" <peter@xilinx.com> wrote in message news:3F44058B.25DB9E3F@xilinx.com... [JB] > > Hmmm... Peter, I suspect you are not quite so aware of the constraints > > on typical college lecturers and support departments as I am :-) [PA] > Jonathan, you make a good point. I had not thought about it too much. > When I went to college, we used vacuum tubes, and the word software was > not yet coined. I'm obviously just a bit younger than you - we had a PDP-8F in the physics lab :-) > I apologize for my crass comments, and I offer no solutions, short of > better funding for schools and ( perish the thought ) higher taxes. Thanks, but no apology is needed - everything you said was absolutely right. And Xilinx has been one of the most creative vendors in offering interesting and useful design kits to academia. (Not even a sniff of enlightened self-interest there, of course ;-> ) One solution, I humbly suggest, is for practitioners and educators to swap places on a regular basis. One of the most fulfilling (and manic) episodes in my career was when I was spending half my life lecturing and half doing electronics in the "real world". Each profession has much to learn from the other. What's more, it might weed out some educators who don't know what they're doing, and some practitioners who can't communicate about what they're doing! > But somehow the next generation engineers must not be educated using > wire-wrapped logic boards with 10- to 20-year old devices. That > misdirects their imagination in the wrong direction, and stifles their > enthusiasm. Absolutely. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 59536
Hello, I'm new in the fpga design and have a question about the timing summary from ise 5.2 from xilinx. Are the minimum period of a final design announced by the software bundle realistic ? Thank you in advance smuArticle: 59537
Hi Jim - > The problems with this is not the 'never cost more than a minute', but >the real risk exposure of the user, to a change in policy or >circumstance at Lattice. a good point, as Cypress, Intel,National, TI, Phillips, and AMD PLD users have found over the years. I guess where Lattice is a bit different is that it's ONLY business is PLDS, so we are more likely to continue to support 'legacy' customers. Our recent introduction of a 2.7ns 1.8v ispJTAG22V10 in a 5mmx5mm qf package would hopefully indicate there are still some legs left in the business. The original poster mentions 'hundreds' of PAL/GAL designs to support and maintain, the best solution is probably to provide the native language support necessary, rather than convert to other tool flows. Time-bomb licenses have never been one of my favorites, and a 'full-up' package with a permanent license is not an expensive proposition. I'll leave that up to the sales rep to figure out tho' :) I will pass along the suggestion for a minimal download tool. Mike Thomas LSC FAEArticle: 59538
Hi I know there are people (reading this newsgroup) with S3 samples so if someone has one (1 pcs) XCF02 ES that he could give away PLEASE PLEASE! (doesnt have to be given away, but there is no price tag for samples that would justify selling them) - if there is something I can do or give in return, just ask. I designed a PCB with XC2S200E and Platform Flash, PCBs are ready next tuesday, but our disti says any XCF devices are 4-6 week leadtime and that may even be longer in real life, so I am kind in problems. need to present my board - and with no configuration memory (or wire soldered 18V02) its no fun. anttiArticle: 59539
Hi guys, In my project, I will also use DCM to derive CLKDV (1/2 clock) but I think there may be an issue. The DCM input frequency is not fix, actually it's configured at power up only, after that the frequency won't change anymore. The frequency can be anything between 66 MHZ (max) and 25 MHZ (min). At the high frequency region there's no problem at all, but when it is lower 58 MHZ, the CLKDV will be lower 24MHZ. Can I use the CLKFX with M=1 and D=2 instead of CLKDV? Or we have a better solution than this? Many thanks,Article: 59540
Ok sounds like I should use the flip flops. I don't care about the delay, since this clock is for other part of the circuit (outside the fpga) that are not synchronized with anything else. However, I have always been told to never use the output of a counter as a clock since it can glitch. This is almost what I'm about to do... Is there a way to avoid glitches? Thanks David "Peter Alfke" <peter@xilinx.com> wrote in message news:3F440FD5.C1F6E488@xilinx.com... > Go into Frequency Synthesis mode, and use M=2, D=4. > But why? Do you need coincident edges? > As a general rule: > Always tell us a little more than the absolute bare-bone question... > > Peter Alfke > ======================= > David Lamb wrote: > > > > Actually, the DCM only works on frequency higher than 24Mhz, so I would need > > to double the clock in order to use it. ( I heard the DCM can do this, but I > > just don't see how...I can't do it in the wizard using any options > > possible...). > > David > > > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > > news:bi0ufn$6nt$1@home.itg.ti.com... > > > Hi, > > > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > > > clock for other devices. I am using a virtexII device, so I can use the > > DCM > > > wizard to divide the clock by two. How is this better than using a state > > > machine with two states that inverts the output signal on each rising edge > > > of the input clock? That scheme could be used to divide the clock by any > > > power of two number...Why would I use the DCM for those? > > > > > > Thanks > > > Dave > > > > > >Article: 59541
Bill Diehls wrote: > I've been working with the Xilinx Webpack on FPGA designs for a few > months with good success. A recent design is approaching full device > utilization and parts of my design are breaking because they no longer > meet timing constraints. > > Being a newbie, I suspect that some of the layout tools and timing > constraint managers need to be employed to tweak my design back into > shape, but I'm having trouble figuring out how to use these. I'm > wondering if there is some good documentation out there for how to do > this, namely with Xilinx -- or better yet, a book of some sort (?) There are several different ways you might proceed. Before you even start, you might want to think about buying larger/faster parts. Spending lots of time speeding up a design when a $2.00 more expensive faster part will meet timing might not be cost effective unless your time is free, the production run is large or the cost of changing parts is high (FPGA on Mars, for example). -- Phil HaysArticle: 59542
Peter, Won't work, output freq. must also be > 24 MHz..... Austin Peter Alfke wrote: > Go into Frequency Synthesis mode, and use M=2, D=4. > But why? Do you need coincident edges? > As a general rule: > Always tell us a little more than the absolute bare-bone question... > > Peter Alfke > ======================= > David Lamb wrote: > > > > Actually, the DCM only works on frequency higher than 24Mhz, so I would need > > to double the clock in order to use it. ( I heard the DCM can do this, but I > > just don't see how...I can't do it in the wizard using any options > > possible...). > > David > > > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > > news:bi0ufn$6nt$1@home.itg.ti.com... > > > Hi, > > > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > > > clock for other devices. I am using a virtexII device, so I can use the > > DCM > > > wizard to divide the clock by two. How is this better than using a state > > > machine with two states that inverts the output signal on each rising edge > > > of the input clock? That scheme could be used to divide the clock by any > > > power of two number...Why would I use the DCM for those? > > > > > > Thanks > > > Dave > > > > > >Article: 59543
Kevin, The CLKDV output is also precisely phase aligned (when it coincides with the incoming edge). CLK0 or CLK2X is used as CLKFB for all of the outputs. All outputs are generated by identical delay cells (as best as can be matched). Austin Kevin Neilson wrote: > From mt interpretation of the datasheet, the CLKFX and CLK2X and CLK0 > outputs are phase-aligned with the input clock, but the CLKDV outputs are > not, or, in other words, the CLKDV output does not subtract a BUFG delay. > Is my interpretation incorrect? > -Kevin > > "Austin Lesea" <Austin.Lesea@xilinx.com> wrote in message > news:3F44049D.C266402C@xilinx.com... > > David, > > > > Well, the input clock of the DCM must be greater than 24 MHz, so you can't > (by > > the recommended specifications) use 20 MHz. > > > > The advantages of the DCM are the fact that the output will be phase > aligned > > with the input, and the outputs will directly drive the global clock > resources. > > > > Austin > > > > David Lamb wrote: > > > > > Hi, > > > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > > > clock for other devices. I am using a virtexII device, so I can use the > DCM > > > wizard to divide the clock by two. How is this better than using a state > > > machine with two states that inverts the output signal on each rising > edge > > > of the input clock? That scheme could be used to divide the clock by any > > > power of two number...Why would I use the DCM for those? > > > > > > Thanks > > > Dave > >Article: 59544
except that the DCM needs a >24 MHz input clock to use the CLKDV output..... Austin Jake Janovetz wrote: > 1. The DCMs are already there. Why use logic resources unless you run > out of DCMs? > > 2. The DCMs will guarantee zero phase error between the two clocks. > This may not be necessary depending on the application, but it's > certainly a nice perk. > > 3. Unless there's a compelling reason not to do this, why not? It's > easy. > > Jake > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:<bi0ufn$6nt$1@home.itg.ti.com>... > > Hi, > > I have a 20Mhz external clock going in my fpga. I need to output a 10Mhz > > clock for other devices. I am using a virtexII device, so I can use the DCM > > wizard to divide the clock by two. How is this better than using a state > > machine with two states that inverts the output signal on each rising edge > > of the input clock? That scheme could be used to divide the clock by any > > power of two number...Why would I use the DCM for those? > > > > Thanks > > DaveArticle: 59545
Anil Khanna wrote: > Yes, you did ask the million dollar question. Here is a quick run down the > list of things you could do to squeeze performance out of a FPGA > > 1. Firstly, make sure the coding style is optimized for FPGAs. See Xilinx > documentation for more info. > There are pointers for efficient use of their architecture and dedicated > resources. > 2. You could always overconstrain your design but this might not get you > much if you design is 80%+ utilized. A few more points: 4. Turn up the placement and route effort in PAR. 5. Run different PAR cost tables. 6. Floorplan datapath memories and registers to fixed locations using the graphical floorplanner. 7. Floorplan areas of the design to area constraints using the graphical floorplanner. > 3. If you really need to get in there and meet timing then you could try the > new FPGA physical synthesis tool from Mentor Graphics. For more info, go to > http://www.mentor.com/precisionphysical/ Also see: http://www.synplicity.com/products/amplify/index.html Amplify has been around for a few years. The Mentor tool is new. -- Phil HaysArticle: 59546
The output of a counter *register* will never glitch. It's a register. Registers don't glitch. The output of a counter *decode* will quite probably glitch. Don't use a decode. "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message news:bi2m0c$ig1$1@home.itg.ti.com... > Ok sounds like I should use the flip flops. I don't care about the delay, > since this clock is for other part of the circuit (outside the fpga) that > are not synchronized with anything else. However, I have always been told to > never use the output of a counter as a clock since it can glitch. This is > almost what I'm about to do... > Is there a way to avoid glitches? > Thanks > David > > > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3F440FD5.C1F6E488@xilinx.com... > > Go into Frequency Synthesis mode, and use M=2, D=4. > > But why? Do you need coincident edges? > > As a general rule: > > Always tell us a little more than the absolute bare-bone question... > > > > Peter Alfke > > ======================= > > David Lamb wrote: > > > > > > Actually, the DCM only works on frequency higher than 24Mhz, so I would > need > > > to double the clock in order to use it. ( I heard the DCM can do this, > but I > > > just don't see how...I can't do it in the wizard using any options > > > possible...). > > > David > > > > > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > > > news:bi0ufn$6nt$1@home.itg.ti.com... > > > > Hi, > > > > I have a 20Mhz external clock going in my fpga. I need to output a > 10Mhz > > > > clock for other devices. I am using a virtexII device, so I can use > the > > > DCM > > > > wizard to divide the clock by two. How is this better than using a > state > > > > machine with two states that inverts the output signal on each rising > edge > > > > of the input clock? That scheme could be used to divide the clock by > any > > > > power of two number...Why would I use the DCM for those? > > > > > > > > Thanks > > > > Dave > > > > > > > > > >Article: 59547
Marlboro, If you wish to keep everything phase aligned, min input F is > 24 MHz, and min output F is > 24 MHz. If you wish to use the CLKFX by itself, Fin > 1 MHz, and Fout> 24 MHz. Changing frequency by too much without a reset may lead to loss of function. After chaning the input frequency by more than the input specification it is recommedned to reset the DCM so it can retrain and find the right taps and re-arrange the six internal delay lines. Otherwise it may overflow, or underflow on one of the delay line tap selections (run right off the end). Austin Marlboro wrote: > Hi guys, > > In my project, I will also use DCM to derive CLKDV (1/2 clock) > but I think there may be an issue. The DCM input frequency is not fix, > actually it's configured at power up only, after that the frequency > won't change anymore. The frequency can be anything between 66 MHZ > (max) and 25 MHZ (min). At the high frequency region there's no > problem at all, but when it is lower 58 MHZ, the CLKDV will be lower > 24MHZ. Can I use the CLKFX with M=1 and D=2 instead of CLKDV? Or we > have a better solution than this? > > Many thanks,Article: 59548
Louis, I am, sadly, at the opposite end of the building from the Spartan team, and not a member of that team (-- except perhaps on an honorary basis?). I am part of the Virtex team (or so I am led to believe). So for S3 features, I would recommend reading the user's guide and data sheet (which I have not done yet). Austin louis lin wrote: > Thank you very much for your help. > Another solution is migrating from XC2S600E to Spartan-3. > I found there are eight of IBUFG in Spartan-3, right? > But how many BUFG are there in it? Same as Spartan-IIE? > Besides, is BUFGMUX output also a clock network? > > "Austin Lesea" <Austin.Lesea@xilinx.com> > : Louis, > : > : Too bad you ran out of resources, and can not change its design. > : > : I suspect that the only way to get around this is to check the timing and the routing > using > : FPGA_Editor, and hand fix any places where the timing is vilolated. > : > : More constraints may cause the design to become unroutable once you run out of resources. > : > : Austin > :Article: 59549
Don't believe everything you are being told. The flip-flops in a counter, whether synchronous or ripple, do not glitch. Maybe the warning meant to say that you should never use a decoded output as a clock, since decoders or any simialr gating structures are notorious for glitching. Your flip-flop output will be perfect. A little delayed, but absolutely glitch-free. Peter Alfke And: Thank you, Austin, for correcting my boo-boo regarding the frequency requirement. David Lamb wrote: > > Ok sounds like I should use the flip flops. I don't care about the delay, > since this clock is for other part of the circuit (outside the fpga) that > are not synchronized with anything else. However, I have always been told to > never use the output of a counter as a clock since it can glitch. This is > almost what I'm about to do... > Is there a way to avoid glitches? > Thanks > David > > "Peter Alfke" <peter@xilinx.com> wrote in message > news:3F440FD5.C1F6E488@xilinx.com... > > Go into Frequency Synthesis mode, and use M=2, D=4. > > But why? Do you need coincident edges? > > As a general rule: > > Always tell us a little more than the absolute bare-bone question... > > > > Peter Alfke > > ======================= > > David Lamb wrote: > > > > > > Actually, the DCM only works on frequency higher than 24Mhz, so I would > need > > > to double the clock in order to use it. ( I heard the DCM can do this, > but I > > > just don't see how...I can't do it in the wizard using any options > > > possible...). > > > David > > > > > > "David Lamb" <gretzteam_nospam@yahoo.com> wrote in message > > > news:bi0ufn$6nt$1@home.itg.ti.com... > > > > Hi, > > > > I have a 20Mhz external clock going in my fpga. I need to output a > 10Mhz > > > > clock for other devices. I am using a virtexII device, so I can use > the > > > DCM > > > > wizard to divide the clock by two. How is this better than using a > state > > > > machine with two states that inverts the output signal on each rising > edge > > > > of the input clock? That scheme could be used to divide the clock by > any > > > > power of two number...Why would I use the DCM for those? > > > > > > > > Thanks > > > > Dave > > > > > > > >
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