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An alternate way to bring internal FPGA signals to IOBs (mainly for debugging or track internals signal's behaviour) is to use "Add Probes" feature in FPGA Editor. This is explained in the solution record http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=6616 This is a more elegant way as you don't need to add ports in RTL or re-run PAR. This will not change timing of the oringal design. You can add probes in FPGA Editor, save the NCD file and generate a new bitstream. For more debug capabilities you can use Chipscope http://www.xilinx.com/ise/verification/chipscope_pro.htm Regards Vikram Martin Euredjian wrote: > I'm eager to learn if there's a better way to do this myself. I'll tell you > that the problem I ran into with various approaches is that bringing some > signals out actually broke the design. The culprit --I think-- had to do > with modified routing due to the monitoring path ... which created timing > problems. I finally resorted to running any signal I want to monitor > through a flip-flop clocked by the appropriate clock domain. I also had to > ensure that the IOB property for that F/F was set to FALSE in order to have > the F/F located close to the signal source and not the IOB. > > -- > ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ > Martin Euredjian > > To send private email: > 0_0_0_0_@pacbell.net > where > "0_0_0_0_" = "martineu" > > "Greg Nichols" <greg@nichols.nu> wrote in message > news:ee7ec04.0@WebX.sUN8CHnE... > Well, I surprised myself by actually figuring this one out on my own! > In order to get rid the the XST error message, I had to edit the file > C:\XILINX\verilog\src\iSE\unisim_comp.v and add these lines: > module OPAD (PAD); > input PAD; > endmodule > // synthesis attribute BOX_TYPE of OPAD is "BLACK_BOX" > To instantiate the pad, the following lines of code were necessary: > OBUF tag12_obuf (.O(TAG12), .I(Poll_Now)); > OPAD tag12_pad (.PAD(TAG12)); > // synthesis attribute loc of tag12_pad is E23; > (Poll_Now is the name of the internal signal I wanted to bring out, and > TAG12 is the name of the pad.) > I'm slightly embarrased to say that this took me about 3 hours to figure > out. Hopefully this post will save someone else some time.Article: 58326
Where can I find the Numerical Recipes?? "Glen Herrmannsfeldt" <gah@ugcs.caltech.edu> wrote in message news:eLGSa.95714$GL4.26933@rwcrnsc53... > > "Avrum" <avrum@REMOVEsympatico.ca> wrote in message > news:roBSa.539$1I5.79766@news20.bellglobal.com... > > You can do a LOT more than that at 100MHz - we have done CRC16 at 128bits > > per cycle at over 100MHz with no trouble at all (12.8Tbps) in a Virtex-II, > > slowest speed grade. For a CRC16 of 128 bits, each CRC bit is a function > of > > a subset of the 128bits coming in and the 16 CRC bits from the previous > > calculation - the most complex bit contains about half the terms (so is > the > > XOR of about 70 bits). Thus, the complete CRC calculator is 16 XOR trees > > each with less than 70 inputs. > > > > A CRC 32 would only be slightly slower, since the largest term would have > > slightly more inputs (probably closer to 78), so you would have 32 XOR > trees > > each with less than 78 inputs - it would be slower, but not much slower. > It > > would, however, consume more than twice the resources (which aren't tiny). > > The only 64 bit polynomial that I know of, (listed in Numerical Recipes if > one is interested) has very few 1's, so should be convenient for > implementing. > > -- glen > >Article: 58327
Glen Herrmannsfeldt wrote: > > "Avrum" <avrum@REMOVEsympatico.ca> wrote in message > news:roBSa.539$1I5.79766@news20.bellglobal.com... > > You can do a LOT more than that at 100MHz - we have done CRC16 at 128bits > > per cycle at over 100MHz with no trouble at all (12.8Tbps) in a Virtex-II, > > slowest speed grade. For a CRC16 of 128 bits, each CRC bit is a function > of > > a subset of the 128bits coming in and the 16 CRC bits from the previous > > calculation - the most complex bit contains about half the terms (so is > the > > XOR of about 70 bits). Thus, the complete CRC calculator is 16 XOR trees > > each with less than 70 inputs. > > > > A CRC 32 would only be slightly slower, since the largest term would have > > slightly more inputs (probably closer to 78), so you would have 32 XOR > trees > > each with less than 78 inputs - it would be slower, but not much slower. > It > > would, however, consume more than twice the resources (which aren't tiny). > > The only 64 bit polynomial that I know of, (listed in Numerical Recipes if > one is interested) has very few 1's, so should be convenient for > implementing. When you are processing more than just a few bits at once, the complexity of the calculation goes up very quickly. So to even process 32 bits at one time should require about half of the external inputs to each bit being calculated. On the positive side however, you will find that only the feedback inputs can not be pipelined. So in a CRC 32 the XOR of about 16 inputs will need to be done in one clock cycle at the CRC register. All of the external inputs may be pipelined as needed to keep the speed of the logic up. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58328
Martin, Thanks for the tip. If probing my design causes it to "break," I will give your flip-flop technique a try. Vikram, Thanks. I think the FPGA Editor method is going to work perfectly for what I need. I just tried it out, and I really like it. The best part is the fact that I wont need to recompile when changing probe points. We have been using ChipScope, with mixed results. The 20-minute recompile time made it a bit tedious. More importantly, we seemed to run into problems with speed (160 MHz) and resources (85% slice utilization and %100 BRAMs) which caused ChipScope to misbehave. ChipScope is nice, but I'm looking forward to running a benchtop logic analyzer on the chip tomorrow to see how that works out. I appreciate your responses, +GregArticle: 58329
OK, that's what I mean by fine, a nice frequency meter. For now I think I will stick to this design as it is kind of simple to implement in a small FPGA. That's true that the frequency displayed will then be 10x more that the frequency at input. What I guess they did was to add a dummy digit at the end, which was stuck to '0'. This way, it's like putting the unit to 0, giving the impression of multiplying by ten the displayed result. But then the minimum frequency measured is 10hz and for the first decade, it went upto 9,999,990 hz for the second decade 99,999,990 - 10,000,000 and the last one 399,999,990 - 100,000,000. Jacques. "Kasper Pedersen" <ngfilter@kasperkp.dk> wrote in message news:<3f1a8ff0$0$5154$edfadb0f@dread11.news.tele.dk>... > "Jacques athow" <jaxlau@yahoo.com> wrote in message > news:acc717b2.0307192037.76ec3db4@posting.google.com... > > In an attempt to create a fine frequency meter, I was drawn by a > > design from Xilinx. It was published in the Q299 32th XCELL edition > > and they describe a simple frequency meter design at RTL. My question > > is that the displayed frequency would be one that has been divided by > > 5 and gated at 0.5 S. > > As the design is to operate at 400MHz input they need a prescaler. They > get 5x from the first flipflops, which is good, but not easily readable. > The gating time is 1/2 second, and thus during the gate time they get > their decade counters incremented by 1/10 of the frequency, which IS > easily readable. > You might think that this was inaccurate, but if they are to measure > frequencies above 10MHz, this makes little difference as the oscillator > is highly unlikely to be better than 1 ppm anyway (they're running off a > watch resonator). > > > Not being a native english speaker I don't understand the expression > 'fine frequency' - I assume you want a meter you can feel proud of? > In that case, reciprocal counting is a useful mode to add, especially > for frequencies <1MHz. > You generate a window pulse of 0.1-100s, and synchronize it to the > incoming signal. Then you synchronize that to the reference oscillator. > And then you use the synced window pulses to gate a pair of counters. > Finally compute inputcounter *reffrequency*prescaler / refcounter. And > in this case the prescaler does not cause loss of resolution. > That, however, is a somewhat complicated thing to do without a > microprocessor, and wouldn't fit in the article.Article: 58330
"Jimmy Zhang" <crackeur@comcast.net> wrote in message news:8kISa.96133$OZ2.20276@rwcrnsc54... > Where can I find the Numerical Recipes?? It is a pretty popular numerical analysis book, though the original is about 20 years old now. Any CS or Engineering library should have it. Good technical bookstores will stock it. It should be available from used book web sites, too. -- glenArticle: 58331
hmurray@suespammers.org (Hal Murray) wrote in message news:<vhff8nep7oeqe1@corp.supernews.com>... > > Am new to fpga.I need help in selecting an external oscillator ( of > >50MHz) for spartan IIE XC2S50E fpga. I would like to know the > >following details for this purpose. > > >1. What are the parameters to be considered in selecting external > >crystal oscillator? > > Any constraints from your application? Accuracy? Temperature > drift? ... > > >2. Any standard crystal oscillator ckts avilable? > > Most people use one of the standard oscillator packages. (rather > that building their own circuit using a raw crystal) > > I'd expect almost any of the packages that run on 3.3 V would work. > In most cases, it's not a big deal. > > >3. How many pins I have to leave in FPGA to connect the external > >crystal oscillator ckt? > > One. Two for a differential input which might give you slightly > less jitter. Maybe more if you are using a DLL and want to sync to > an external pin. > > There are special clock-input pins. > > >4. Is there any specific documents that I can refer for this? > > How about the data sheet? I don't have the one for the -E handy, > but the Spartan II has several pages on "Using Versatile I/O". The > part on the clock inputs is on page 32 of section 2. > > Check the banking rules if you are doing something fancy. > > There is another section on clocking. Hi friends, Thank you for the information and quick response. I searched for the oscilattor pakages based on the info that u told.Some of the links that I got is given below. http://www.vanlong.com/products/oscillator.htm http://www.golledge.co.uk/docs/products/osc_ld/gxou102.htm Thank you. Bijesh Bijesh VMArticle: 58332
Hi folks, I've got reasonable hunches about the following, but can't find it in "black and white" anywhere in the docs. I'm thinking specifically about the Spartan3 and Virtex2, but expect the answers would apply for the V2Pro as well. If a pin is configured as a GCLK output, is it driven at the voltage level of that bank's VCCO? (I'm certain the answer is "yes"). Then, what is the switching threshold voltage for a GCLK input? For other IO's, the input switching voltage depends on the IO standard - VREF_# for some, and VCCO_#/2 for others (where # is the bank number), and so on. Does/can a clock input have an IO standard? Finally, are there intrinsic differential pairings for GCLKs in the same way that there are for normal IOs? e.g. IO_L05N_0 and IO_L05P_0 can form a differential IO pair if you want them to. Can two clocks be automatically paired in the same way, or do you just "force it" by driving two separate clocks 180 degrees out of phase? Thanks, JohnArticle: 58333
Hi all, Am new to fpga. I would like to know about QuickSwitch devices and whether they are ideal to interface fpga (3.3v) with devices with different (5v)logic levels.Please share your knowledge on the following questions. 1. Is it a good practice to use Quickswitch to interface (3.3v) spartan IIE fpga and (5v) logic devices? 2. Is it a commonly used approch to use Quickswitch devices with fpga? If not so what are its disadvantages? 3. Is it a recent technology? From what I read and understood is that,Quickswitches operation is in effctive to connecting a small resistance in series between the two logoc levels. I read about Quickswitch devices from the site http://www.idt.com/products/pages/Bus_Switches-QS316245.html. 4. At frequencies (say 50MHZ) whether the quickswitch devices will introduce significat delay? 5.I think bidirectional data flow capability of the quickswitch device is a very good feature( no need of additional data direction control signals)compared to other Transceiver chips (like 74LVX4245).Whats your thinking? regards BijeshArticle: 58334
louis lin <n2684172@ms17.hinet.net> wrote: :> [ chop an example of `ifdef that would be trivial in the :> traditional C programming world, but strains the capabilities :> of Xilinx's Verilog tools] :> :> > I had to "touch" the test.v to force ISE to re-scan the relationship :> > among test.v, mode0_proc.v, and mode1_proc.v. However, I have to "touch" :> > so many files in different directories if these files all contained such :> > "ifdef"... Is there any other way to solve it? :> :> I gave up on letting ISE itself deal with `ifdef. Now I run :> all my Verilog through Icarus first (iverilog -E) using a Makefile, :> and only then sic ISE on the preprocessed output. I agree the :> real problem is in the dependency generator, the synthesizer :> itself probably gets things right. :> :> - Larry :> : What is "iverilog"? A free verilog simulator: www.icarus.com Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 58335
hello,everyone,
now i work with synplify pro, and my program use 3 component as black box.
but when i synthsize it, there are 3 warning:
unbound component .. mapped to black box.
and when i use technology view, there is no
ports and instances.
I do not know what is wrong.
Any replies greatly appreciated.
thanks
zhaoke
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity test is
end test;
architecture Behavioral of test is
component ARM7 is
port ( ADR : out std_logic_vector(23 downto 0);
DAT : inout std_logic_vector(15 downto 0);
OE, WR0, CSEXT2, CSEXT3 : out std_logic
);
end component;
component OSCI is
port( CLK : out std_logic
);
end component;
component myfpga is
port( A : in std_logic_vector(23 downto 0);
D : inout std_logic_vector(15 downto 0);
OE , WR0, CSEXT2, CSEXT3 : in std_logic;
CLK : in std_logic);
end component;
signal ADRS : std_logic_vector(23 downto 0);
signal DATS : std_logic_vector(15 downto 0);
signal OES, WR0S, CSEXT2S, CSEXT3S, CLKS : std_logic;
begin
my_arm : ARM7 port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S);
my_fpga : myfpga port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S, CLKS);
my_osci : OSCI port map(CLKS);
end Behavioral;
Article: 58336Hi fellows, I am getting following error's My ucf file entry is given after this error. ERROR ____________________________________________________________________________ Checking timing specifications ... ERROR:TSDatabase:19 - Processing TIMESPEC definition "TS_CLK_2X=PERIOD "CLK_0_2XOUTDLL" 10000.000000 pS HIGH 5000.000000 pS" from UCF file: No TNM, TPSYNC or user group named "CLK_0_2XOUTDLL" is defined. ERROR:TSDatabase:19 - Processing TIMESPEC definition "TS_P2CLK2X=FROM "PADS" TO "CLK_0_2XOUTDLL" 8500.000000 pS" from UCF file: No TNM, TPSYNC or user group named "CLK_0_2XOUTDLL" is defined. ERROR:TSDatabase:19 - Processing TIMESPEC definition "TS_CLK2X2P=FROM "CLK_0_2XOUTDLL" TO "PADS" 9000.000000 pS" from UCF file: No TNM, TPSYNC or user group named "CLK_0_2XOUTDLL" is defined. Checking expanded design ... NGDBUILD Design Results Summary: Number of errors: 3 Number of warnings: 0 One or more errors were found during NGDBUILD. No NGD file will be written. Writing NGDBUILD log file "vir3_top.bld"... _______________________________________________________________________________ UCF FILE ENTRY _____________________________________________________________________________ # # Timing Constraints # # NOTE: CLK_0_OUTDLL not used in this design # #TIMESPEC "TS_CLK_0" = PERIOD "CLK_0_OUTDLL" 16 HIGH 8; TIMESPEC "TS_CLK_2X" = PERIOD "CLK_0_2XOUTDLL" 10 HIGH 5; TIMESPEC "TS_P2P" = MAXDELAY FROM "PADS" TO "PADS" 20 nS; TIMESPEC "TS_P2CLK2X" = MAXDELAY FROM "PADS" TO "CLK_0_2XOUTDLL" 8.5 nS; #TIMESPEC "TS_P2CLK0" = MAXDELAY FROM "PADS" TO "CLK_0_OUTDLL" 8.5 nS; TIMESPEC "TS_CLK2X2P" = MAXDELAY FROM "CLK_0_2XOUTDLL" TO "PADS" 9 nS; # # Pin Location Constraints # Uncomment required pins ______________________________________________________________________________ Help would be appreciated Cheers ISAACArticle: 58337
Hi does anybody know if it is possible to get old libraries and if so, from where? I am using ISE 5.1i and am trying to redo a core which uses a LogiBlox DP_RAM module originally generated in 1999. When I try to synthesise the code it cant locate the library, do I have to redo a core to try and emulate this or can I simply get hold of the Logiblox library? Thanks in advance. -- Cheers! MikeArticle: 58338
rickman <spamgoeshere4@yahoo.com> writes: > Martin Schoeberl wrote: > > > > Why is everyone talking about 0.1uF caps? Isn't it time to adjust the cap > > values to the higher speed of the logic and to avoid EMI problems. A > > standard 0.1uF cap 0805 with X7R dielectric is at resonance at 10 MHz (see > > datasheet of Kemel caps)! Above 10 MHz the impedance becomes inductive. EMI > > is measured up to 1 GHz. > > Two points I would make. > <snip - good point tho'!) > 2) If you don't like the Kemel (sp? Kemet perhaps) caps, use someone > else's caps that are rated with a higher resonance or a lower > impedance. I know that the 0.1 uF caps I use have a resonance above 50 > MHz. Perhaps you were looking at a larger package which adversely > affects the impedance more than does the cap value? 0.1 uF caps come in > 0603 packages which have very good high freq characteristics. > And don't forget that the inductance varies depending on both the cap itself, *and how it is mounted on the board*. You can raise the resonance significantly by placed the fanout vias in the pad of the cap, or even providing multiply vias per pad! Cheers, Martin -- martin.j.thompson@trw.com TRW Conekt, Solihull, UK http://www.trw.com/conektArticle: 58339
"John Williams" <jwilliams@itee.uq.edu.au> wrote in message news:bfg3k7$930$1@bunyip.cc.uq.edu.au... > Hi folks, > > I've got reasonable hunches about the following, but can't find it in > "black and white" anywhere in the docs. I'm thinking specifically about > the Spartan3 and Virtex2, but expect the answers would apply for the > V2Pro as well. > > If a pin is configured as a GCLK output, is it driven at the voltage > level of that bank's VCCO? (I'm certain the answer is "yes"). There is no such thing as a GCLK output; Xilinx's nomenclature can be a bit confusing. In the datasheets, Xilinx gives the "names" of each IO pad in the device/package. Most of these are simply IO_L###_N/P_#, which describes its position on the die. Some pins have dual functions, and hence the name reflects that. For example the pad IO_L95N_0/GCLK7P indicates that it can be a regular I/O or a "GCLK7". The term GCLK is a bit confusing - in this context, it only indicates that this pin is one of several that has special dedicated routing to some of the internal clocking structures (the inputs of the DLLs/DCMs and the BUFGs). Several types of internal components can be instantiated and mapped to this position. The type of component instantiated determines how this component will function. The instantiation of an OBUF (of any type) indicates that this is being used as an output buffer, and hence is not using any of the special clock routing. In this mode, the dual function pin functions like any other regular I/O pin in the same bank. Similarly, the instantiation of an IBUF or IOBUF indicates the same thing; this is a normal I/O that is not using any of the dedicated routing, and is the same as any other input or I/O in the same bank. In these cases it is using the IO_L###_N/P_# part of its name and not the GCLK part of its name (and hence probably shouldn't be called a GLCK). The only time the "GCLK" functionality is being used is when you instantiate or infer an IBUFG. This informs the tools that you are planning to use this pin specifically for its dedicated routing to the clocking resources (the DCMs or BUFG). This doesn't actually change the behaviour of the pad itself, only the routing of the resulting internal signal. When you instantiate an IBUFG, the tools check that the output of the IBUFG is indeed connected to a clock resource that can be reached by dedicated routing; the CLKIN or CLKFB of a DCM on the same side of the die, or the BUFG directly in line with the IBUFG (In the case of the pad listed above, that would be the BUFG named BUFGMUX7P). > > Then, what is the switching threshold voltage for a GCLK input? For > other IO's, the input switching voltage depends on the IO standard - > VREF_# for some, and VCCO_#/2 for others (where # is the bank number), > and so on. Does/can a clock input have an IO standard? Again, the nomenclature is messing you up - the switching voltage for the IBUFG in a GLCK position depends on the type of IBUFG you instantiate (or the attribute you set on the pin). Just like any other input, you can specify its I/O standard. This can be done by specifically instantiating the I/O standard you want (i.e. instantiating an IBUFG_HSTL1), or by setting the IOSTANDARD constraint in the UCF or source file. Thus, the switching voltage depends on the standard - for HSTL, SSTL, etc... it is based on the VREF of the bank, and for LVCMOS, LVTTL, etc... it is based on the VCCO of the bank. > > Finally, are there intrinsic differential pairings for GCLKs in the same > way that there are for normal IOs? e.g. IO_L05N_0 and IO_L05P_0 can > form a differential IO pair if you want them to. Can two clocks be > automatically paired in the same way, or do you just "force it" by > driving two separate clocks 180 degrees out of phase? Like all other I/Os, you can instantiate an IBUFG_LVDS just like you instantiate an IBUF_LVDS. You then have to LOC it to a GCLK position. The GLCK pins are paired with eachother - you should look at the other part of the name to determine the pairing. So IO_L95N_0/GCLK7P is paired with IO_L95P_0/GCLK6S. For an LVDS pad, you use the LOC of the P - in this case the position of GCLK6S. > > Thanks, > > John > AvrumArticle: 58340
Hi all, the error message like this : FATAL_ERROR:Map:Portability/export/Port_Main.h:116:1.17 -This application has discovered an exceptional condition from which it cannot recover.Process will terminate. To resolve this error, please consult the Answers Database... Xilinx answer to use "editbin" from msvc++ sdtudio-6.0.... but I dont have such thing..., download map.exe from xilinx still give same error. How to get around it? please...I think the error ocurs with this particular design only, I try other projects it works fine,... what's the true story about this? many thanksArticle: 58341
"bijesh v.m." wrote: > > Hi all, > > Am new to fpga. I would like to know about QuickSwitch devices and > whether they are ideal to interface fpga (3.3v) with devices with > different (5v)logic levels.Please share your knowledge on the > following questions. > > 1. Is it a good practice to use Quickswitch to interface (3.3v) > spartan IIE fpga and (5v) logic devices? That is one way of dealing with 5 volt signals. Or you can use a 5 volt tolerant FPGA in the first place. I am finding that the Altera ACEX EP1K family is a good choice also and saves board space if you have a lot of 5 volt signals to interface. > 2. Is it a commonly used approch to use Quickswitch devices with > fpga? If not so what are its disadvantages? The disadvantage is the extra board space. > 3. Is it a recent technology? No, series pass switches have been used for voltage shifting for years. > From what I read and understood is that,Quickswitches operation is in > effctive to connecting a small resistance in series between the two > logoc levels. Not exactly. They are a variable resistance where the resistance increases as the input voltage gets close to the Vdd voltage. This is because a high input voltage reduces the drive voltage which turns off the series pass transistor. So at lower voltage levels the switch is low resistance and has nearly no delay. > I read about Quickswitch devices from the site > http://www.idt.com/products/pages/Bus_Switches-QS316245.html. > > 4. At frequencies (say 50MHZ) whether the quickswitch devices will > introduce significat delay? The delay is less than a nanoSecond. These switches are almost like a wire. > 5.I think bidirectional data flow capability of the quickswitch device > is a very good feature( no need of additional data direction control > signals)compared to other Transceiver chips (like 74LVX4245).Whats > your thinking? It all depends on your application. For example, if you were adding a bunch of IO ports to control 5 volt signals from a 3 volt device then you could do better with a register since you can use a lot fewer pins on the FPGA. Adding extra registers could share the data bus and would only require adding control signals. Also keep in mind that the quick switch will not let the 3 volt device *drive* to 5 volts if that is needed. To get a signal to 5 volts you will need your low voltage driver to be open collector (drain) and a pullup to 5 volts on the output side of the switch. This will be a bit slower than a 5 volt, direct drive, totem pole output. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58342
Symon, Great idea! I will pass it along. To use a soft core is, as you point out, best, as one can tailor it to the best method of decompression! By the way, since you have disclosed this, there is nothing to prevent any of our customers from doing this, now. Heck, one could use the PPC in an amazingly complex decompression to unravel the bitstream in a virtex II pro .... Austin Symon wrote: > Hey Austin, > How about an App note/ Tech exclusive showing how to do > configuration bitstream decompression using the ICAP present in some > of your parts? The configuration stream first loads the FPGA with a > small decompression engine. This engine then decompresses the rest of > the bitstream and loads the rest of the FPGA through the ICAP. This > way, you (Xilinx) get to demonstrate partial configuration and the > ICAP. We (the customers) get a way to compress bitstreams if needed. > You're not selling a tool, it's an app note. > It also is better than a 'hard' solution, as you can update the > decompression engine as new ideas are tried. You could start with run > length encoding and add more complex stuff later. Users could develop > their own, depending on their requirements. > As mentioned on comp.arch.fpga passim, you can alter many bits > with SEUs without affecting the logic design, this would imply to me > significant compression is possible. > cheers, Syms. > > Austin Lesea <Austin.Lesea@xilinx.com> wrote in message news:<3F1462AB.B2CEE7A7@xilinx.com>... > > Nick, > > > > It is really hard to sell a tool that only works sometimes (in fact, it does more > > damage to do so, than to just not use that tool). > > > > Thus, until we have a really robust method of compression that works across > > thousands of bitstreams, we will stick to the easy method that we use now > > (suppressing unused frames from being in the .bit file). > > > > Austin > > > > "Nicholas C. Weaver" wrote: > > > > > In article <3F144161.242FBBAB@xilinx.com>, > > > Austin Lesea <Austin.Lesea@xilinx.com> wrote: > > > >Compression of bit streams.... > > > > > > > >Is a tricky business. Some bitstreams compress well, others do not compress > > > >much at all. > > > > > > Right. But compression, in the worst case, offers no savings, but in > > > the best case offers substantial savings. > > > > > > And I'd expect that there is generally a fair amount of savings, just > > > from all the switchpoints which support a fairly large amount of > > > fanout when most switches only have a small amount of fanout most of > > > the time. > > > -- > > > Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 58343
If you have Synplify Pro 7.2, you can just uncomment your lines to include
the unisim library.
If you have an older version, you can use Synplify's virtex library:
library virtex;
use virtex.components.all;
In all versions, you can add the blackbox attributes to your components:
-- These attributes are needed if virtex library not used with Synplify.
attribute syn_black_box : boolean;
attribute syn_black_box of IBUFG : component is true;
attribute syn_black_box of IBUF : component is true;
attribute syn_black_box of CLKDLL : component is true;
attribute syn_black_box of BUFG : component is true;
attribute syn_black_box of OBUF : component is true;
"zhaoke" <zhaoke@eikon.tum.de> wrote in message
news:bfg95j$je7$1@wsc10.lrz-muenchen.de...
> hello,everyone,
> now i work with synplify pro, and my program use 3 component as black box.
> but when i synthsize it, there are 3 warning:
> unbound component .. mapped to black box.
> and when i use technology view, there is no
> ports and instances.
> I do not know what is wrong.
> Any replies greatly appreciated.
> thanks
> zhaoke
>
> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> -- Uncomment the following lines to use the declarations that are
> -- provided for instantiating Xilinx primitive components.
> --library UNISIM;
> --use UNISIM.VComponents.all;
>
> entity test is
> end test;
>
> architecture Behavioral of test is
> component ARM7 is
> port ( ADR : out std_logic_vector(23 downto 0);
> DAT : inout std_logic_vector(15 downto 0);
> OE, WR0, CSEXT2, CSEXT3 : out std_logic
> );
>
> end component;
> component OSCI is
> port( CLK : out std_logic
> );
> end component;
> component myfpga is
> port( A : in std_logic_vector(23 downto 0);
> D : inout std_logic_vector(15 downto 0);
> OE , WR0, CSEXT2, CSEXT3 : in std_logic;
> CLK : in std_logic);
> end component;
> signal ADRS : std_logic_vector(23 downto 0);
> signal DATS : std_logic_vector(15 downto 0);
> signal OES, WR0S, CSEXT2S, CSEXT3S, CLKS : std_logic;
> begin
> my_arm : ARM7 port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S);
> my_fpga : myfpga port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S, CLKS);
> my_osci : OSCI port map(CLKS);
>
> end Behavioral;
>
>
>
Article: 58344
In VHDL the ports between modules can be made of basic or complex types
available in your design. So the following should be perfectly correct:
-- Code --------------------
PACKAGE MyTypes IS
TYPE RGB_Type IS
RECORD
red : STD_LOGIC;
green : STD_LOGIC;
blue : STD_LOGIC;
END RECORD RGB_Type;
END package MyTypes;
entity Test is
port (clk : in STD_LOGIC;
RGB_in : in work.MyTypes.RGB_type;
RGB_out : out work.MyTypes.RGB_type);
end entity Test;
-- End Code----------------
Unfortunately Quartus II 3.0 is not supporting this when generating a
symbol.
-- Processing messages --------------
Info: Running Quartus II Analysis & Synthesis
Info: Version 3.0 Build 199 06/26/2003 SJ Web Edition
Error: Can't create symbol for entity test -- declaration for port RGB_in
cannot be of complex type
Error: Can't create symbol for entity test -- declaration for port RGB_out
cannot be of complex type
-------------------------------------
Does anyone of you know if this is a limitation common to schematic editors
around or is it just missing in the Quartus Schematic Editor?
Another problem with the schematic editor is that it is not displaying
inital values of generics which are not of type integer. The following code
(having generics of type integer and real) works fine, but inserting the
module as a block in the schematic editor only shows the integer value, not
the real value. However this seems to be a display issue only, as far as I
have tried it, the result is still working, so the value is there (you can
change it, then it stays visible), you just don't see the inital one.
Still, not the way it should be, isn't it? I might try the Altera support
page on this :-), just to see if someone cares.
-- Code --------------------
entity Test is
generic (number1 : real := 1.25; number2 : integer := 2);
port (clk : in STD_LOGIC;
output : out STD_LOGIC);
end entity Test;
-- End Code----------------
\Manfred
--
Article: 58345The black boxes instances have been pruned because they have no fanouts to the pins of the chip. You can give them a virtual fanout using the syn_noprune attribute on the component declarations. Add attribute syn_noprune : boolean; attribute syn_noprune of ARM7 : component is true; ... Ken McElvain Synplicity, Inc. zhaoke wrote: > hello,everyone, > now i work with synplify pro, and my program use 3 component as black box. > but when i synthsize it, there are 3 warning: > unbound component .. mapped to black box. > and when i use technology view, there is no > ports and instances. > I do not know what is wrong. > Any replies greatly appreciated. > thanks > zhaoke > > library IEEE; > use IEEE.STD_LOGIC_1164.ALL; > use IEEE.STD_LOGIC_ARITH.ALL; > use IEEE.STD_LOGIC_UNSIGNED.ALL; > > -- Uncomment the following lines to use the declarations that are > -- provided for instantiating Xilinx primitive components. > --library UNISIM; > --use UNISIM.VComponents.all; > > entity test is > end test; > > architecture Behavioral of test is > component ARM7 is > port ( ADR : out std_logic_vector(23 downto 0); > DAT : inout std_logic_vector(15 downto 0); > OE, WR0, CSEXT2, CSEXT3 : out std_logic > ); > > end component; > component OSCI is > port( CLK : out std_logic > ); > end component; > component myfpga is > port( A : in std_logic_vector(23 downto 0); > D : inout std_logic_vector(15 downto 0); > OE , WR0, CSEXT2, CSEXT3 : in std_logic; > CLK : in std_logic); > end component; > signal ADRS : std_logic_vector(23 downto 0); > signal DATS : std_logic_vector(15 downto 0); > signal OES, WR0S, CSEXT2S, CSEXT3S, CLKS : std_logic; > begin > my_arm : ARM7 port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S); > my_fpga : myfpga port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S, CLKS); > my_osci : OSCI port map(CLKS); > > end Behavioral; > > >Article: 58346
The sins of the past... :-) I patented that method 26 years ago, while I was at Fairchild Semiconductor: US patent # 4 023 116, filed July 76, issued May 77. It's a neat way to reduce jitter when perfect phase adjustment is not required. Peter Alfke ========================================== Jim Granville wrote: > > If you are seriously worried about PLL/VCO sidebands, better PLL > detectors > have deliberate dead-band removal - this is extra logic that prevents > a 'flat spot' in the phase/voltage curve, that can occur in simpler > digital-state only designs. > If in this class, you should use the FPGA OP to drive an analog switch, > so the relatively noisy Vcc/Gnds do not appear on the VCO control > voltage > domain. > > -jgArticle: 58347
Hi Peter, I would like to ask if the reference design support MontaVista Linux Pro 3.0 ? Thanks very much! tk Peter Ryser wrote: > Antti, > > the EDK reference design for ML300 contains > - 1 PPC 405 > - 1 PLB DDR > - 1 PLB bus with arbiter > - 1 PLB2OPB bridge > - 1 PLB BRAM controller with 32 KB BRAM attached > - 1 OPB Uart > - 2 OPB GPIO > - 1 OPB 10/100 Ethernet (interrupt driven) > - 1 OPB IIC > - 1 OPB System ACE CF > > There is no touchscreen, PS/2, TFT, parallel port and AC97. Adding these > peripherals to the design is planned for a later release that will most > likely happen towards the end of the year. > > There is some documentation in the zip file that lists the peripherals and > explains the design. > Again, please contact your Xilinx FAE if you would like to get access to > this design. > > Thanks, > - Peter > > > > Antti Lukats wrote: > >> Peter Ryser <ryserp@xilinx.com> wrote in message >> news:<3F1846C0.776CD1F5@xilinx.com>... >> > >> > If you want to work with EDK please contact your FAE and ask him to get >> > you access to the EDK reference design for ML300. He will be able to >> > get you access to the design. >> >> Hi Peter, >> >> when we received the EDK + DDR project, I also asked to be notified >> when a better EDK ref. design will be available, and so far have not >> got any more info, could you please enlight us what additional cores >> are available in the EDK ref. design you mentioned? >> >> ASFAIK TFT and Touchscreen are not implemented (or hopefully are now?) >> I have still having trouble to get EDK to work correctly using the >> obsoleted TFT ref. design - eg. display is looking in stripes 8 pixels >> missing after 8 ok pixels - if the problem is fixed and ref design >> availabl would be greate. >> >> anttiArticle: 58348
You might be able to code up a modual with the same name and I/O and function and try to link to that. A dual port ram should be easy to recreate and the port name should be simple. Steve "Michael Nicklas" <michaeln@nospam.slayer.com> wrote in message news:bfgeuq$ljm$1$8300dec7@news.demon.co.uk... > Hi > > does anybody know if it is possible to get old libraries and if so, from > where? > > I am using ISE 5.1i and am trying to redo a core which uses a LogiBlox > DP_RAM module originally generated in 1999. When I try to synthesise the > code it cant locate the library, do I have to redo a core to try and emulate > this or can I simply get hold of the Logiblox library? > > Thanks in advance. > > -- > Cheers! > > Mike > > >Article: 58349
Hi Zhaoke easy way to do this is to put the library of black box components in your project files list (add the .vhd file that corresponds to your chip selection - can be anyones chip, synplicity supports most all of them). This will instantiate all of the black box modules that you need. Andrew zhaoke wrote: >hello,everyone, >now i work with synplify pro, and my program use 3 component as black box. >but when i synthsize it, there are 3 warning: >unbound component .. mapped to black box. >and when i use technology view, there is no >ports and instances. >I do not know what is wrong. >Any replies greatly appreciated. >thanks >zhaoke > >library IEEE; >use IEEE.STD_LOGIC_1164.ALL; >use IEEE.STD_LOGIC_ARITH.ALL; >use IEEE.STD_LOGIC_UNSIGNED.ALL; > >-- Uncomment the following lines to use the declarations that are >-- provided for instantiating Xilinx primitive components. >--library UNISIM; >--use UNISIM.VComponents.all; > >entity test is >end test; > >architecture Behavioral of test is >component ARM7 is > port ( ADR : out std_logic_vector(23 downto 0); > DAT : inout std_logic_vector(15 downto 0); > OE, WR0, CSEXT2, CSEXT3 : out std_logic > ); > >end component; >component OSCI is > port( CLK : out std_logic > ); >end component; >component myfpga is > port( A : in std_logic_vector(23 downto 0); > D : inout std_logic_vector(15 downto 0); > OE , WR0, CSEXT2, CSEXT3 : in std_logic; > CLK : in std_logic); >end component; >signal ADRS : std_logic_vector(23 downto 0); >signal DATS : std_logic_vector(15 downto 0); >signal OES, WR0S, CSEXT2S, CSEXT3S, CLKS : std_logic; >begin >my_arm : ARM7 port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S); >my_fpga : myfpga port map(ADRS, DATS, OES, WR0S, CSEXT2S, CSEXT3S, CLKS); >my_osci : OSCI port map(CLKS); > >end Behavioral; > > > >
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