Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Tom Seim <soar2morrow@yahoo.com> wrote in message news:6c71b322.0308010843.67e9a150@posting.google.com... > > in C > > count_val++ > > > > in VHDL > > count_val <= count_val + 1; > > > > You conveniently leave out all of the necessary supporting code > required to actually implement your counter. What do you mean (seriously) ? The synthesis tool deals with the details. If count_val is defined as an integer the line above is the usual way of implementing a counter. You _could_ break it up into individual bits and work out the equations for each one, but why bother? > Now let's take a little > more complex example (with ALL of required code): > > int 13 array3d [5][6][3]; // 13 bit wide array of 5*6*3 = 90 integers > int 4 i,j,k; // valid 4-bit array indices > i = 1; j = 2; k = 3; > array3d[i][j][k]++; > i++; j--; > array3d[i][j][k]--; OK, it's slightly more verbose in VHDL, and I'm not sure if any synthesis tools support it but .... (Note this is off the top of my head and un-checked) type array_typ is array(1 to 5,1 to 6,1 to 3) of std_logic_vector(12 downto 0); signal array_3d : array_typ; signal i,j,k : integer range 1 to 8; . . i <= 1; j <= 2; k <= 3; array_3d(i,j,k) <= array_3d(i,j,k) + '1'; i <= i - 1; j <= j - 1; array_3d(i,j,k) <= array_3d(i,j,k) - '1'; VHDL can abstract the implementation pretty well too, the critisism should be with the Synthesis tool vendors. I suppose implementing this sort of structure is where HandelC wins, it would be interesting to see what sort of a job it does (speed and size wise) against a hardware engineer's implementation in VHDL. > > It would be interesting to see a comparison of the devices needed to > > implement a fairly complex function (SDH/Sonet TU11 -> STM1 device) > > when designed in HandelC and an HDL, and the corresponding development > > times. > > Celoxica does have some case studies on their web site: > > http://www.celoxica.com/technical_library/case_studies/default.asp Aye, I should have said 'independant' comparison. Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design www.nialstewartdevelopments.co.ukArticle: 58876
"Kolja Sulimma" <news@sulimma.de> ha scritto nel messaggio news:b890a7a.0307310821.4bbe0c89@posting.google.com... > A few weeks ago I send out a request for quotes for 100 > pieves XC2S200 > to all european xilinx distributors and got a single > response! You are so damn right, same problem here in Italy. :( I gave up some time ago, now I buy Xilinx parts from Digikey for the prototypes, and I let the assembliers buy them for the production. I wonder why Xilinx doesn't have a WebShop where you can buy anything... why only the CPLDs? And why it doesn't provide a direct samples service like other big companies? Each time I ask my distributor for a sample is a pain in the ass, I never know when (or if) it will arrive. -- LorenzoArticle: 58877
But you are considering the Altera EP1C3 or the Actel APA150. Very hasty comparison : - dedicated flip flops : EP1C3 = 2910, APA150 = 0 (well, 6000), FPSLIC = 2800 - ram bits : EP1C3 = 60K, APA150 = 36K, FPSLIC = 128K (?) Just to say the FPSLIC doesn't seem that small. Don't know how efficient the architecture is though. Just a note : the AVR core and peripherals are not implemented in the FPGA, they are on dedicated silicon. So they are not wasting any space. But of course it depends on the applications you have in mind. If you didn't plan to have a microcontroller core, then this is not the device you're looking for. Otherwise the device seems like a good idea, but didn't hear of many people using it though. As Rickman mentioned, fear of it being cancelled after a few years may have to do with this. Regards, Marc "Rob Judd" <judd@ob-wan.com> wrote in message news:3F2D5868.C49B912E@ob-wan.com... > 40K gates is way too small for anything I'm considering, and the "added > value" stuff just wastes internal space. We all know where to find AVR > core and serial if we want it. > > Rob > > > Marc Van Riet wrote: > > > > Anyone any experience with the FPSLIC devices ? They have several packages > > with low pin count (84 PLCC, 100 VQFP, 144 TQFP). Only up to 40Kgates FPGA > > (2800 registers), but you do have a processor core, and several peripherals, > > and 32Kbytes + 16 Kbytes of memory already built-in. > > > > Marc > >Article: 58878
On 2 Aug 2003 12:28:58 -0700, sandeep_babel@yahoo.com (Sandeep) wrote:
>Hello everyone,
>
>
>I am new in this field.. i just wanted to ask which development boards
>will be best suited for starters.. are there any sites that gives a
>comparison of the different development kits from the different
>vendors, and some cheap distributor of these kits in the US.
>Also wanted to know abt some projects for beginners in fpga design..
>please suggest me some and the associated reading that i will have to
>do with them.
>
>thnks a lot in advance,
>
>-- sandeep
Have a look at:
http://www.fpga-faq.com/FPGA_Boards.htm
===================
Philip Freidin
philip@fliptronics.com
Host for WWW.FPGA-FAQ.COM
Article: 58879I would like to contribute a multi-cycle (slow, but area-compact) (Hehe, someone else already released a pipelined integer-divider, to the opencores.org repository. Gence I'm marketing my divider as 'compact'!) I am reading through the FAQ, and one part has me a bit confused... === The 'licensing' portion -- I understand that the 'GPL' license is fairly restrictive in that it forces derivative works to be distributed in documented *AND* modifiable form. My goal is to let *anyone* use my integer-divider as they see fit. If they want to use it in a closed commercial project, that's fine. It seems like a GPL-release cannot be used in a closed project, is that correct? So under which license should I release my divider? LGPL, BSD, etc.?!? ... Also, is Xilinx Webpack 5.1ISE the final version that will run under Win98se (no flames please)? The newer versions refuse to install.Article: 58880
Pacbell User wrote: > [snip] > Also, is Xilinx Webpack 5.1ISE the final version that will run > under Win98se (no flames please)? The newer versions refuse to install. The release notes for the licensed version of ISE 5.1 say win2k or higher is required. The Webpack might have different requirements but I'd be very surprised. -- Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer Marmot Engineering . . . . . . . VHDL, ASICs, FPGAs, embedded systems Vancouver, BC, Canada . . . . . . . . . . . http://www.marmot-eng.comArticle: 58881
Rich, do you happen to live in SF bayarea? If so could you email me using address of this posting? I am looking for some help on FPGA. Thanks, Jimmy Zhang "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F2D3614.AD21FDEF@yahoo.com... > zhengyu wrote: > > > > I've got two quick question. I don't have FPGA yet, but I want someone to > > offer me some quick comments > > > > 1. I have got to do some 64 bit integer comparison, actually I have to do up > > to 64 comparisons at the same time, the output is whether there is any pair > > that equals. > > This is not a question... :) > > Equality compares are easy. It uses a two input XOR for each bit with > all the results being OR'd together. This will take 32 LUTs for the XOR > and the first OR gate and 11 more LUTs to combine the rest for a total > of 43 LUTs in four levels. If the design uses the "special" features > that most chips have (ORing of LUTs within a CLB), you can use the LUTs > in pairs or even groups of four and reduce the number of levels for > speed. > > > > 2. If I want to create an 16 bit address space, that would translate to 512 > > k bits, does Vertex II give enough > > block RAM so I don't have to use SRAM to do that? What kind of latency > > performance should I expect from > > typical SRAM, is 5ns read access reasonable?? what is the performance of > > block ram?? > > Is that 16 bit address (64k words) of 8 bit words? Because 64k x 8 = > 512K. > > You can get this much RAM in the VirtexII if you use the XC2V500 part. > Or in the new Spartan3 you could use a XC3S1500. I am not sure which > will be cheaper, but I bet it is the Spartan3. > > The speed of the block RAM will be much faster than anything external to > the FPGA. The block ram will be synchronous and lends itself well to > pipelined operations. > > A lot of how you design will be implemented will depend on your data > flow which you have said nothing about. Think about how the storage > will be orgainized and accessed. Obviously one large block of memory > with one interface will not let you do 64 compares at one time. If you > rate of performing these compares is not fast, you can use one compare > logic block and run the different data through it sequentially. Then > one memory could easily do the job. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58882
Cypress is anyway getting out of the PLD business... http://www.eet.com/semi/news/OEG20030730S0063 "rickman" <spamgoeshere4@yahoo.com> wrote in message news:3F2A84FE.20106575@yahoo.com... > Marc Randolph wrote: > > > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3F29C212.EC74896B@yahoo.com>... > > > I have been given a very good price on the Coolrunner XCR3512XL, but > > > even with 512 macrocells, including small FIFOs (8 bits x 16 words, two > > > FIFOs) uses up half the chip. > > ^^^^^^^^^^^^^ > > Unless the design is complete and you can verify that it fits AND you > > have a pinout, this would scare the hell out of me. I have to admit > > not having used the Coolrunnner, but over the past six years, we have > > had an absolutely horrible time making very minor changes to > > moderately full 95xxx series Xilinx CPLD's. Again, this may not apply > > as much to the Coolrunner, since it is a completely different family - > > but I'd still verify it first. > > > > I agree with the other poster - what about the Cypress or Lattice > > devices? I realize that gets you away from your "all Xilinx" board, > > but is there really a good reason for desiring that (except maybe you > > can get all parts from one distributor)? > > No, sticking with Xilinx is not a strong desire since the software is > not common anyway. But Lattice has nothing that will fit this socket > and I have not been able to get a decent price on a Cypress part. I > guess that is also part of my goal to use Xilinx. I have gotten some > really great pricing on the parts I have discussed with them. They are > working with me, so it makes me want to work with them. > > But I agree that using the XCR3512XL is scaring me as well. That is why > I am asking about other Xilinx alternatives. > > I am sure I looked at the Cypress parts. I need about 170+ IOs in a 256 > FBGA. The insides are not real important since that many IOs almost > always means a larger part than what I need, say 20,000 gates or 1000 > LUT/FF. The memory is optional since with that many FFs I can make my > own FIFOs easily. Any idea of what a real price in a Cypress part would > run? I don't really see much that will fit the socket unless I am > missing something. > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58883
Hi all, I'm doing prototyping for ASICs. Before I start my work, I have to estimate the gates the FPGA or CPLD would use. I know it's hard to get a precise result. I just want some common answer, 1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just logic) Please tell me your experience. Thanks, JayArticle: 58884
Lorenzo Lutti wrote: > > "Kolja Sulimma" <news@sulimma.de> ha scritto nel messaggio > news:b890a7a.0307310821.4bbe0c89@posting.google.com... > > > A few weeks ago I send out a request for quotes for 100 > > pieves XC2S200 > > to all european xilinx distributors and got a single > > response! > > You are so damn right, same problem here in Italy. :( I gave up some > time ago, now I buy Xilinx parts from Digikey for the prototypes, and I > let the assembliers buy them for the production. > > I wonder why Xilinx doesn't have a WebShop where you can buy anything... > why only the CPLDs? And why it doesn't provide a direct samples service > like other big companies? Each time I ask my distributor for a sample is > a pain in the ass, I never know when (or if) it will arrive. If you are getting free Xilinx samples you are doing better than in the US. Xilinx does not sample FPGAs in the US and I have never gotten a disti to sample one either. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58885
What kind of gates - If you are running standard cell type ASIC, then the vendor can give you a good idea. If it's a semi custom, you can figure about 40 transistors for most standard logic gates and flops, but you'll have to build your own and steer the currents with the available resistors. Are there mapped cells (i.e. cells that are fixed in your target ASIC)? Are there dedicated I/O flops, are there clock specific mask layers? You need the architecture of your target ASIC to get a good idea of this ratio, and the architecture of your FPGA -Actel SX and SXA can get pretty close to 1:1 for some types of ASICs, old PAL based CPLD structures are dependent on what they call a gate, most others are in between somewhere. Andrew Jay wrote: >Hi all, > >I'm doing prototyping for ASICs. Before I start my work, I have to estimate >the gates the FPGA or CPLD would use. >I know it's hard to get a precise result. I just want some common answer, >1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just >logic) >Please tell me your experience. > >Thanks, >Jay > > > >Article: 58886
Mike Treseler wrote: > > rickman wrote: > > . . . > > differently and reaches the end of the process. At the top of this > > process, it waits for the "Start" signal again, but if the "Start" flag > > is already set, it hangs. > > > > So does a wait statement always perform an edge detect by default? > > No. > You can wait UNTIL an expression has a value of true or > you can wait ON a signal_id for *any* value change. > > > Here is my wait statement... > > wait until ARM_Bus_Start or rising_edge(Reset); > > If ARM_Bus_Start is already set when this executes, the process hangs > > here. > > Consider View, Source > and setting some breakpoints. > Run/step code and watch the signals. > > Either the wait is in a different process > or ARM_Bus_Start is not true at the right time. I did look at everything in detail in the simulator. The wait statement shown above executes with ARM_Bus_Start set to true and the process is hung at that wait. I have solved the problem by testing ARM_Bus_Start before I execute the wait and it runs as expected. So it is pretty clear that the issue is the wait requiring a change in state of a signal in the expression before it evaluates the expression. I will try some more tests when I get a chance. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 58887
Thanks for your response. To simplify the case, just suppose that I have a 5k gate array ASIC designs (general logic for control and interface)to implement to one CPLD(may be CoolRunnerII) What's the relationship between the ASIC gate array and CPLD macrocells? "Andrew Paule" <lsboogy@qwest.net> ??????:ynlXa.981$h_3.65136@news.uswest.net... > What kind of gates - If you are running standard cell type ASIC, then > the vendor can give you a good idea. If it's a semi custom, you can > figure about 40 transistors for most standard logic gates and flops, but > you'll have to build your own and steer the currents with the available > resistors. > > Are there mapped cells (i.e. cells that are fixed in your target ASIC)? > Are there dedicated I/O flops, are there clock specific mask layers? > You need the architecture of your target ASIC to get a good idea of this > ratio, and the architecture of your FPGA -Actel SX and SXA can get > pretty close to 1:1 for some types of ASICs, old PAL based CPLD > structures are dependent on what they call a gate, most others are in > between somewhere. > > Andrew > Jay wrote: > > >Hi all, > > > >I'm doing prototyping for ASICs. Before I start my work, I have to estimate > >the gates the FPGA or CPLD would use. > >I know it's hard to get a precise result. I just want some common answer, > >1:3 between ASIC and FPGA/CPLD gate count?(not consider the memory, just > >logic) > >Please tell me your experience. > > > >Thanks, > >Jay > > > > > > > > >Article: 58888
"Pacbell User" <dont_reply@dont_reply.com> wrote in message news:<sSgXa.472$gC7.418@newssvr23.news.prodigy.com>... > I would like to contribute a multi-cycle (slow, but area-compact) > (Hehe, someone else already released a pipelined integer-divider, > to the opencores.org repository. Gence I'm marketing my divider as'compact'!) > I am reading through the FAQ, and one part has me a bit confused... could I have a sneak preview of your divider ? (I want violate the license, whatever you will choose later) and you are right about licensing (that is confusing) GPL is what people think 'free' but in some way its more restrictive than commercial licenses. anttiArticle: 58889
Does it mean that figure 6. in xapp139 (Device configuration flow diagramm) has error? The "Reconfigure path" trough "Shundown sequence" is available or not? under "shutdown sequence" i mean the process described on p14 XAPP139 [ from XAPP139 1. Load the CFG_IN instruction into the JTAG instruction register. Next, go to the SHIFT-DR .... COR (Configuration Option Register) with the SHUTDOWN bit = 1 .... ] the described process does not need access to PROG -------------------- Thanks. Sergey.Article: 58890
> 1. iMPACT doesn't do this quite easily. You can use the debug bitstream > functionality and start shifting data in with the appropriate JTAG > instructions. I did not understand which way one can debug bitstream? Is there tool in ISE5 toolchein to do this? Or third party or selfmade software should be used? Thanks. Sergey.Article: 58891
> 1. iMPACT doesn't do this quite easily. You can use the debug bitstream > functionality and start shifting data in with the appropriate JTAG > instructions. I am sorry for my verbosity. Let me explain. I did find "TAP debug" dialog in iMPACT. But it is extremely dificult and time-consuming to enter commands bit-by-bit. Is there a way to perform the comands in batch mode or place them into bitstream file? In my prev. message i ask about tools doing this. BR, Sergey Yemets Samsung Software Center (Moscow Branch Office)Article: 58892
I have a querry regarding CPLD, we are using. It is XC9536XL and XC9572TQ100 Xilinx CPLDs. I tried to develop a simple divide by two scheme, with a T flip flop, with T pin tied high and clock given to flip flop through one of the global clock I/O pins of CPLD. It is expected to get pulses of half the frequency at Q output of the flip flop, with Q output toggling at every positive edge of clock. However, I get some pulses of continually varying frequency at the output pin. The devices I used are, XILINX WEBPACK ISE 4.2 as HDL editor, Impact tool for program download. Kindly guide me as to the possible sources this ambiguity.Article: 58893
Marc, Looking at the AT94K05AL right now ... 5K usable gates, 20K SRAM. EP1C6 (a better comparison) - 6K LE's (registers), 92K ram APA150 - 150K gates, 6K registers, 36K ram Add to that the need for an expensive IAR compiler for the AVR core and it's pretty average. It's difficult to do a meaningful feature comparison though, owing to the different architectures. I do know that the EP1C6 and APA150 are very similar in price (when the config chip is added into the equation). May check out the Atmel too, just to be sure I'm not missing out on any bargains. Rob Marc Van Riet wrote: > > But you are considering the Altera EP1C3 or the Actel APA150. Very hasty > comparison : > - dedicated flip flops : EP1C3 = 2910, APA150 = 0 (well, 6000), FPSLIC = > 2800 > - ram bits : EP1C3 = 60K, APA150 = 36K, FPSLIC = 128K (?) > Just to say the FPSLIC doesn't seem that small. Don't know how efficient > the architecture is though. > > Just a note : the AVR core and peripherals are not implemented in the FPGA, > they are on dedicated silicon. So they are not wasting any space. > > But of course it depends on the applications you have in mind. If you > didn't plan to have a microcontroller core, then this is not the device > you're looking for. Otherwise the device seems like a good idea, but didn't > hear of many people using it though. As Rickman mentioned, fear of it being > cancelled after a few years may have to do with this. > > Regards, > Marc > > "Rob Judd" <judd@ob-wan.com> wrote in message > news:3F2D5868.C49B912E@ob-wan.com... > > 40K gates is way too small for anything I'm considering, and the "added > > value" stuff just wastes internal space. We all know where to find AVR > > core and serial if we want it. > > > > Rob > > > > > > Marc Van Riet wrote: > > > > > > Anyone any experience with the FPSLIC devices ? They have several > packages > > > with low pin count (84 PLCC, 100 VQFP, 144 TQFP). Only up to 40Kgates > FPGA > > > (2800 registers), but you do have a processor core, and several > peripherals, > > > and 32Kbytes + 16 Kbytes of memory already built-in. > > > > > > Marc > > >Article: 58894
PU, You can use the IBM opensource license, the Mozilla license, the BSD license, the iMatix Xitami license, anything you want. Personally, I'd just leave any licensing off it, retain copyright and add a notice saying "Do as thou wilt". It's less troublem, and as soon as it hits the net some bozo will slap a GNU license on it anyhow. Rob Pacbell User wrote: > > I would like to contribute a multi-cycle (slow, but area-compact) > (Hehe, someone else already released a pipelined integer-divider, > to the opencores.org repository. Gence I'm marketing my divider as > 'compact'!) > I am reading through the FAQ, and one part has me a bit confused... > > === > > The 'licensing' portion -- I understand that the 'GPL' license > is fairly restrictive in that it forces derivative works to be > distributed in documented *AND* modifiable form. > > My goal is to let *anyone* use my integer-divider as they see > fit. If they want to use it in a closed commercial project, that's > fine. It seems like a GPL-release cannot be used in a closed > project, is that correct? > > So under which license should I release my divider? LGPL, BSD, etc.?!? > > ... > > Also, is Xilinx Webpack 5.1ISE the final version that will run > under Win98se (no flames please)? The newer versions refuse to install.Article: 58895
On Sun, 03 Aug 2003 23:11:50 +0000, Philip Freidin wrote:
> On 2 Aug 2003 12:28:58 -0700, sandeep_babel@yahoo.com (Sandeep) wrote:
>>Hello everyone,
>>
>>
>>I am new in this field.. i just wanted to ask which development boards
>>will be best suited for starters.. are there any sites that gives a
>>comparison of the different development kits from the different
>>vendors, and some cheap distributor of these kits in the US.
>>Also wanted to know abt some projects for beginners in fpga design..
>>please suggest me some and the associated reading that i will have to
>>do with them.
>>
>>thnks a lot in advance,
>>
>>-- sandeep
>
> Have a look at:
>
>
> http://www.fpga-faq.com/FPGA_Boards.htm
>
Actually, that's:
http://www.fpga-faq.com/FPGA_Boards.shtml
>
> ===================
> Philip Freidin
> philip@fliptronics.com
> Host for WWW.FPGA-FAQ.COM
Article: 58896rickman wrote: > Here is my wait statement... > > wait until ARM_Bus_Start or rising_edge(Reset); > > If ARM_Bus_Start is already set when this executes, the process hangs > here. > > I am using ModelSim XE II/Starter 5.6e. > Suggestion: if (ARM_Bus_Start) then -- continue immediately else -- note: removed rising_edge because it is implied in the 'wait until' wait until ARM_Bus_Start or Reset; endif; Your problem is that you should remember that a wait statement in VHDL will always wait for some event. In your situation, you don't want to wait at all when the condition is already met. Regards, RienkArticle: 58897
BSD licencense is popular, but the original had some problems see: http://www.gnu.org/philosophy/bsd.html So get a copy of the 'new' version or state it like suggested 'revised BSD license'. Martin -- -------------------------------------------------------- JOP - a Java Processor core for FPGAs now on Cyclone: http://www.jopdesign.com/cyclone/ "Pacbell User" <dont_reply@dont_reply.com> schrieb im Newsbeitrag news:sSgXa.472$gC7.418@newssvr23.news.prodigy.com... > I would like to contribute a multi-cycle (slow, but area-compact) > (Hehe, someone else already released a pipelined integer-divider, > to the opencores.org repository. Gence I'm marketing my divider as > 'compact'!) > I am reading through the FAQ, and one part has me a bit confused... > > === > > The 'licensing' portion -- I understand that the 'GPL' license > is fairly restrictive in that it forces derivative works to be > distributed in documented *AND* modifiable form. > > My goal is to let *anyone* use my integer-divider as they see > fit. If they want to use it in a closed commercial project, that's > fine. It seems like a GPL-release cannot be used in a closed > project, is that correct? > > So under which license should I release my divider? LGPL, BSD, etc.?!? > > ... > > Also, is Xilinx Webpack 5.1ISE the final version that will run > under Win98se (no flames please)? The newer versions refuse to install. > >Article: 58898
Neeraj Varma wrote: > > Cypress is anyway getting out of the PLD business... > http://www.eet.com/semi/news/OEG20030730S0063 Nearly. They ARE getting out of SPLD, and older process CPLD devices. -jgArticle: 58899
Jon Elson wrote: > > > Yves Deweerdt wrote: > >> Hello all, >> >> I would like to reuse a 14 inch TFT screen of a IBM T21 laptop, this >> LCD panel is a HT14X14-101. >> But I can't find any information about the pinout of the connector, or >> what protocol I should use to drive this screen. >> >> Can anyone give me information on how to use this kind of screen? > > > Does the laptop still work? Do you have a logic analyzer? If so, you > can probe the signals and find out how the screen image is encoded > and serialized for the display. Generally, the colors are all mixed > together (rgbrgbrgb) in a serial stream, but the stream may be sent > in blocks of 4 bits. Often the top half and bottom half of the screen > is sent separately to the drivers above and below the board. > There are a couple of sync lines and a pixel clock. there are also > several analog (contrast) and power lines, which may have voltages > generated in the controller board in the laptop. > > Jon The laptop won't boot any more, but it still prints an error message at boot time, so I guess it is possible to put a logic analyzer on it, but I don't have one. Thanks for the suggestion! Yves
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z