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Messages from 66825

Article: 66825
Subject: Re: SmartMedia writer (implments using VHDL)....
From: "p" <chaosdynasty@hotmail.com>
Date: Fri, 27 Feb 2004 03:21:31 GMT
Links: << >>  << T >>  << A >>
Hi,

www.sfu.ca/~pyuan/sm/

enjoy!

All the doc are free. But you need to register in the SSFDC forum to get
them. So I will save everybody the trouble...


"Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message
news:1077817576.568943@news-01.evisp.enertel.nl...
> On a sunny day (Thu, 26 Feb 2004 09:59:07 GMT) it happened "p"
> <chaosdynasty@hotmail.com> wrote in <Lrj%b.619427$X%5.315413@pd7tw2no>:
>
> >By the way, if anyone wants the SM specifications, I can put them on my
site
> >for download
> Yes please.
> JP



Article: 66826
Subject: Re: Stratix 2 ALUT architecture patented ?
From: kempaj@yahoo.com (Jesse Kempa)
Date: 26 Feb 2004 19:21:36 -0800
Links: << >>  << T >>  << A >>
nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver) wrote in message news:<c1lb97$5uc$1@agate.berkeley.edu>...
> In article <103s244a4ugb899@news.supernews.com>,
> Kenneth Land <kland1@neuralog1.com1> wrote:
> >Austin,
> >
> >I agree that performance claims will have to wait, but Jesse Kempa posted
> >the LE results for a Nios softcore on Stratix I vs. II.  The numbers showed
> >just north of 30% fewer LE's used.
> 
> Considering the impressive design mapping required in the NIOS 2 (the
> FPGA talk on the subject was VERY-cool), how much redesign was
> done/needed for Stratix II?  Or is this Nios 1.1?

Just to prevent any confusion (on the Nios stuff): I am assuming by
"NIOS 2" you mean "Nios II", which is a new product that has been
announced as part of Altera's 2004 new product line-up, but has not
yet been released... all I can say about this is to please be patient.

Nios "I" versions up to this point (1.0, 1.1, 2.0... up to the
just-released v3.2) have been more-or-less an evolution on the
original processor & instruction set introduced with Nios >3 years
ago. Probably the most significant amount of architecture-specific
optimization went into Nios targeting the Apex FPGA family.

While there are architecture tweaks here and there, the CPU remains
largely unchanged between Stratix & Stratix II... but don't take my
word for it, generate the respective CPUs and diff the HDL! Really the
magic behind all of this is in Quartus with synthesis & fitting
optimizations for each device architecture.


Jesse Kempa 
Altera Corp.
jkempa at altera dot com

Article: 66827
Subject: Question: size of Stratix??
From: Jian Liang <jliang@snoopy.ecs.umass.edu>
Date: 26 Feb 2004 22:46:14 -0500
Links: << >>  << T >>  << A >>
  I am looking for the die size of Stratix EP1s10 FPGA. It will be highly appreciated if anybody can give me a hint where to find such information. Any number in terms of mm^2, lamda, transistor count or gate count will be fine. I have checked the data sheet but could not find any.

Thanks for care!
Please reply to my email: jliang@ecs.umass.edu



Article: 66828
Subject: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
From: ramntn@yahoo.com (ram)
Date: 26 Feb 2004 19:56:55 -0800
Links: << >>  << T >>  << A >>
Try using a  pullup for HALTNEG and TRSTNEG in xilinx constraints editor tool
Ram

"Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message

 news:<c1l0tn$6mi$1@sunnews.cern.ch>...
> Hi,
> I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
> programming succeeded, the done pin remains low and all the outputs remain
> High.
> I have 8 V2P7s in parallel and they all the drive the same DONE line.
> What happens when we just program one of the 8 devices with JTAG in such a
> setup ?
> PLEASE HELP !!!
> Thanks in advance,
> Adarsh

Article: 66829
Subject: Re: SmartMedia writer (implments using VHDL)....
From: hamilton <hamilton@deminsional.com>
Date: Thu, 26 Feb 2004 22:03:59 -0700
Links: << >>  << T >>  << A >>
comments embedded

p wrote:
> Hi guys,
> 
> thanks for your input
> 
> I did spend a lot of time studying the SM FAT12 implmentation (<8 mb = FAT
> 12). Theoretically, the sequentially step would be
> 
> 1. set address to the 1st sector, the FAT area
	The 1st sector is NOT the FAT area
> 2. write the filename, attribute, extension, etc. to FAT
	These things go into the directory area not the FAT area
> 3. set address to the root directory sector
> 4. write the filepath to the root directory
	Huugh, I don't understand what this means.
> 5. set address to the 2nd sector, the data area
	The 2nd sector is NOT the data area
> 6. stream the data, compute the total number of bytes written
	You can only write 512 bytes at a time, no streaming
> 7. jump back to the FAT area and add the length value
	The length does NOT go into the FAT area.


	I am sorry, you do not understand how FAT file systems work.

	Google is your friend. Here, I'll help you out:
	<http://www.google.com/search?hl=en&ie=UTF-8&oe=UTF-8&q=fat12&btnG=Google+Search>

	Links I have used to decode FAT files are on this list.

	Good Luck


Article: 66830
Subject: Re: Question: size of Stratix??
From: marise <m_ramsaran@hotmail.com>
Date: Thu, 26 Feb 2004 21:05:09 -0800
Links: << >>  << T >>  << A >>
I ran the testbench as shown below 
and even though it seems to be a simple piece of code ,I keep getting errors 
for the syntax particularly opening files and closing them for reading or writing. 
I am using 3.1i Foundation Xilinx with Synopsys synthesis tools.Apparently the textio 
package is for simulation only and was advised to use "synthesis on/off" 
The code is as follows 
library ieee; 
use ieee.std_logic_1164.all; 

library ieee; 
USE IEEE.STD_LOGIC_TEXTIO.ALL; 
use std.textio.all 

entity testbench is 
generic( 
        vwidth : INTEGER := 8); 

end testbench; 

architecture TB_ARCHITECTURE of testbench is 
component window_9 
generic( 
vwidth : INTEGER := 8 
 ); 

port( 
        Clk: in STD_LOGIC; 
        RSTn: in STD_LOGIC; 
        D: in std_logic_vector (vwidth-1 downto 0); 
        w11: out std_logic_vector(vwidth-1 downto 0); 
        w12: out std_logic_vector(vwidth-1 downto 0); 
        w13: out std_logic_vector(vwidth-1 downto 0); 
        w21: out std_logic_vector(vwidth-1 downto 0); 
        w22: out std_logic_vector(vwidth-1 downto 0); 
        w23: out std_logic_vector(vwidth-1 downto 0); 
        w31: out std_logic_vector(vwidth-1 downto 0); 
        w32: out std_logic_vector(vwidth-1 downto 0); 
        w33: out std_logic_vector(vwidth-1 downto 0); 
        DV: out STD_LOGIC 
    ); 
end component; 

signal Clk: STD_LOGIC; 
 signal RSTn: STD_LOGIC; 
signal D: std_logic_vector(vwidth-1 downto 0); 
signal w11: std_logic_vector(vwidth-1 downto 0); 
 signal w12: std_logic_vector(vwidth-1 downto 0); 
 signal w13: std_logic_vector(vwidth-1 downto 0); 
signal w21: std_logic_vector(vwidth-1 downto 0); 
signal w22: std_logic_vector(vwidth-1 downto 0); 
 signal w23: std_logic_vector(vwidth-1 downto 0); 
signal w31: std_logic_vector(vwidth-1 downto 0); 
signal w32: std_logic_vector(vwidth-1 downto 0); 
 signal w33: std_logic_vector(vwidth-1 downto 0); 
signal DV: STD_LOGIC; 

begin 

UUT : window_9 
      port map 
     ( 
        Clk=>Clk, 
        RSTn=>RSTn, 
        D=>D, 
        w11=>w11, 
        w12=>w12, 
        w13=>w13, 
        w21=>w21, 
        w22=>w22, 
        w23=>w23, 
        w31=>w31, 
        w32=>w32, 
        w33=>w33, 
        DV=>DV ); 


read_from_file: process(Clk) 
variable indata_line: line; 
variable indata: integer; 

file input_data_file: text open read_mode is "lena.bin"; 
--file input_data_file: text is in "A:/lena.bin"; 
begin 
if rising_edge(Clk) then 
readline(input_data_file,indata_line); 
read(indata_line,indata); 
D <= conv_std_logic_vector(indata,8); 
if endfile(input_data_file) then 
report "end of file -- looping back to start of file"; 
file_close(input_data_file); 
--return; 
--file input_data_file: text is in "A:/lena.bin"; 
file_open(input_data_file,"lena.bin"); 
end if; 
end if; 
end process; 
write_to_file: process(Clk) 
variable outdata_line: line; 
variable outdata: integer:=0; 
file output_data_file: text open write_mode is "vhdl_output.bin"; 
--file output_data_file:text is out "vhdl_output.bin"; 
begin 
if rising_edge(Clk) then 
outdata := CONV_INTEGER(unsigned(w11)); 
if DV = '1' then 
write(outdata_line,outdata); 
writeline(output_data_file,outdata_line); 
end if; 
end if; 
end process; 

clock_gen: process 
begin 
Clk <= '0'; 
wait for 5 ns; 
Clk <= '1'; 
wait for 5 ns; 
end process; 
reset_gen: process 
begin 
RSTn <= '0'; 
wait for 10 ns; 
RSTn <= '1'; 
wait; 
end process; 
end TB_ARCHITECTURE; 
--synopsys translate_off 

configuration cfg_TESTBENCH_WINDOW9 of testbench is 
    for TB_ARCHITECTURE 
    for all : window_9 
    use configuration work.cfg_window_9; 
    end for; 
end for; 
  end configuration cfg_TESTBENCH_WINDOW9 ; 
  --synopsys translate_on 




Article: 66831
Subject: Re: Dual-stack (Forth) processors
From: "Martin Euredjian" <0_0_0_0_@pacbell.net>
Date: Fri, 27 Feb 2004 06:08:27 GMT
Links: << >>  << T >>  << A >>
John M. Drake wrote:

> > Have you consider just doing it the FPGA way?  I haven't stopped to
think
> > about what's required but you can certainly create building blocks in
> > hardware (say, filters).
>
> I wasn't aware that the "FPGA way" and a Forth processor were mutually
> exclusive.

Neither am I.  :-)

But, seriously, there are a lot of things that you cannot do with a
sequential processor, Forth or otherwise.  Example:  32 tap FIR filter
running at 150MHz, one result per clock.  What you can do is have a little
Forth (or whatever) processor within the FPGA that loads coefficients into
that filter.  That's what I implied by the "FPGA way":  Use the high-speed
capabilities of FPGA's to develop custom processing sub-blocks that a Forth
(or something else) processor can then pull strings on.  This in contrast to
insisting that everything be done with a Forth machine just out of
attachment to the language (note that the OP is not suggesting that at all).


-- 
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Martin Euredjian

To send private email:
0_0_0_0_@pacbell.net
where
"0_0_0_0_"  =  "martineu"



Article: 66832
Subject: Re: DPRAM issue
From: Tim Hubberstey <bogus@bogusname.com>
Date: Fri, 27 Feb 2004 07:55:45 GMT
Links: << >>  << T >>  << A >>
ian wrote:
> 
> I am using a DPRAM with data bus width of 32 bits on both sides of the
> RAM. However, the input data at A side is 16 bits. So in order to send
> 32 bits of data to fill one address of the RAM, I need to use a mux
> and introduce a clock cycle of latency into the writing process at A
> side. The problems is that mux logic is not scan insertable and the
> extra clock cycle latency is not welcome either. So my question is: is
> there any nice and dirty tricks in VHDL that can avoid those problems
> without changing the RAM?

This actually has nothing to do with VHDL, it is purely a design
question. 

Since you mention scan insertion, I'm going to assume you're dealing
with an ASIC, not an FPGA. Your comment about requiring a mux makes no
sense if you're writing from a 16-bit bus to a 32-bit RAM port. This is
actually a de-muxing function. Furthermore, you would normally do this
with a 16-bit register to hold one value until the second value is
available and then write both values together as one 32-bit word. I see
nothing here that should be a problem with scan insertion.

If your DPRAM has separate byte or half-word enables, you could deal
with this by tying the upper and lower halves of the Port A data bus
together and using the byte/half-word enables to control the write. This
would eliminate the latency you mention. If you are doing a standard
cell design, you should be able to ask your vendor to generate you a RAM
with the necessary enables. Otherwise, you _are_ going to have one clock
of latency on the first 16-bit value
-- 
Tim Hubberstey, P.Eng. . . . . . Hardware/Software Consulting Engineer
Marmot Engineering . . . . . . .  VHDL, ASICs, FPGAs, embedded systems
Vancouver, BC, Canada  . . . . . . . . . . . http://www.marmot-eng.com

Article: 66833
Subject: Re: Inquiry on configuration file analysis
From: simon <ssteineg@ee.ethz.ch>
Date: Fri, 27 Feb 2004 09:57:52 +0100
Links: << >>  << T >>  << A >>
PO Laprise wrote:
> hurjy wrote:
> 
>> hi all
>>
>> currently I need to analize the FPGA configuration file....(for example,
>> recent Xilinx or Altera device)........how it is organized...
>>
>> Could anybody point me out to the reference....or material
>>
>> thanks in advance
>>
> 
> I know for a fact that Xilinx's "Virtex-II Platform FPGA User Guide" 
> (UG002, not to be confused with the datasheet, which is DS031) contains 
> a good amount of detail on that device's configuration in the 
> Configuration->Configuration Details section, and I suppose that the 
> guides for their other devices have the same type of info.  Also look 
> for xapp151, which covers the Virtex family configuration architecture, 
> which is similar to the Virtex-II, Spartan-II and Spartan-III 
> architectures.  Unfortunately (for the curious and anal amongst us ;), 
> some of the details haven't been made public (or hadn't when I last 
> looked at this stuff), I suppose for IP protection reasons.  I don't 
> know about Altera devices, sorry.
> 

Hi,
Additionally to the above mentioned xapp138 might be useful.
The information you find there apply to virtex. Some are the same for 
virtex-II - some not. good luck finding out which...
One important observation i did: Frame addressing seems to have 
changed... To what? - I haven't found out exactly until now...
If you've made familiar with the command syntax, jBits might be helpful 
to see how your bitstreams configure the device. You will find a helpful 
method called bitstreamToString() which retranslates your .bit file to 
the xilinx command syntax. jBits also offers methods to manually 
manipulate your bitstreams (be careful with these!).

Again, good luck and much fun
Simon


Article: 66834
Subject: Re: Basic jitter from a CPLD (XC7500XL)
From: "Jim" <jim@nospam.com>
Date: Fri, 27 Feb 2004 08:58:48 -0000
Links: << >>  << T >>  << A >>
"Jim Granville" <no.spam@designtools.co.nz> wrote in message
news:yvu%b.28550$ws.3214332@news02.tsnz.net...
> > I do see what you mean about the slew rate of the transformer and its
effect
> > on jitter. We are using a pulse transformer in the transmit side only.
This
> > is to achieve galvanic isolation and is recommend for SPDIF output
circuits
> > in the datasheets and documents we have, e.g.:
> > http://www.cirrus.com/en/pubs/proDatasheet/CS8405A-f.pdf  (800KB) page
34 -
> > consumer output circuit
> > http://www.cirrus.com/en/pubs/appNote/AN134-4.pdf  (70KB)
> > http://www.epanorama.net/documents/audio/spdif.html  (a collection of
SPDIF
> > circuits from various sources)
> >
> > The transformer is a Pulse Engineering PE-65812 and is recommended by
Cirrus
> > Logic for SPDIF transmission. Hopefully this means jitter from the
> > transformer is kept as low as possible. Since the SPDIF outputs of all
> > consumer devices are meant to have a transformer in them (AFAIK), then
they
> > must all have this problem?
> >
> > On the other hand, I have also seen that many DIY audio geeks prefer a
> > direct connection with no transformer, I guess for exactly the reasons
you
> > have suggested. However, since our product is for sale to the general
> > public, I like the idea of galvanic isolation to cover us in case of
> > incorrect connections by users and also failure within the unit itself
that
> > could possibly damage their expensive equipment.
>
>   This mentions Biphase modulation, and that requires clock recovery on
> the RX side. Thus you should choose low jitter Xtal source, (and a high
> accuracy one could also help, if a digital PLL is used in the RX ) but
> the jitter introduced by the cpld will likely be insignifcant.
>   I see the cirrus device specs MAX of 1ns jitter, which may or may not
> include the transformer :)
>
>   The RX clock recovery will lock into the centres of the data bi-phase
> bits, so final clock jitter will be determined mainly by their lock scheme
.
>   Of course, poor jitter, or frequency skew, on the data edges makes the
> clock lock job harder...
> -jg

In fact for the RX side I am using a Cirrus Logic digital audio receiver IC
with in-built PLL, CS8416:
http://www.cirrus.com/en/products/pro/detail/P1005.html
It talks about low-jitter clock recovery. I am using the recovered clock
from this IC to clock the CPLD. I was thinking I could maybe add another
CS8416 and a flipflop to reclock the CPLD's output before routing it through
the transformer, but didn't want to if not necessary (cost & extra
components & something else to worry about!)

-Jim



Article: 66835
Subject: Re: SmartMedia writer (implments using VHDL)....
From: "Kelvin" <kelvin8157@hotmail.com>
Date: Fri, 27 Feb 2004 17:08:02 +0800
Links: << >>  << T >>  << A >>
yuan r u willing to share with the ng how you wired a smartmedia card?

Kelvin



p <chaosdynasty@hotmail.com> wrote in message
news:%Iy%b.626113$ts4.526502@pd7tw3no...
> Hi,
>
> www.sfu.ca/~pyuan/sm/
>
> enjoy!
>
> All the doc are free. But you need to register in the SSFDC forum to get
> them. So I will save everybody the trouble...
>
>
> "Jan Panteltje" <pNaonStpealmtje@yahoo.com> wrote in message
> news:1077817576.568943@news-01.evisp.enertel.nl...
> > On a sunny day (Thu, 26 Feb 2004 09:59:07 GMT) it happened "p"
> > <chaosdynasty@hotmail.com> wrote in <Lrj%b.619427$X%5.315413@pd7tw2no>:
> >
> > >By the way, if anyone wants the SM specifications, I can put them on my
> site
> > >for download
> > Yes please.
> > JP
>
>



Article: 66836
Subject: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
From: "Adarsh Kumar Jain" <Adarsh.Jain@cern.ch>
Date: Fri, 27 Feb 2004 10:30:29 +0100
Links: << >>  << T >>  << A >>
Thanks for your suggestions.
We are able to get something out from the Transceivers.
I was using the JTAGClk and John, as you said, too late.
The board was already designed !
I found another issue with ISE. It was ignoring some of my pin assignments
without giving me any warnings or errors.
Particularly, when i do not instantiate a differential clk buffer for an
incoming differential clk (i was trying to get both the P and N out
directly, just to check), the tool was assigning those pins to some dummy
outputs i have just for simulation and debugging.
And these outputs were basically smashing the incoming clk signal.
Is this an issue with ISE or I was doing sthg fundamentally wrong ?
Thanks
Adarsh

"ram" <ramntn@yahoo.com> wrote in message
news:61c2cc9d.0402261956.7513a7bf@posting.google.com...
> Try using a  pullup for HALTNEG and TRSTNEG in xilinx constraints editor
tool
> Ram
>
> "Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message
>
>  news:<c1l0tn$6mi$1@sunnews.cern.ch>...
> > Hi,
> > I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
> > programming succeeded, the done pin remains low and all the outputs
remain
> > High.
> > I have 8 V2P7s in parallel and they all the drive the same DONE line.
> > What happens when we just program one of the 8 devices with JTAG in such
a
> > setup ?
> > PLEASE HELP !!!
> > Thanks in advance,
> > Adarsh



Article: 66837
Subject: Re: SmartMedia writer (implments using VHDL)....
From: rjd@transtech-dsp.com (rob d)
Date: 27 Feb 2004 01:55:08 -0800
Links: << >>  << T >>  << A >>
"Kelvin" <kelvin8157@hotmail.com> wrote in message news:<403d4dfb$1@news.starhub.net.sg>...
> It is true that it is more difficult to write to FAT16. However, we can
> simplify it.
> 
> Format the SM/MMC/SD with FAT16, and write an empty file to this card. Then,
> with the same FAT16 reader to
> get the addresses. Thirdly, write to this file...do I sound right?
> 
> Best Regards,
> Kelvin
> 
> 
I have done exactly this, using a PCMCIA flash card hosted by my MACH
(lattice) cpld and c51 micro. I used my host to download via rs232 a
binary dump of the flash after formatting to understand the fat format
and where my data started. It is as easy as it sounds. The newer
standards use the same electrical interface and so my design also
worked with smartmedia inserted into a PCMCIA card converter. I could
save a PAL video image (I forget the number of kilobytes) in half a
second.

Rob

Article: 66838
Subject: Re: Free PCI-bridge in VHDL for Spartan-IIE
From: "David Brown" <david@no.westcontrol.spam.com>
Date: Fri, 27 Feb 2004 13:01:04 +0100
Links: << >>  << T >>  << A >>

"Kevin Brace" <k0evinbr1ace@m2ail.c3om> wrote in message
news:c1kbg6$t67$3@newsreader.mailgate.org...
>         The $100 license's US residency requirement is there because if
> a licensee violates the license agreement of personal use, and uses the
> PCI IP core in a commercial project in a foreign country, it is probably
> going to be much harder to stop that than if it happened in this
> country.

That's about as smart as PHB's who insist on buying commercial software and
avoiding open source software as they want to know who they can sue if they
have problems.  I know web-based sales are more anonymous than traditional
shops, but isn't decending from "the customer is always right" to "the
customer is probably a thief" going a bit far?

If someone within the US decides to "steal" your core by using it in a
commercial product, or, heaven forbid, learning something by using it
(academic research being also forbidden), what exactly are you going to do
about it?  The likely culprit will either be someone too small to be worth
bothering about since they would not have bought a full license anyway, or
big enough that lawyers fees and a court battle would cost far more than its
worth.

When you are selling high-price software (and presumably this applies to
your fully licensed core), you can afford to use tight legal licenses and
agreements that will be internationally enforcable.  But for low-price
software available by download, you have to accept that there will be a
certain amount of illegal use of the software.  That's a fact, and you won't
change it.  You won't be able to stop it, and you won't be able to sue the
abusers.  There are a few things you can do to stop this being a problem -
one is to make sure users can see the advantages of using the part legally,
such as better support, upgrades, restrictions in the evaluation parts
functionality (such as limited run time, as used by Altera's OpenCore
system, or lower performance), etc.  Another is to widen your market - if
removing the "US-only" restriction gives you ten times as many paying
customers, would it matter if it also gave you a hundred times as many
pirates?

So please reconsider your attitude here, or perhaps stick to what you know
best (which is presumably VHDL design and pci cores :-) and get someone else
to handle your sales and marketting.




Article: 66839
Subject: Re: Free PCI-bridge in VHDL for Spartan-IIE
From: "David Brown" <david@no.westcontrol.spam.com>
Date: Fri, 27 Feb 2004 13:11:21 +0100
Links: << >>  << T >>  << A >>

"Kevin Brace" <kev0inb1rac2e@m3ail.c4om> wrote in message
news:c1gk8c$v5k$1@newsreader.mailgate.org...
> Hi Marius,
>
> I believe it is theoretically much harder to enforce contractual
> obligation like prohibition of redistribution or the requirement of
> non-profit use if the licensee resides in a foreign country.
>
>

I believe that you have almost no possibility of realisticly enforcing your
contracts with people within the USA - for a start, how do you intend to
identify abusers of your software?  Even if you find someone whom you can
prove has broken the contract, it would cost you far more time and money
that it is worth wasting.  Your market would not be big enough that it would
be worth going after a few cheats as "examples to others".

There are many countries in the rest of the world - and in many of them, it
is much easier and cheaper to enforce such contracts than in the USA.  And
for those countries where it would be harder - if your core is so much
better than other available cores or home-writen cores, and the
people/companies are so corrupt that they would take your core without
paying the full license, then they are going to be able to get hold of it
anyway so you might as well take their $100 rather than nothing.


> Kevin Brace
>
>
>
>
> Marius Vollmer wrote:
> >
> > Kevin Brace <kev0inb1rac2e@m3ail.c4om> writes:
> >
> > > That restriction is there for legal reasons.  If what I am dealing
> > > with wasn't an IP core, there won't be such a restriction.
> >
> > Now I'm curious, too.  What _are_ those legal reasons, precisely?
> >
> > --
> > GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3  331E FAF8 226A D5D4 E405



Article: 66840
Subject: Re: Stratix 2 ALUT architecture patented ?
From: johnjakson@yahoo.com (john jakson)
Date: 27 Feb 2004 06:52:53 -0800
Links: << >>  << T >>  << A >>
Ray Andraka <ray@andraka.com> wrote in message news:<403E90F1.E251EC30@andraka.com>...
> If someone will pay for my time doing it (and be willing to fit in my
> schedule),  I'd be happy to do an app or two targeted to each of the
> families, pulling out all the stops for each one to see which does better
> for that app after all the tricks in my bag are applied.  I'll guarantee the
> internals of the two functionally equivalent designs would be rather
> different.  Of course that would only be a valid comparison for the pieces
> of that application.
> 

I suspect if one does a dozen apps, not all DSP, but a general
variety, and for clock freqs all over the range from 50 to 300Mhz, you
would get wildly varying results for which is better even if X & A
agreed on 2 roughly equal technologies. Just doing same in X devices
produces variations due to different strengths of different families
even if closely derived.

I am willing to put up my 300MHz cpu when it is complete but I suspect
I already know the answer, just look up in specs for who has fastest
DP BlockRam cycle and N (say 12,16) bit adder or 3 4bLUT equiv levels.
But I'd be curious to know A results too.

johnjakson_usa_com

Article: 66841
Subject: comp.arch.fpga : Multisource databus
From: evspronsen <thegodzilla@gmx.net>
Date: Fri, 27 Feb 2004 06:57:52 -0800
Links: << >>  << T >>  << A >>
Hello, 
I'm a bit stuck, help!! A want to make a multisource databus. But i can get done. 
Can someone tell me or point me a example how it is done. I googled and didn't find any thing. 

Thanks, 
 Ernst van Spronsen 



Article: 66842
Subject: Re: Suggestions: Eval/Demo Board.
From: johnjakson@yahoo.com (john jakson)
Date: 27 Feb 2004 07:03:22 -0800
Links: << >>  << T >>  << A >>
Philip Freidin <philip@fliptronics.com> wrote in message news:<n38t30lqn0um4pthhp6us1tparpscbt3m0@4ax.com>...
> On Thu, 26 Feb 2004 11:14:58 -0500, "Invisible One" <Invisible_1@sympatico.ca> wrote:
> >I am looking for a good, reasonably priced FPGA evaluation board for general
> >development.  Any good suggestions?
> >
> >My preference is to Xilinx.
> >
> >J.
> 
> 
>      http://www.fpga-faq.com/FPGA_Boards.shtml
> 
> 
> 
> ===================
> Philip Freidin
> philip@fliptronics.com
> Host for WWW.FPGA-FAQ.COM

Philip, are there any sp3 boards that have shipped AFAYK, NuHorizons
has a $150? board but not sure if available yet. I expect there are
quite a few in the wings sans parts.

johnjakson_usa_com

Article: 66843
(removed)


Article: 66844
Subject: Re: Done Pin Remains Low after JTAG Configuration of V2Pro
From: gabor@alacron.com (Gabor Szakacs)
Date: 27 Feb 2004 07:16:16 -0800
Links: << >>  << T >>  << A >>
Did you try "Enable Internal Done Pipe" in the
startup options?  It would seem that otherwise the
device waits for the Done pin to go high.

Another approach I've used with a similar setup
(except V2, not V2pro) is to generate a dummy project
to load into each of the "unused" parts in the chain.
When all parts are loaded, the Done pin should go high.

> "Adarsh Kumar Jain" <Adarsh.Jain@cern.ch> wrote in message
> 
>  news:<c1l0tn$6mi$1@sunnews.cern.ch>...
> > Hi,
> > I am trying to configure V2P7s with JTAG, but after the iMPACT tool says
> > programming succeeded, the done pin remains low and all the outputs remain
> > High.
> > I have 8 V2P7s in parallel and they all the drive the same DONE line.
> > What happens when we just program one of the 8 devices with JTAG in such a
> > setup ?
> > PLEASE HELP !!!
> > Thanks in advance,
> > Adarsh

Article: 66845
Subject: Re: Stratix 2 ALUT architecture patented ?
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 27 Feb 2004 15:47:32 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <95776079.0402261921.4d7bab99@posting.google.com>,
Jesse Kempa <kempaj@yahoo.com> wrote:

>Just to prevent any confusion (on the Nios stuff): I am assuming by
>"NIOS 2" you mean "Nios II", which is a new product that has been
>announced as part of Altera's 2004 new product line-up, but has not
>yet been released... all I can say about this is to please be patient.
>
>Nios "I" versions up to this point (1.0, 1.1, 2.0... up to the
>just-released v3.2) have been more-or-less an evolution on the
>original processor & instruction set introduced with Nios >3 years
>ago. Probably the most significant amount of architecture-specific
>optimization went into Nios targeting the Apex FPGA family.
>
>While there are architecture tweaks here and there, the CPU remains
>largely unchanged between Stratix & Stratix II... but don't take my
>word for it, generate the respective CPUs and diff the HDL! Really the
>magic behind all of this is in Quartus with synthesis & fitting
>optimizations for each device architecture.

I'm specifically referring to the very HEAVY NIOS optimizations
between 1.1 and 2.0 described in the talk at FPGA this year, on 
" A High Performance 32-bit ALU for Programmable Logic" by Peter
Metzgen of Altera.  (Sorry, don't have it online).

The talk/paper was all ABOUT architectural tweaks/modifications to get
the ALU and other structures to be not only much smaller, but only 2
LUT stages per pipeline stage, and the reason for the large size
reduction between 1.1 and 2.0.  IT really was programmed down at the
LE level, understanding tricks with the carry chain etc.

How much reoptimiation was needed for Stratix II?
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 66846
Subject: Re: Stratix 2 ALUT architecture patented ?
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Fri, 27 Feb 2004 15:51:44 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <403E90F1.E251EC30@andraka.com>,
Ray Andraka  <ray@andraka.com> wrote:
>If someone will pay for my time doing it (and be willing to fit in my
>schedule),  I'd be happy to do an app or two targeted to each of the
>families, pulling out all the stops for each one to see which does better
>for that app after all the tricks in my bag are applied.  I'll guarantee the
>internals of the two functionally equivalent designs would be rather
>different.  Of course that would only be a valid comparison for the pieces
>of that application.

I'll argue that 4 apps acn be fairly good (heck, I did in the past)
for this comparison, if you choose them well.

AES:  Memory/SBOxes, delay chains, LUTs

Smith/Waterman: 16 bit ALU systolic operations

Sythentic datapath:  What does a generic microprocessor-ish datapath
look like

Sythesized processor core:  How do pushbutton hairballs behave.


But doing the first three right is still probbaly 1-3 weeks of
billable time for Ray Andraka (and 2-6 months for lazy gradstudents
like I was).

-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 66847
Subject: Re: Inquiry on configuration file analysis
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Fri, 27 Feb 2004 10:02:24 -0700
Links: << >>  << T >>  << A >>
Hi all,

There are documentation plans to update XAPP138 information for V2/2P in 
the userguide and Spartan3 in an xapp. You can also derive this 
information yourself as well if it is needed urgently. Please contact 
the Xilinx hotline support for help.

Regards, Wei
Xilinx Applications

simon wrote:
> PO Laprise wrote:
> 
>> hurjy wrote:
>>
>>> hi all
>>>
>>> currently I need to analize the FPGA configuration file....(for example,
>>> recent Xilinx or Altera device)........how it is organized...
>>>
>>> Could anybody point me out to the reference....or material
>>>
>>> thanks in advance
>>>
>>
>> I know for a fact that Xilinx's "Virtex-II Platform FPGA User Guide" 
>> (UG002, not to be confused with the datasheet, which is DS031) 
>> contains a good amount of detail on that device's configuration in the 
>> Configuration->Configuration Details section, and I suppose that the 
>> guides for their other devices have the same type of info.  Also look 
>> for xapp151, which covers the Virtex family configuration 
>> architecture, which is similar to the Virtex-II, Spartan-II and 
>> Spartan-III architectures.  Unfortunately (for the curious and anal 
>> amongst us ;), some of the details haven't been made public (or hadn't 
>> when I last looked at this stuff), I suppose for IP protection 
>> reasons.  I don't know about Altera devices, sorry.
>>
> 
> Hi,
> Additionally to the above mentioned xapp138 might be useful.
> The information you find there apply to virtex. Some are the same for 
> virtex-II - some not. good luck finding out which...
> One important observation i did: Frame addressing seems to have 
> changed... To what? - I haven't found out exactly until now...
> If you've made familiar with the command syntax, jBits might be helpful 
> to see how your bitstreams configure the device. You will find a helpful 
> method called bitstreamToString() which retranslates your .bit file to 
> the xilinx command syntax. jBits also offers methods to manually 
> manipulate your bitstreams (be careful with these!).
> 
> Again, good luck and much fun
> Simon
> 


Article: 66848
Subject: Surplus cplds
From: claire_ess@yahoo.co.uk (Only_me)
Date: 27 Feb 2004 09:07:12 -0800
Links: << >>  << T >>  << A >>
Hi,
I am looking for people in the UK who have surplus xilinx xc9536xl -5
in plcc 44 packages that they are willing to sell,also looking for
xilinx Virtex2 2v250's
Thanks in advance.
Claire

Article: 66849
Subject: Re: V2Pro config problems with HSTL_II_DCI pads...
From: Chen Wei Tseng <chenwei.tseng@xilinx.com>
Date: Fri, 27 Feb 2004 10:15:11 -0700
Links: << >>  << T >>  << A >>
John,

Assuming you're using 6.2i software, when DCI IOs are used it's possible 
  for the FPGA to wait and try to match DCI before DCI is released. You 
can tell from your bgn file if match cycle is set prior to the done 
cycle. You can also set bitgen options to not wait for DCI and give that 
a try.

http://toolbox.xilinx.com/docsan/xilinx6/books/data/docs/dev/dev0125_18.html

Regards, Wei
Xilinx Applications

John Providenza wrote:

> I'm seeing a problem configuring a V2Pro-7 part when I add
> HSTL_II_DCI pads to my design. The bit stream downloads,
> but I don't get a 'done' signal.  If I change the pads to
> be HSTL_II, the bitstream downloads OK.  I'm also using
> some HSTL_I_DCI pads, but these don't seem to cause a
> problem.
> 
> Anyone else seen and/or worked-around this problem?
> 
> Thanks!
> 
> John P.




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