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Messages from 67400

Article: 67400
Subject: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
From: jon@beniston.com (Jon Beniston)
Date: 11 Mar 2004 02:25:23 -0800
Links: << >>  << T >>  << A >>
> I also upgraded to Webpack 6.2 and got quite a shock. For the sp3, the
> fmax has shot up to 430MHz overall and the 2 larger blocks besides
> blockram are in the 550MHz ballpark.

If true, then Wow! Your FPGA based CPU is faster than 0.13 ASIC CPUs.

 The timing report is essentially
> same as before, no special warnings but some improvement in compile
> time I was looking for. 

Is that post-synthesis or post-layout? 

> As a crosscheck, I redid the other sp2, v2pro
> and got same results as before. Only the sp3 goes up. 430MHz x 1.3 is
> about 550mips.

On my own designs, I only saw a small increase in sp3 performance when
upgrading to 6.2. But then I don't use XST, so maybe that's whats
giving you the increase. Have you tried other synthesis tools /
physical optimisation tools? They should give you even more
performance.

If you really want to verify it, why don't you run a back annotated
gate-level sim?
 
> I have been contemplating how to license the design, I would like to
> see the final design in its Transputer form open to individuals and
> dot edu, but $ for commercial interest. Trolltech does this with Qt,
> gpl for non commercial Linux and the KDE world while still doing well
> for $ Windows market.
> 
> I am interested in other points of view on this.

Sounds good. One day i intend to license my own (more humble) CPU in
this way. Make sure to use GPL rather than LPGL.

Cheers,
Jon

Article: 67401
Subject: Re: Routing phases after it has completed routing?
From: "Kelvin" <kelvin8157@hotmail.com>
Date: Thu, 11 Mar 2004 20:42:44 +0800
Links: << >>  << T >>  << A >>
sounds reasonable...

Kelvin


"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:xEQ3c.1551$zS4.16753@attbi_s51...
> The design is 100% routed but still doesn't meet timing until the number
in
> parentheses is zero.  The router has to keep ripping up and rerouting
paths
> until timing is met.
> -Kevin
>
> "Kelvin @ SG" <kelvin8157@hotmail.com> wrote in message
> news:404fbb0f$1@news.starhub.net.sg...
> > Hi, there:
> >
> > I have been confused why ISE6 always spend a lot of time after it has
> > completed routing...
> > On the routing log, it seems at Phase 7, it accomplished all routing
> > already...but why Phase 8?
> >
> > Best Regards,
> > Kelvin
> >
> >
> >
> > Phase 9.27
> > Phase 9.27 (Checksum:55d4a77) REAL time: 5 mins 4 secs
> >
> > Writing design to file switch_top.ncd.
> >
> > Total REAL time to Placer completion: 5 mins 7 secs
> > Total CPU time to Placer completion: 5 mins 3 secs
> >
> >
> > Phase 1: 13137 unrouted;       REAL time: 5 mins 10 secs
> >
> > Phase 2: 12564 unrouted;       REAL time: 5 mins 57 secs
> >
> > Phase 3: 3148 unrouted;       REAL time: 6 mins 3 secs
> >
> > Phase 4: 3148 unrouted; (22384)      REAL time: 6 mins 4 secs
> >
> > Phase 5: 3161 unrouted; (22208)      REAL time: 6 mins 5 secs
> >
> > Phase 6: 3161 unrouted; (22208)      REAL time: 6 mins 6 secs
> >
> > Phase 7: 0 unrouted; (22732)      REAL time: 6 mins 27 secs
> >
> > Writing design to file switch_top.ncd.
> >
> > Phase 8: 0 unrouted; (22195)      REAL time: 10 mins 24 secs
> >
> >
> >
>
>



Article: 67402
Subject: Stratix GX experience ?
From: emblab@online.ru (Vlad)
Date: 11 Mar 2004 04:48:58 -0800
Links: << >>  << T >>  << A >>
Dear colleagues,

I'm interested if any of you have had any practical experience with
implementing gigabit protocols with Altera Startix GXs. Any information on
good or bad experience would be truly appreciated.

Also, did you use Altera's GX-evaluation board ever. How did you find it ?

Thanks in advance,
Vlad

Article: 67403
Subject: Re: Oftenly used hardware algorithm for RC4 encryption?
From: Max <mtj2@btopenworld.com>
Date: Thu, 11 Mar 2004 13:06:54 +0000 (UTC)
Links: << >>  << T >>  << A >>
On Thu, 11 Mar 2004 16:35:22 +0800, Kelvin @ SG wrote:

>what is the oftenly used algorithms for RC4 encryption in an FPGA?

Same as in software. The algorithm for RC4 is published by RSA Labs,
but how you implement it is up to you.

>is it true that i have to use at least 256X8X2 registers or RAM?

It's a permutation cypher. I can't remember the block size offhand,
but that sounds about right (particularly with block-chaining).

It's quite a modest RAM requirement, as crypto algorithms go.

-- 
  Max

Article: 67404
Subject: Re: Answering Machine RAM
From: news@rtrussell.co.uk
Date: Thu, 11 Mar 2004 13:11:23 +0000 (UTC)
Links: << >>  << T >>  << A >>
Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote:
: I know; this is off-topic:  I can't figure out why, when there is a brief
: power outage, my answering machine loses time information but retains voice
: messages.  I guess the messages must be stored in FLASH.  Is it just too
: much of a pain to write the time into FLASH as well?

Only you know it was a "brief" power outage.  Arguably storing time
information would be a bad thing, because after a long outage the
machine would come up with a 'valid' but completely wrong time.

Another possible reason is the undesirability of performing regular
writes to FLASH memory (e.g. every second), either because of the
potential for 'fatigue' failure of the device or because of risks
associated with the power failing in the middle of a write or erase
operation.

Richard.
http://www.rtrussell.co.uk/
To reply by email change 'news' to 'richard'

Article: 67405
Subject: Quartus II 3.0 sp1 web, verilog input, memories optimized away ?
From: "raymund hofmann" <filter001@desinformation.de>
Date: Thu, 11 Mar 2004 14:35:06 +0100
Links: << >>  << T >>  << A >>
I am trying this:

module uv_v_filter
  (
    input       clk,
    input       active,
    input[7:0]  y,
    input[7:0]  u,
    input[7:0]  v,

    output      activeout,
    output[7:0] yout,
    output[7:0] uout,
    output[7:0] vout
  );

  parameter log2samplesline=9;
  reg[log2samplesline-1:0]  samplecounter;
  reg[7:0]  yout, uout, vout;

  integer i;

  // line memories

  reg       activeout;

  reg[7:0]  yshift0[0:(1<<log2samplesline)-1];

  reg[7:0]  ushift0[0:(1<<log2samplesline)-1];
  reg[7:0]  ushift1[0:(1<<log2samplesline)-1];

  reg[7:0]  vshift0[0:(1<<log2samplesline)-1];
  reg[7:0]  vshift1[0:(1<<log2samplesline)-1];

  always @(posedge clk)
   begin
    yout<=yshift0[samplecounter];
    uout<=(   u                       * 1
            + ushift0[samplecounter]  * 2
            + ushift1[samplecounter]  * 1
            + 2
         )>>2;
    vout<=(   v                       * 1
            + vshift0[samplecounter]  * 2
            + vshift1[samplecounter]  * 1
            + 2
         )>>2;
    // shift registers / line memories
    if (active)
     begin
      ushift0[samplecounter]<=ushift1[samplecounter];
      vshift0[samplecounter]<=vshift1[samplecounter];

      yshift0[samplecounter]<=y;
      ushift1[samplecounter]<=u;
      vshift1[samplecounter]<=v;

      samplecounter<=samplecounter+1;
     end
    else
     begin
      samplecounter<=0;
     end

    activeout<=active;

   end

endmodule

And Quartus seems to optimize the memories away to a strange number of 22
bit's, targeting a cyclone.
And funny is:
vshift1 gets 20 bits.
yshift0 gets 2 bits

Is Quartus or me the problem ?

Raymund Hofmann



Article: 67406
Subject: Re: very strange error
From: Bruno <bruno.vermeersch@hogent.be>
Date: Thu, 11 Mar 2004 06:08:33 -0800
Links: << >>  << T >>  << A >>
I doubt that this might be the problem, in the START state I make a first check 
to make sure this problem does not occur. I don't think it's possible for count 
to be less than 1.

Article: 67407
Subject: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
From: johnjakson@yahoo.com (john jakson)
Date: 11 Mar 2004 06:38:44 -0800
Links: << >>  << T >>  << A >>
> What exactly is the purpose of this CPU, that is, why would a user want
> this CPU instead of a commercial CPU?  It sounds like it uses a fair
> amount of FPGA real estate, although the speed is impressive.  But it
> requires a memory interface that can keep it fed which will use a lot of
> IOs.  
> 
> Also, what do you mean about it's "Transputer form"?  
> 
> -- 
> 
> Rick "rickman" Collins
> 
>
Hi Rickman

The original and still main intent of the project is to create a new
Transputer. The underlying cpu is just a std RISC with hyperthreading
but the Transputer specifics are process creation and message support
in HW to allow par type programming at very fine granularity as well
as scalability to allow unlimited cpu ganging. The ganging is based on
the simple idea that Transputers are just widgets like any other chips
to be glued together into larger cpus. It works because of the message
passing scheme being similar to HW.

The 2 parts can be separated, ie Transputer like features can be added
to any cpu with KROC port of Occam, but most cpus have very high
swapping context overhead to make it work as well and are missing alot
of the plug an play HW, like links. These specifics can be added onto
the base cpu when it is stable.  I may release them as separate cpus.

You are right about the memory bandwidth. I am planning on using
RLDRAM, a few x $ of DDR, but way more bandwidth, and way less
latency. IE 20ns cycles at 8 banks. 1 bank per cpu seems right as 2nd
level cache. DDR for primary if more needed. The real idea behind
Transputers is to distribute cpus into the memory space so 24b address
space may be fine. Adding 1G memory to each Transputer is like saying
I don't want more computing.

Before FPGAs took of, Transputers were the way to do alot of the same
things (at the higher end) since Occam (Inmos transputer language) was
sort of a HDL for processes. Occam has since evolved into HandelC,
same people but using FPGAs directly.

The technology died out because Inmos didn't have their act together
and FPGAs weren't around to help them prototype. The 2 tchnologies
crossed paths without barely knowing each other. Most all the older
European FPGA houses today came from Transputer backgrounds ie
Nallatech, Sundance & many others. Many of the earlier super computers
used i860, Sparcs, Alphas or whatever as their compute nodes, but used
Transputers for their communications into the backplane. Any
Transputer person today seeing PCI Express, Hypertransport,
hyperthreading, and a dozen other link like technologies would smile
on, already did that 20yrs ago.

Why am I doing this, well I am interested in bringing the Transputer
technology back from the dead, and FPGAs esp sp3 looks incredible to
just waste on conventional cpu design. I also worked at Inmos so I
have the perspective of having beeing part of something great that
made some mistakes. I'd give it a 2nd chance in a heartbeat. Not that
many people around would have the confidence to do this, but I wear
many hats, just takes time.

I want my own Bluegene, I can't afford one. So I put together N cpus
to do the kinds of things only Transputer farms can do, buts thats
another future project. If I scale N Transputers together, the cost is
linear to the basic HW costs. Perhaps sp3-5000 can hold 20+ instances,
but theres power issues to deal with. Ofcourse if I got to 250K units,
I might get a price break too. Now when was the last time anyone
offered an Athlon in N way cpu that scales by instance count. It
doesn't work for most cpus since they are stuck with the shared data
model and expensive NRE for special smp controllers. A couple of
slower Transputers should easily be able to beat 1 faster x86 at any
task. Even Intel is seeing the light. But Intel doesn't understand
Occam and is stuck with x86 rock around its neck.

regards all

johnjakson_usa_com

sorry to sound like blowing my own horn, but the possibilities of FPGA
technology seems far more interesting than the endless x86 drivel on
comp.arch.

Article: 67408
Subject: Re: very strange error
From: Nicolas Matringe <matringe.nicolas@numeri-cable.fr>
Date: Thu, 11 Mar 2004 15:41:58 +0100
Links: << >>  << T >>  << A >>
Bruno a écrit:
> I doubt that this might be the problem, in the START state I make a 
> first check to make sure this problem does not occur. I don't think it's 
> possible for count to be less than 1.

I'm afraid XST (and any other tool) is not clever enough to know this. 
Besides, if length = 1, count will be 0.
Try it :o)

-- 
  ____  _  __  ___
|  _  \_)/ _|/ _ \   Adresse de retour invalide: retirez le -
| | | | | (_| |_| |  Invalid return address: remove the -
|_| |_|_|\__|\___/


Article: 67409
Subject: Re: Answering Machine RAM
From: "Jim" <me@privacy.net>
Date: Thu, 11 Mar 2004 14:44:09 -0000
Links: << >>  << T >>  << A >>
"Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
news:BJQ3c.1317$C51.24342@attbi_s52...
> I know; this is off-topic:  I can't figure out why, when there is a brief
> power outage, my answering machine loses time information but retains
voice
> messages.  I guess the messages must be stored in FLASH.  Is it just too
> much of a pain to write the time into FLASH as well?  If it can't be
written
> into FLASH, couldn't it use a small cap to back up the volatile RAM?
Maybe
> I shouldn't expect too much for $25.
> -Kevin
>

I find this particular issue a PITA too, especially as I have to find the
damn user manual everytime I want to set the time on my answerphone - #*55
or whatever I have to press to get it into time-set mode.

Rather than FLASH, wouldn't the normal approach be to fit battery-backup for
the real-time clock? It would mean very occassional battery replacement but
it would probably last 5 years or so, by which time they'd likely call the
product obsolete ;)

Jim





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Article: 67410
Subject: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
From: johnjakson@yahoo.com (john jakson)
Date: 11 Mar 2004 06:49:26 -0800
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote in message news:<404FE5F4.146E6CE4@yahoo.com>...
> john jakson wrote:
> > 
> > A while back I mentioned I'd post an update on progress for this R3
> > hyperthreaded cpu project.
> > 
>  ......
> > 
> > Licensing
> > I have been contemplating how to license the design, I would like to
> > see the final design in its Transputer form open to individuals and
> > dot edu, but $ for commercial interest. Trolltech does this with Qt,
> > gpl for non commercial Linux and the KDE world while still doing well
> > for $ Windows market.
> > 
> > I am interested in other points of view on this.
> 

I forgot to say the following.

If sp3 really can do what Webpack 6.2 says it can, I think we have
just crossed another of those unmarked milestones in history where
FPGAs can actually do more than an ASIC team can inspite of the fact
that FPGAs only simulate HW fabric.

It is now possible for cpu designers to build computers with far more
interesting architectures in far less time than ASIC teams could ever
concieve. FPGA foundry does all the hard work of making the BlockRams
and logic fabric go as fast as most ASIC cell designs and architects
put it together.

Just how fast does nVidia gpu work, only at 300MHz or so, but they
probably get to use a couple of times more logic per pipeline, but I
bet their memories are still 300MHz. There aren't that many ASIC guys
working on anything faster than that. The only thing ASICs still have
going is the sheer possibility to put even vaster amounts of stuff
onto chips and at lower costs if marketing can sell millions of em.

congrats to sp3 if its true.

Article: 67411
Subject: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
From: Marius Vollmer <marius.vollmer@uni-dortmund.de>
Date: Thu, 11 Mar 2004 16:30:37 +0100
Links: << >>  << T >>  << A >>
johnjakson@yahoo.com (john jakson) writes:

> A couple of slower Transputers should easily be able to beat 1
> faster x86 at any task.

Hmmm, not at _any_ task, I'd say.  Some tasks might not be
parallelizable enough.  And even if they are, you still need people to
write these parallel programs, which is very much harder than writing
sequential programs.

I don't see anyone rewriting their HDK synthesis tools, for example,
to take advantage of massive fine-grain parallelism to speed them up.
Heck, they don't even take advantage of the widely existing dual-CPU
SMP, right?

But, your project sounds mighty cool.  By all means, do it, and
release it with the GPL! :-)

Article: 67412
Subject: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
From: johnjakson@yahoo.com (john jakson)
Date: 11 Mar 2004 07:35:43 -0800
Links: << >>  << T >>  << A >>
jon@beniston.com (Jon Beniston) wrote in message news:<e87b9ce8.0403110225.313772a3@posting.google.com>...
> > I also upgraded to Webpack 6.2 and got quite a shock. For the sp3, the
> > fmax has shot up to 430MHz overall and the 2 larger blocks besides
> > blockram are in the 550MHz ballpark.
> 
> If true, then Wow! Your FPGA based CPU is faster than 0.13 ASIC CPUs.
> 

Only because of HT and 3 level of LUT logic. HT means the pipelines
are mostly independant but cyclic like the spokes of a wheel. Just
like DSP (which is what I have been doing alot of over the years since
my Inmos days).

>  The timing report is essentially
> > same as before, no special warnings but some improvement in compile
> > time I was looking for. 
> 
> Is that post-synthesis or post-layout? 
> 

Post synth.

> > As a crosscheck, I redid the other sp2, v2pro
> > and got same results as before. Only the sp3 goes up. 430MHz x 1.3 is
> > about 550mips.
> 
> On my own designs, I only saw a small increase in sp3 performance when
> upgrading to 6.2. But then I don't use XST, so maybe that's whats
> giving you the increase. Have you tried other synthesis tools /
> physical optimisation tools? They should give you even more
> performance.
> 

Perf is surely due to 3 levels of LUT or 2 mux levels etc. 

Don't have Symplify or full ISE budget, but would gladly accept a free
license if anyone is listening. email at bottom.


> If you really want to verify it, why don't you run a back annotated
> gate-level sim?
> 

Will do as soon as Verilog source is complete. The Visual C env is
much easier to set up testing for partial blocks than any Verilog env
I used. C can be used to create "should do same as fn()s" in a jiffy.
Can also link it into other tools like the upcoming assembler,
compiler, ucf maker etc etc. Also C  allows me to create complex logic
in C for getting something to work 1st, when it does, turn it back
into HDl RTL form. Worked well for me for 20yrs.


> > I have been contemplating how to license the design, I would like to
> > see the final design in its Transputer form open to individuals and
> > dot edu, but $ for commercial interest. Trolltech does this with Qt,
> > gpl for non commercial Linux and the KDE world while still doing well
> > for $ Windows market.
> > 
> > I am interested in other points of view on this.
> 
> Sounds good. One day i intend to license my own (more humble) CPU in
> this way. Make sure to use GPL rather than LPGL.
> 
> Cheers,
> Jon


Not a big fan of GPL. If no $ licenses are forthcoming, I will fold
the them both into MIT/BSD and let the world rip into it.

johnjakson_usa_com

Article: 67413
Subject: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
From: "Tim" <tim@rockylogic.com.nooospam.com>
Date: Thu, 11 Mar 2004 15:43:25 -0000
Links: << >>  << T >>  << A >>
john jakson wrote:
>                          Also C  allows me to create complex logic
> in C for getting something to work 1st, when it does, turn it back
> into HDl RTL form. Worked well for me for 20yrs.

Or do it in Pascal/Delphi and you are just a hop and a skip from
VHDL.  And if _that_ isn't a controversial sentence....



Article: 67414
Subject: Re: Xilinx differential output voltage is adjustable.
From: Austin Lesea <austin@xilinx.com>
Date: Thu, 11 Mar 2004 07:49:49 -0800
Links: << >>  << T >>  << A >>
Symon,

Other than to set the level to 1X, or 2X, and to trim the current 
sources, that is all there is.  It is not a programmable D/A converter.  
I am afraid that all your bit twiddling will do you no good at all.

Austin


Symon wrote:

>Austin,
>Cool as chips! So, how about letting us know on CAF what those mystery
>bits actually do? It seems that they control both the common mode
>voltage and the differential voltage. But, which bits control which
>characteristics? Please don't make me experiment myself! You could
>save me a host of AC coupling caps!
>
>Of course, I don't expect guaranteed specs. However, I'm surprised
>that Xilinx doesn't tout this as a unique selling point, especially as
>there are so many differential signalling standards emerging as supply
>voltages continue to fall.
>
>Thanks, Symon.
>
>
>Austin Lesea <austin@xilinx.com> wrote in message news:<c2npfg$dkt1@cliff.xsj.xilinx.com>...
>  
>
>>Symon,
>>
>>Yes, it does, and yes they all work similarly.
>>
>>Austin
>>
>>    
>>

Article: 67415
Subject: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
From: nweaver@ribbit.CS.Berkeley.EDU (Nicholas C. Weaver)
Date: Thu, 11 Mar 2004 15:51:34 +0000 (UTC)
Links: << >>  << T >>  << A >>
In article <adb3971c.0403110735.71e1b6e8@posting.google.com>,
john jakson <johnjakson@yahoo.com> wrote:
>jon@beniston.com (Jon Beniston) wrote in message
>news:<e87b9ce8.0403110225.313772a3@posting.google.com>...
>> > I also upgraded to Webpack 6.2 and got quite a shock. For the sp3, the
>> > fmax has shot up to 430MHz overall and the 2 larger blocks besides
>> > blockram are in the 550MHz ballpark.
>> 
>> If true, then Wow! Your FPGA based CPU is faster than 0.13 ASIC CPUs.
>> 
>
>Only because of HT and 3 level of LUT logic. HT means the pipelines
>are mostly independant but cyclic like the spokes of a wheel. Just
>like DSP (which is what I have been doing alot of over the years since
>my Inmos days).

Actually, thats not hyperthreading/SMT, thats
interleaved-multithreading or C-slowing.  See Chapter 11 and Appendix
B:

http://www.cs.berkeley.edu/~nweaver/nweaver_thesis.pdf

It is a big win in FPGA-based CPUs if you can't get your forwarding
path small enough.
-- 
Nicholas C. Weaver                                 nweaver@cs.berkeley.edu

Article: 67416
Subject: what exactly means fanout ?
From: ccoutand@hotmail.com (chris)
Date: 11 Mar 2004 08:03:43 -0800
Links: << >>  << T >>  << A >>
Fanout/fanin are terms that appear everywhere in the FPGA
literatures but I can not really find out what it exactly means.
Is someone can enlighten me on this subject ?
Thanks.
Christophe.

Article: 67417
Subject: Altera, Cyclone: pin not connected warning
From: "Pszemol" <Pszemol@PolBox.com>
Date: Thu, 11 Mar 2004 10:11:26 -0600
Links: << >>  << T >>  << A >>
Hi,
I have been working for a little time with Altera Cyclone part
and I have my project almost ready to go. I am in the process
of cleaning things up and I need to review all warnings I got
from the building process.
One of them is "Warning: Pin XXX not connected" - it is right,
I have a track with signal on PCB going into the Altera part 
but later on I decided to not use it in my FPGA design...

What is the common practice of dealing with such pins to clear
this warning and do not short this pin with signal to ground/vcc? 

I hate the practice of ignoring any "stupid" warnings because it
quiets my sensitivity for wornings which are potential errors.
When I write any piece of software I try to clean it the way
no warning is reported during the build process. I want the same
happened in Quartus software during my FPGA design synthesis.

Thanks for any input.

Article: 67418
Subject: Re: Quartus II 3.0 sp1 web, verilog input, memories optimized away
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 11 Mar 2004 08:36:18 -0800
Links: << >>  << T >>  << A >>
raymund hofmann wrote:

> And Quartus seems to optimize the memories away to a strange number of 22
> bit's, targeting a cyclone.
> And funny is:
> vshift1 gets 20 bits.
> yshift0 gets 2 bits
> 
> Is Quartus or me the problem ?

Consider writing a verilog testbench and siming your code.
If it doesn't sim as expected, then debug the code
until it sims ok.

       -- Mike Treseler


Article: 67419
Subject: Re: very strange error
From: Mike Treseler <mike_treseler@comcast.net>
Date: Thu, 11 Mar 2004 08:47:38 -0800
Links: << >>  << T >>  << A >>
> Bruno a écrit:
> 
>> I doubt that this might be the problem, in the START state I make a 
>> first check to make sure this problem does not occur. I don't think 
>> it's possible for count to be less than 1.

Try running a modelsim compile (vcom test.vhd).
This will give you better syntax error messages.

         -- Mike Treseler


Article: 67420
Subject: Re: what exactly means fanout ?
From: "Leon Heller" <leon_heller@hotmail.com>
Date: Thu, 11 Mar 2004 16:50:30 -0000
Links: << >>  << T >>  << A >>

"chris" <ccoutand@hotmail.com> wrote in message
news:33923a80.0403110803.4f889814@posting.google.com...
> Fanout/fanin are terms that appear everywhere in the FPGA
> literatures but I can not really find out what it exactly means.
> Is someone can enlighten me on this subject ?
> Thanks.
> Christophe.

Fanout basically means the number of inputs that may be driven by an output.
An excessive number of inputs will load down the output and it won't work
reliably.

Leon



Article: 67421
Subject: Re: Dual-stack (Forth) processors
From: nospaambrad1@tinyboot.com (Brad Eckert)
Date: 11 Mar 2004 08:54:58 -0800
Links: << >>  << T >>  << A >>
rickman <spamgoeshere4@yahoo.com> wrote in message news:<404FDFE5.4961E719@yahoo.com>...
> I am aware
> that you market an HDL version of an older Forth processor, but I expect
> that is not well optimized for FPGA implementation.  
> 
From what I've seen on the MPE web site, the RTX2000 core runs
reasonably fast in an FPGA. About the same speed as my processor. The
stacks use block RAM, so I would expect it to fit reasonably well in
an FPGA. Maybe Stephen can tell us how many Spartan II slices it uses.

The RTX2000 is an old design, but newer isn't necessarily better. It
was designed back when hardware was expensive and it turned out very
well.

--
Brad

Article: 67422
Subject: System Ace: can not program Avnet V2P7 board
From: John Black <black@eed.com>
Date: Thu, 11 Mar 2004 10:08:32 -0700
Links: << >>  << T >>  << A >>
Hi,
  I have an Avnet V2P7 development board, it is so strange that I can
not load my design via System Ace CF card, the "Sys Ace Error" light is
always on. The board layout is not complex in that SysAce is the 1st
device in JTAG chain, V2P7 as the 2nd, then a PROM and Spart2e. So there
should be no trick in generating ACE file in iMPACT: just add the design
file,  and that's it.
   Does anyone else seeing similar problem?
   I am using ISE 6.2 on Windows 2000.

Thanks a lot!


Article: 67423
Subject: Re: licence for Xilinx 2.1i
From: Brian Philofsky <brian.philofsky@no_xilinx_spam.com>
Date: Thu, 11 Mar 2004 10:28:04 -0700
Links: << >>  << T >>  << A >>


> Can the webpack tools be used to synthesize the design to an XNF or EDIF
> file to use in the ISE 4.1 tool?  

No, not for the XC4000 families.  That is why there is no synthesis tool 
in the Classic version of the software.  XST can only target 
Virtex/Spartan-II and later architectures and was never made to work 
with the older devices.  If it was that easy, we would have just thrown 
the synthesis tool in there.

--  Brian


Article: 67424
Subject: Re: 300MHz spartan3 cpu update , and Webpack6.2 shocker
From: rickman <spamgoeshere4@yahoo.com>
Date: Thu, 11 Mar 2004 12:33:46 -0500
Links: << >>  << T >>  << A >>
john jakson wrote:
> 
> rickman <spamgoeshere4@yahoo.com> wrote in message news:<404FE5F4.146E6CE4@yahoo.com>...
> > john jakson wrote:
> > >
> > > A while back I mentioned I'd post an update on progress for this R3
> > > hyperthreaded cpu project.
> > >
> >  ......
> > >
> > > Licensing
> > > I have been contemplating how to license the design, I would like to
> > > see the final design in its Transputer form open to individuals and
> > > dot edu, but $ for commercial interest. Trolltech does this with Qt,
> > > gpl for non commercial Linux and the KDE world while still doing well
> > > for $ Windows market.
> > >
> > > I am interested in other points of view on this.
> >
> 
> I forgot to say the following.
> 
> If sp3 really can do what Webpack 6.2 says it can, I think we have
> just crossed another of those unmarked milestones in history where
> FPGAs can actually do more than an ASIC team can inspite of the fact
> that FPGAs only simulate HW fabric.
> 
> It is now possible for cpu designers to build computers with far more
> interesting architectures in far less time than ASIC teams could ever
> concieve. FPGA foundry does all the hard work of making the BlockRams
> and logic fabric go as fast as most ASIC cell designs and architects
> put it together.
> 
> Just how fast does nVidia gpu work, only at 300MHz or so, but they
> probably get to use a couple of times more logic per pipeline, but I
> bet their memories are still 300MHz. There aren't that many ASIC guys
> working on anything faster than that. The only thing ASICs still have
> going is the sheer possibility to put even vaster amounts of stuff
> onto chips and at lower costs if marketing can sell millions of em.
> 
> congrats to sp3 if its true.

I will say your goals are optimistic at least.  If you are doing this as
a hobby, then fine.  But if you are serious about marketing a CPU or
core, then you have a long road ahead of you.  But then maybe you
realize that and are up to the task.  

One thing I don't quite get about the idea of everyone rolling their own
CPU is the effort required.  Clearly the automotive companies have a
high enough volume to justify designing their own CPUs and SOCs.  But
mostly they just go to a chip company and ask, "what can you build for
us?"  This is because there is a lot of work involved in doing a new
architecture.  So why would other companies want to make such a large
investment in a custom CPU design even if they don't have to build an
ASIC to get it built? 

I don't want to doubt that you are seeing the results you claim.  But
Xilinx has publicly said that the Sp3 is not as fast as the VII/VIIpro. 
So unless you can get the same or better results targeting the Virtex
family, I suspect your results are anomolous.  

But keep us informed, this is very interesting.  

-- 

Rick "rickman" Collins

rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.

Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design      URL http://www.arius.com
4 King Ave                               301-682-7772 Voice
Frederick, MD 21701-3110                 301-682-7666 FAX



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