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Just a thoght: Did you specify JTAG clock as the startup clock when generating the bit file? Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chips "Joelle" <joelle_yf@yahoo.ca> wrote in message news:26449685.0404032118.3f163a01@posting.google.com... > I am using iMPACT trying to download to a Spartan II-E FPGA on a > digilent D2E board, but for some reason every time I download this > particular code's bit file I got "Programming Failed". I have > downloaded other bit files and they programmed fine but this > particular file I have problem with. All the synthesis and place and > route steps were fine. > > PROGRESS_START - Starting Operation. > Validating chain... > Boundary-scan chain validated successfully. > Validating chain... > Boundary-scan chain validated successfully. > '1':Programming device... > done. > INFO:iMPACT:579 - '1': Completed downloading bit file to device. > INFO:iMPACT:580 - '1':Checking done pin ....done. > '1': Programming terminated, Done did not go high. > PROGRESS_END - End Operation. > Elapsed time = 9 sec.Article: 68426
Hi, there: I am reading some open source codes and found this KCPSM...what is that? Is it readable and modifiable? Kelvin -- Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E Devices -- -- Version : 1.00c -- Version Date : 14th August 2002 -- -- Start of design entry : 2nd July 2002 -- -- Ken Chapman -- Xilinx Ltd -- Benchmark House -- 203 Brooklands Road -- Weybridge -- Surrey KT13 ORH -- United Kingdom -- -- chapman@xilinx.com ---------------------------------------------------------------------------- -------- -- -- Start of Main Architecture for KCPSM -- architecture macro_level_definition of kcpsm is -- ---------------------------------------------------------------------------- -------- -- -- Components used in KCPSM and defined in subsequent entities. -- ---------------------------------------------------------------------------- --------Article: 68427
Jim Granville wrote: > Subroto Datta wrote: > > <snip> > >>> Not really. >>> I was told the purchased full version of Quartus runs forever. >>> It then doesn't support the latest chips though. >>> >>> Rene >> >> >> Rene is correct. The full version of Quartus received when an annual >> subscription is purchased, will run forever, with the license provided at >> the time of the subscription purchase. You do NOT have to renew your >> license annually to use the version of Quartus that you received as >> part of >> the subscription. >> >> For example, lets say you purchased an annual subscription for Quartus in >> February 2004. Your license file will contain an entry 2005.02. What this >> means that you will be able to use any version of Quartus released before >> and including February 2005 for as long as you please. This includes the >> versions of Quartus to be released between now and February 2005, >> Quartus II >> 4.0, 4.0 SP1, Quartus II 3.0, Quartus II 2.2, .... > > > Sounds good. Timed licenses have many pitfalls. > One is version control - suppose you archive your source, _and_ the > tools ( as many do, on passing into production), then 3-4 years later > a fix/rev comes along, and suddenly the tools you thought were archived, > are useless.... > Another is the tutor who arrives for the CPLD LAB, only to find that > since last year, the SW has timed out, and he has to scramble to find > someone who knows how to get & fix the license whilst the students > [twiddle their thumbs / study diligently / riot ] <= select appropriate. The reason for the timed licenses it to convince the user to get a full version. After happily using the free web version for several years, I felt compelled to get a full version just for being able to support past projects. As you said, I may have to support a project ten years later. Then I'll have to get an old machine, install the old version of Quartus, and rework the project. It may be for a then popular chip series, not supported any longer. Sure, I could turn back the clock of the old PC ... It is a pity the ownership of an older version is not really honored. The discount for a new version runs out together with the current version. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 68428
okie I understand now...it looks like one of those cute microcontroller stuff...:) Kelvin "Kelvin" <kelvin8157@hotmail.com> wrote in message news:c4p3am$shu$1@mawar.singnet.com.sg... > Hi, there: > > I am reading some open source codes and found this KCPSM...what is that? Is > it > readable and modifiable? > > Kelvin > > > > -- Constant (K) Coded Programmable State Machine for Spartan-II and Virtex-E > Devices > -- > -- Version : 1.00c > -- Version Date : 14th August 2002 > -- > -- Start of design entry : 2nd July 2002 > -- > -- Ken Chapman > -- Xilinx Ltd > -- Benchmark House > -- 203 Brooklands Road > -- Weybridge > -- Surrey KT13 ORH > -- United Kingdom > -- > -- chapman@xilinx.com > > -------------------------------------------------------------------------- -- > -------- > -- > -- Start of Main Architecture for KCPSM > -- > architecture macro_level_definition of kcpsm is > -- > -------------------------------------------------------------------------- -- > -------- > -- > -- Components used in KCPSM and defined in subsequent entities. > -- > -------------------------------------------------------------------------- -- > -------- > >Article: 68429
"Amaury Anciaux" <amaury.anciaux@tiscali.be> wrote in message news:c4gqjm$a54$1@ail.sri.ucl.ac.be... > The bus macro doesn't seem to lack anything, but I discovered that if I route the concerned signal to a "pip" further to the left, the design finally routes. So it seems that the PAR needs to have that first part of the path to route the signal. > > Another question, are the bus macro really compulsory? If I use a custom bus macro, without TBUFs, just to be sure that the signal passes through the same nets, will it work? > I am sure the given bus macro is not the only solution...you may try build a BM with two registers or only four TBUFs, thus only occupies two slices...but the principle of no-crossing of two adjacent module is compulsory...The TBUF is intended to as a precaution for contention I guess...Am I right? Kelvin > Your help was very useful. > > Regards, > Amaury Anciaux > > > Yes, but in this case, even in the final assembly, this signal stays > > unrouted. > > I attach some example files: the NCD routed designs of the two modules, and > > the final assembly. > > The signals conerned are controlL<3> and controlL<7> (in module 1 and final > > assembly). Other unrouted signals in the modules are normal. > Try the following at the command prompt: > > xdl -ncd2xdl bm_v2p_4b.nmc > > This converts the bus macro to an XDL-description. Have a look at the > .XDL-file this generates. For each net, there should be a section where > it specifies which PIPs to use and such. For each net there should be an > attribute like this: > > cfg "_NET_PROP::IS_BUS_MACRO:" , > > If there isn't, par sometimes doesn't route the corresponding output > net. I have no idea why that is... In case this attribute is not set for > the fourth bit of your bus macro, it could help to insert it manually in > the .XDL-file and convert that back to ncd-format: > > xdl -xdl2ncd bm_v2p_4b.xdl > > This gives you an .ncd-file which you have to rename to .nmc to be able > to use it as a macro. > > Don't know if this will help you, but I always had to manually insert > the above attribute for all nets in the macros I did myself in FPGA > Editor. FPGA Editor always seems to "forget" that, for whatever reason. > > BTW, I'm not sure if all of this works satisfactory with ISE6.1/6.2... > When using XDL in ISE6, I always get a warning that "this is a new > revision ncd, some features might be lost" or something. > > > As you can see, they are connected to the same TBUF in both bus macros. > > BTW, do you know if the T input of a TBUF has to be "1" or "0" to be in high > > impedance? > "1" disables the tristate buffer, so "1" for high impedance. > > -- > Best regards, > Sean Durkin > >Article: 68430
Simon Peacock wrote: > Actually.. in a few years all software will be on a one year license.. maybe > not the OS... but MS has already looked into subscription based licenses and > offers them to businesses. > > But the theory behind it... good or bad... is that they have staff to pay... > and people want updates... and tech support ... so is a simple case of > supply and demand... > Xilina and Altera also have free versions so you can get the web pack and > pay nothing... Modelsim even have a free .. if limited version of their > simulator (for xilinx) so its a feast or famine. > > It all comes down to who wants to pay and who complains the most. Altium > (Protel) tried to go subscription based... I was paying about $500 a year in > upgrades before that and I chose when to get the upgrade... the subscription > based was $1000 per year... the result as I think, as many a user also felt > by the mailing list, was that why bother? their last version, although it > has a few bugs (most well known) was extremely stable and very productive, > so we all told Altium that subscription = no more $$$$.. Altium in the end > backed down and you have a choice of $1000 per year and unlimited number of > updates and free next versions or just free service packs and $2000 for the > next revision (when you want it). The subscription of Altium would possibly have worked under different conditions. They didn't have a track of successful support. Meaning they have local distributors with a certain staff. I tried to call them a few times in the past. Their gurus were holding classes, sure, they cannot sit around and for my call. I favour the newsgroups, or newlist approach as you mostly find someone with the knowlewdge. As opposed to the employed experts, they don't do projects (anymore). The newsgroups/list are free and therefore no reson for a subscribtion. Then the product delivered together with the subscription was hmm, buggy. I got a call from Altium last september, whether I wished to continue the till now included subscription. The lady appeared quite shocked when I told her that I once installed DXP but never got to use it. The new version DXP2004 is useable, I'm still exploring. Rene -- Ing.Buero R.Tschaggelar - http://www.ibrtses.com & commercial newsgroups - http://www.talkto.netArticle: 68431
Hi Jim, Two of Altera's newer tools, SOPC Builder and DSP Builder, do not support AHDL, either for importing or generation. Quartus and Max Plus II definitely still support it. -- Pete > <snip> > > Hi Chris, > An earlier poster in this thread made this claim > > ".. AHDL is being abandoned even by Altera's newer tools." > > Can you comment on that ? AHDL will/does support MAX II, for example ? > > I know designers who use AHDL, and find it very productive > in the CPLD space, and there must be large numbers of legacy designs > coded in AHDL out there. > > -jgArticle: 68432
If the Virtex/spartan2 FPGA is set up for master serial mode and has a programmed serial PROM connected this may interfer with boundary scan programming. See Xilinx database record no. 9013 for solutions. Note that currently there are problems with Impact when trying to set the PROM in HIGHZ mode. Bent. "Joelle" <joelle_yf@yahoo.ca> wrote in message news:26449685.0404032118.3f163a01@posting.google.com... > I am using iMPACT trying to download to a Spartan II-E FPGA on a > digilent D2E board, but for some reason every time I download this > particular code's bit file I got "Programming Failed". I have > downloaded other bit files and they programmed fine but this > particular file I have problem with. All the synthesis and place and > route steps were fine. > > PROGRESS_START - Starting Operation. > Validating chain... > Boundary-scan chain validated successfully. > Validating chain... > Boundary-scan chain validated successfully. > '1':Programming device... > done. > INFO:iMPACT:579 - '1': Completed downloading bit file to device. > INFO:iMPACT:580 - '1':Checking done pin ....done. > '1': Programming terminated, Done did not go high. > PROGRESS_END - End Operation. > Elapsed time = 9 sec.Article: 68433
Kelvin wrote: > okie I understand now...it looks like one of those cute microcontroller > stuff...:) I think it's the precursor to what is now known as Picoblaze... And if I'm not wrong, the name is a "backronym", originally meaning Ken Chapman's Programmable State Machine.... JohnArticle: 68434
Hello, does anyone know if it is possible to connect several Xilinx XC9536 CPLD output pins in a Wired-OR configuration? If possible, how can I do it in VHDL? Thanks Best Regards BrunoArticle: 68435
The one I can think of:
if OR_REDUCE(drivers) = '1' then
w <= DRIVE(1)
else
w <= DRIVE(0);
Externally, you would pull-up a line by resistor to Vcc and implement
transistor internally in FPGA:
O <= '0' when A = '0' else 'Z';
cheers.
Article: 68436sanpab@eis.uva.es wrote in message news:<d79abcea.0403310122.4e892b97@posting.google.com>... > Hi all, > > Maybe I'm another Jurasic dinousar. First I used AHDL, a vary good > language (ten years ago), very ease to learn and connections-oriented, > very suitable if you come from schematic tools. > I am too (JurAsic), but not AHDL but HDL from Inmos ( a really great but proprietary in house structural HDL developed in 80 with many features Verilog is just now getting). > Later I learn VHDL. Hard, hard, hard. Ok, it is behavior-oriented > and tool independent (not completelly at the very begining, but what > you want for free?). I'm agree that is very redundant, so complex to > use. > > Finally I have learn Verilog and as all you can supose, I'm a fun of > it: as simple as AHDL and as powerful as VHDL (except about 'generate' > before 2000). > > Anyway, I'm also fun of Xilinx (coming from Altera a few years ago), > so I prefer a simple language, vendor independent, and C-like. > > When will we use C for circuit design? ;-) > Now you are asking to be flamed and accused of witchcraft. Truth is its not so difficult to use C with Verilog (or others). For 1 clock domain all digital, its a lifesaver for rapid 1M cycle sims. But for many N clock designs not so digital, it may well be more trouble than its worth. You can use SystemC for high level modelling but not HW synthesis. regards johnjakson_usa_comArticle: 68437
Ray Andraka <ray@andraka.com> wrote in message news:<406AF4DE.B027EE6B@andraka.com>... > OK, so webcam type stuff. These have a low pixel rate and image size compared to other > video. Bit serial arithmetic works great for this. I think the gradient vector flow > might be a little easier to do. > > YunghaoCheng wrote: > > > Ray Andraka <ray@andraka.com> wrote in message news:<406A644A.67629932@andraka.com>... > > > You didn't mention your image size or pixel rate. Those are a factor in > > > determining the best approach. > > > > > > YunghaoCheng wrote: > > > > > > > Hi folks!! > > > > Now ,I am designing a real-time visual tracking system based on FPGAs. > > > > > > > > The images are captured by the CCD camera, and we do edge detection > > > > by using (Sobel-mask) 2D convolver. > > > > We also use two consecutive image > > > > frames I(k) and I(k-1) to subtracted pixel by pixel ,in order to > > > > find out the moving object. > > > > > > > > A "Moving Edge" is include by doing a logic AND operation between the > > > > subtracted image and the edge image(obtained by Sobel-mask)of the > > > > current frame. > > > > > > > > After finding out the "Moving Edge" we must to extract the object's > > > > shape > > > > by using Active Contour Model(or snake). > > > > > > > > Now I have implemented the "Moving Edge" detection function on > > > > a Xilinx FPGA.The next step is to design the "Snake-Based Outline > > > > Extraction" > > > > function block. I've found a lot of reference papers on the Google > > > > about the > > > > "active contour model" and finally I want to choose two methods--> One > > > > is Greedy algorithm based snake-model and the other one is Gradient > > > > Vector Flow (GVF)based algorithm. > > > > I wonder which one is more suitable for FPGA based architecture > > > > design? > > > > Could anyone can give me some recommendations or you have any other > > > > good ideas > > > > to design the object outline extraction function on FPGA..?? > > > > > > > > Thanks a lot!! > > > > > > -- > > > --Ray Andraka, P.E. > > > President, the Andraka Consulting Group, Inc. > > > 401/884-7930 Fax 401/884-7950 > > > email ray@andraka.com > > > http://www.andraka.com > > > > > > "They that give up essential liberty to obtain a little > > > temporary safety deserve neither liberty nor safety." > > > -Benjamin Franklin, 1759 > > > > Yes .. > > > > The image size is 320x240 and in order to meet a nearly real-time constraint, > > each image frame (320x240) processing time must be less than 34 ms. > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 Yes .. Bit-serial methods can be used to deal with the heavy arithmetic operations in the computing of Gradient Vector and Energy Function. I also found a lot of tutorial materials on your Web site(www.andraka.com) and they gave us some useful information. But now we still face a problem that the GVF method is like one kind of "Optimization Method" and it consumes several iterations before reaching its optimal solution. And the iteration numbers may differ from case by case. My question is that -- "how to design a flexible structure on FPGA?" Flexible means the numbers of iteration can be changed.Article: 68438
An aside: I often set this to value to "2" to balance between "too much" and "too little" information when I'm trying to look at signals in multiple modules. Jason "Barry Brown" <barry_brown@remove_this.agilent.com> wrote in message news:1080922432.565287@cswreg.cos.agilent.com... > In the wave window, click on Tools > Window Preferences, and set the > "Display Signal Path" to 1. Then you can save your wave window setup by > clicking File > Save Format. > > Barry Brown > > > > "Frank van Eijkelenburg" <someone@work.com> wrote in message > news:406d746c$0$65165$d5255a0c@news.versatel.net... > > Hi, > > > > does anyone know if it's possible to display short signal names in the > wave > > window of modelsim. I have for instance a signal > > /gb_eth_tb/ethernet_mac/receive_state in my wave window. How can I get > > modelsim so far that it only displays the name receive_state in the wave > > window. I saw that you can give it a "display name", can this be done by a > > script? > > > > TIA, > > Frank > > > > > >Article: 68439
Hi folks, I want to learn Hardware Verification Language (HVL). Which HVL is the most popular for FPGA design? I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron books. Are there other Hardware Verification Languages? Say I designed something in FPGA with Verilog or VHDL. How do I know that it is time to verify my design with HVL as opposed to Verilog/VHDL testbenches? HendraArticle: 68440
Hendra Gunawan wrote: > Hi folks, > I want to learn Hardware Verification Language (HVL). Which HVL is the most > popular for FPGA design? > I have seen "e" and "Open Vera" from Samir Palnitkar and Janick Bergeron > books. Are there other Hardware Verification Languages? > Say I designed something in FPGA with Verilog or VHDL. How do I know that it > is time to verify my design with HVL as opposed to Verilog/VHDL testbenches? You could also look here : http://research.microsoft.com/fse/asml/ -jgArticle: 68441
what is the minimum software required to take advantage of a virtex II pro (in terms of cost)? just a poor college student trying to learn fpga's. Virtex II pro is obviously a bit excessive, but my main reason for learning fpga's is to begin to do high bandwidth data shuffling. the rocketio seems well suited to that, and i'm hoping with EDK i might actually be able to implement gigabit ethernet within my lifetime. i found a dev kit with EDK for $500. EDK has ISE demo, but i'm not sure how much that will cover me for, ie: if its usable & relatively fully featured. it says the free web pack is not good for any but the simplest of virtex II pro's, presuambly in powerpc core support (which baseline vII pro lacks) this is just for learning, i dont need a license to produce or distribute anything, although it would be nice (not required) if i could eventually like to release some of my work for free online. kit is memec design one featuring xc2vp4: http://www.insight-electronics.com/cgi-bin/bvutf8memec/scripts/local/manuDetailArticle.jsp?catPath=/INSIGHT/AMERICAS/UNITED_STATES/MANUFACTURERS/MD_XILINX/EVALUATION_KITS/Virtex%20Series%20Kits&Manu=10089&isDetailPage=true&EDOID=209000&Div=INSIGHT&Reg=AMERICAS&Country=UNITED_STATES&Lang=EN&PnACountry=UNITED_STATES thanks matt fowleArticle: 68442
Hello all, I have to design a FPGA which is located solely in a small board (DB). The DB is connected to the main board with a connector whose schematic I have (all exhanged signals locations). I am requested to deliver a pinout of my FPGA, can someone tell me which are the constraints of this task? The only constraint I have in mind is that signals belonging to the same bus must be placed to pins that are very close (bit 0 next to bit 1 and so on). The timing of all signals is not critical since the maximum clock frequency of the signals is 78MHz and the technology used is LVTTL. Thanks in advance for your helpArticle: 68443
On Mon, 5 Apr 2004 11:23:36 +0300, "alphaboran" <alphaboran@yahoo.no-spam.com> wrote: >Hello all, > >I have to design a FPGA which is located solely in a small board (DB). The >DB is connected to the main board with a connector whose schematic I have >(all exhanged signals locations). I am requested to deliver a pinout of my >FPGA, can someone tell me which are the constraints of this task? >The only >constraint I have in mind is that signals belonging to the same bus must be >placed to pins that are very close (bit 0 next to bit 1 and so on). This is probably the *worst* pinout from the point of view of ground bounce. Read the guidelines for SSOs in the datasheet. You can have a maximum number of outputs per VCC/GND pair, or a maximum number of outputs per I/O bank. (The datasheet will have the maximum numbers allowable, and this number will differ with the I/O standard used. LVTTL is one of the worst!) Also add grounds to regular I/O pins close to your clock inputs. (Use floorplanner or fpga editor to work out which pins are closest on the die. This isn't always the same as "close" on the BGA balls.) Make your clock inputs differential if possible. IIRC, one of the Xilinx app notes recommended adding grounds to regular I/O pins around the DCMs. Again, use floorplanner or fpga editor to work out which pins these are. Regards, Allan.Article: 68444
Hello, I've designed in an instrument board an ATMEL CPLD. For that purpose I had to use their "low cost" software. First I tried the CUPL tool, but it was too much bugged. Then I used their VHDL "prochip designer" which is based on altium tool and their proprietary fitters. After some fighting with VHDL (my first project) I finally had it all OK with simulation, synthesis and fitting (PAR). I had to work around some strange synthesizer results but finally got it OK. Then came the time of timing analysis, using the vital files provided by their fitter. Again some annoying bugs, like (traced by comparing the vital/edif/fitter equations report files) - generated vital files not compatible with their provided vital library (quickly derived from their fpga library) - some vital outputs with the wrong polarity - some floating vital CPLD internal signals - some *strange* results like DFFs with permanent reset, or permanently disabled CE... OK, so far I think (I've not tested the CPLD as I still don't have the board) I know where the errors are in their outputs and that my final design is OK. I've made a *nice* bug report to ATMEL with all my analysis, my commented sources, their file results, and all that's needed to help them quickly reproduce the bugs, and also an enquiry about whether my analysis and consequently my jedec output files were good or not. All that sent, as requested, to their pld support 2 weeks ago. I had no acknowledge, no answer, not even an evidence of live, despite one reminder a few days ago. Are these guys serious ? Any experience ? Thanks, Fred.Article: 68445
"Fred Bartoli" <fred._canxxxel_this_bartoli@RemoveThatAlso_free.fr_AndThisToo> wrote in message news:40714abb$0$19461$626a14ce@news.free.fr... > Hello, > > I've designed in an instrument board an ATMEL CPLD. > For that purpose I had to use their "low cost" software. > First I tried the CUPL tool, but it was too much bugged. Then I used their > VHDL "prochip designer" which is based on altium tool and their proprietary > fitters. > After some fighting with VHDL (my first project) I finally had it all OK > with simulation, synthesis and fitting (PAR). I had to work around some > strange synthesizer results but finally got it OK. > > Then came the time of timing analysis, using the vital files provided by > their fitter. > Again some annoying bugs, like (traced by comparing the vital/edif/fitter > equations report files) > - generated vital files not compatible with their provided vital library > (quickly derived from their fpga library) > - some vital outputs with the wrong polarity > - some floating vital CPLD internal signals > - some *strange* results like DFFs with permanent reset, or permanently > disabled CE... > > OK, so far I think (I've not tested the CPLD as I still don't have the > board) I know where the errors are in their outputs and that my final design > is OK. > > I've made a *nice* bug report to ATMEL with all my analysis, my commented > sources, their file results, and all that's needed to help them quickly > reproduce the bugs, and also an enquiry about whether my analysis and > consequently my jedec output files were good or not. > All that sent, as requested, to their pld support 2 weeks ago. I had no > acknowledge, no answer, not even an evidence of live, despite one reminder a > few days ago. I've always found Xilinx and Altera support very good for their CPLDs and FPGAs. Perhaps you are using the wrong chips. 8-) LeonArticle: 68446
Hello all,
I'm still working with DSPBuilder. Here's a VHDL problem
that I can fix but don't understand. DSPBuilder.vhd has a line
obj:lpm_add_sub <snip> port map (cin => '1');
Quartus is happy with this, and in fact I use constant port values
in my own VHDL all the time. But Model Technology (Altera Edition 5.7e)
complains:
# ** Error: Actual for formal cin is not a signal.
# ** Error: Value associated with cin does not have a static name.
So first I tried
constant one : std_logic := '1';
...
obj:lpm_add_sub <snip> port map (cin => one);
and got
# ** Error: Actual for formal cin is not a signal.
And finally
signal one : std_logic := '1';
...
obj:lpm_add_sub <snip> port map (cin => one);
which worked.
My questions are:
(1) Why is port map(cin=>'1') not considered OK ?
(2) Is it bad practice to do this ?
Thanks in advance for any pointers.
Btw, The component declaration for lpm_add_sub is
COMPONENT lpm_add_sub
GENERIC ( <snip> );
PORT ( <snip>
cin: IN STD_LOGIC := '0';
<snip>
);
END COMPONENT;
-rajeev-
Article: 68447Hello I am working on some Schematic based Digital Design experiments for a Xilinx CPLD evaluation board. For this I am using Xilinx ISE 5.2i with all associated softwares along with the ECS (Schematic editor). I am facing problems in running a schematic created on one PC on another platform with the SAME XIlinx ISE 5.2i with the SAME Registration code.( The PC Platforms are same too.. Windows XP on INTEL Pentium 4). When the given schematic, successfully complied and tested on the first PC, is transferred using floppy disks from the first PC to the second PC and is copied/ pasted in the ECS editor of the second PC, then during compilation, it aborts and gives errors. I feel this may be due to NETLIST incompatibility of the schematic from the first platform to the other, but I am not sure. I would be extremely grateful if anybody could help me out on this by giving a specific reason for such an error, and steps to overcome this/ or confirm that this method won't work thanks regards Ayan RoyArticle: 68448
iinu@juno.com (ty) writes: > My question is, is there a way to read in these coefficient files? > Currently, I input the coefficients manually into the vhdl code. You could write a small program that generates VHDL package from your coefficients file, using any language that you are familiar with. The less unfamiliar tools you use, the more robust your project becomes. I used the CoreGenerator once to generate boot roms for a CPU design and it sucked mightily. I don't remember the details (luckily), but the thing was difficult to control from a Makefile, I think, it had strange conventions where it wanted its input and output files to be, it needed to start up Java although I didn't need any GUI, etc. Now I just write small programs (often in C) that outputs a VHDL package with the needed constants. Simple, easy, works every time.Article: 68449
Cyrille, The 3 FDRI writes are of different sizes. The easiest thing for you to do is to generate ascii format of the bit file (bitgen option -b) so you can easily find out what the address are. For the same given part, the FAR address and FDRI words will always be the same. Regards, Wei Xilinx Applications Cyrille Lambert wrote: > Hi everybody, > > I have some problem to understand the bitstream, in the application > note XAPP138 (v2.7) it's written page 21, table 9, it appears the > Bitstream Data Frames and CRC command set. In this one, FDRI is > written a first time to 3000 4000h, then the number of data words > needs to be indicated, the data frames are sent (the number relies on > the previous packet Header type 2), the FAR is entered, the next frame > address, and the same thing twice more. > > My questions are: > · The data words number does it have to take in account the pad words > (See XAPP151 (v1.6) p24 "FDRI")? > · The data frames do they need to be divided in three to respect the > 3 packets data or multiply by 3? > · What is the expected value of the next two FDRI? > > Thanks for your contribution, > Cyrille lambert
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